CN114883435A - Flexible solar cell chip and preparation method and application thereof - Google Patents

Flexible solar cell chip and preparation method and application thereof Download PDF

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Publication number
CN114883435A
CN114883435A CN202210419916.5A CN202210419916A CN114883435A CN 114883435 A CN114883435 A CN 114883435A CN 202210419916 A CN202210419916 A CN 202210419916A CN 114883435 A CN114883435 A CN 114883435A
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layer
metal bonding
bonding layer
solar cell
epitaxial
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CN114883435B (en
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王兵
范芳芳
王文开
张文涛
胡丹
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Zhongshan Dehua Chip Technology Co ltd
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Zhongshan Dehua Chip Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/044—PV modules or arrays of single PV cells including bypass diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention relates to a flexible solar cell chip and a preparation method and application thereof, belonging to the technical field of solar cells; according to the chip PI layer, a first metal bonding layer and a second metal bonding layer are arranged in the partial area of the surface of the PI layer, an adhesive layer is arranged in the first metal bonding layer and the second metal bonding layer, the first metal bonding layer and the second metal bonding layer are divided by the adhesive layer, a first epitaxial layer is arranged in the partial area of the surface of the first metal bonding layer, and a second epitaxial layer is arranged in the partial area of the surface of the second metal bonding layer. According to the flexible solar cell chip, the diode and the solar cell chip are integrally formed; thereby saving the treatment process; and the problem of breakage caused in the welding process can not occur, and the production yield is high.

Description

Flexible solar cell chip and preparation method and application thereof
Technical Field
The invention relates to the technical field of solar cells, in particular to a flexible solar cell chip and a preparation method and application thereof.
Background
The flexible solar cell has the advantages of adjustable forbidden band width, light weight, high mass specific power, flexibility, good surface coverage and the like.
When a solar cell array is formed by flexible gallium arsenide solar cells in the related art, in order to avoid failure of the whole cell array caused by problems of single cells, each cell chip is generally provided with a bypass diode which is reversely connected with the cell chip in parallel, the bypass diode adopted in the related art is generally a silicon or gallium arsenide diode and needs to be connected with the cell chip in parallel for welding, and due to the flexible characteristic of the flexible cell chip, breakage is easy to occur in the welding operation process of the bypass diode, so that the production yield is reduced.
Therefore, there is a need to develop a flexible solar cell chip in which the bypass diode does not require a soldering operation.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a flexible solar cell chip, and a bypass diode in the chip does not need to be welded.
The invention also provides a preparation method of the flexible solar cell chip.
The invention also provides application of the flexible solar cell in preparation of the flexible solar cell.
The method comprises the following specific steps: the invention provides a flexible solar cell chip in a first aspect, comprising:
the surface part area of the PI layer is provided with a first metal bonding layer and a second metal bonding layer, glue layers are arranged in the first metal bonding layer and the second metal bonding layer, the first metal bonding layer and the second metal bonding layer are divided by the glue layers, a first epitaxial layer is arranged on the surface part area of the first metal bonding layer, and a second epitaxial layer is arranged on the surface part area of the second metal bonding layer;
the interconnection electrode is arranged on the surface of the glue layer and comprises a first interconnection electrode and a second interconnection electrode, one end of the first interconnection electrode is connected with the surface of the first metal bonding layer, the other end of the first interconnection electrode is connected with the surface of the second epitaxial layer, one end of the second interconnection electrode is connected with the surface of the second metal bonding layer, and the other end of the second interconnection electrode is connected with the surface of the first epitaxial layer.
According to the technical scheme of the flexible solar cell chip, the flexible solar cell chip at least has the following beneficial effects:
according to the flexible solar cell chip, the diode and the solar cell are integrally formed; therefore, the diode does not need to be welded separately in the subsequent process, thereby saving the treatment process; and the breaking problem caused in the welding process can not occur, and the production yield is high (the reject ratio of the working procedure in the related technology is 10% -20%, but the invention can not cause the loss caused by the damage of the diode or the battery chip caused by welding the diode, that is, the yield loss caused by the welding action can not occur any more).
The adhesive layer plays a role in supporting the interconnected electrodes and prevents short circuit when the electrodes are bridged; therefore, it must be insulated by a glue layer. Meanwhile, the problem that the interconnection electrode has larger stress due to overlarge height difference between the solar battery area and the diode area, so that the circuit is broken is solved, and the reliability of electric connection is improved.
According to some embodiments of the invention, the flexible solar cell chip is comprised of a solar cell epitaxial region, a solar cell lower electrode region, a diode epitaxial region, a diode lower electrode region, and an isolation region;
the lower electrode region of the solar cell is electrically connected with the diode epitaxial region through a first interconnection electrode;
the solar cell epitaxial region is electrically connected with the diode lower electrode region through a second interconnection electrode;
the isolation region is used for dividing the solar cell epitaxial region and the diode epitaxial region.
According to some embodiments of the invention, the first metal bonding layer consists of a Pd layer, a Zn layer, an Au layer, and a Cr layer in that order.
According to some embodiments of the invention, the Pd layer of the first metal bonding layer is bonded to the first epitaxial layer.
According to some embodiments of the invention, the first metal bonding layer comprises a Cr layer bonded to a PI layer.
According to some embodiments of the invention, the Pd layer of the first metal bonding layer has a thickness of 40nm to 60 nm.
According to some embodiments of the invention, the Pd layer of the first metal bonding layer has a thickness of 50 nm.
According to some embodiments of the invention, the Zn layer of the first metal bonding layer has a thickness of 80nm to 120 nm.
According to some embodiments of the invention, the Zn layer of the first metal bonding layer has a thickness of 100 nm.
According to some embodiments of the invention, the thickness of the Au layer in the first metal bonding layer is 1600nm to 2400 nm.
According to some embodiments of the invention, the Au layer of the first metal bonding layer has a thickness of 2000 nm.
According to some embodiments of the invention, the Cr layer in the first metal bonding layer has a thickness of 40nm to 60 nm.
According to some embodiments of the invention, the Cr layer in the first metal bonding layer has a thickness of 50 nm.
According to some embodiments of the invention, the second metal bonding layer consists of a Pd layer, a Zn layer, an Au layer, and a Cr layer in that order.
According to some embodiments of the invention, the Pd layer of the second metal bonding layer is bonded to the second epitaxial layer.
According to some embodiments of the invention, the Cr layer is bonded to the PI layer in the second metal bonding layer.
According to some embodiments of the invention, the Pd layer of the second metal bonding layer has a thickness of 40nm to 60 nm.
According to some embodiments of the invention, the Pd layer of the second metal bonding layer has a thickness of 50 nm.
According to some embodiments of the invention, the Zn layer of the second metal bonding layer has a thickness of 80nm to 120 nm.
According to some embodiments of the invention, the Zn layer of the second metal bonding layer has a thickness of 100 nm.
According to some embodiments of the invention, the Au layer of the second metal bonding layer has a thickness of 1600nm to 2400 nm.
According to some embodiments of the invention, the Au layer of the second metal bonding layer has a thickness of 2000 nm.
According to some embodiments of the invention, the Cr layer of the second metal bonding layer has a thickness of 40nm to 60 nm.
According to some embodiments of the invention the Cr layer of the second metal bonding layer has a thickness of 50 nm.
Cr has good adhesion, does not need to be too thick, is mainly Au as a conductive layer, and Zn and Pd are ohmic contact metals.
According to some embodiments of the invention, the interconnection electrode is a Pd layer, a Ge layer, a first Au layer, an Ag layer, and a second Au layer in that order.
The Pd layer and the Ge layer are both ohmic contact metal, the first Au layer participates in certain ohmic contact, the second Au layer is protective metal and prevents Ag from being oxidized, and Ag is metal mainly conducting electricity.
According to some embodiments of the invention, a portion of the Pd layer of the interconnect electrode is in contact with the epitaxial layer.
According to some embodiments of the invention, a portion of the Pd layer of the interconnect cell is in contact with the Au layer of the metal bonding layer.
According to some embodiments of the invention, the thickness of the Pd layer in the interconnect electrode is between 40nm and 60 nm.
According to some embodiments of the invention, the thickness of the Pd layer in the interconnect electrode is 50 nm.
According to some embodiments of the invention, the thickness of the Ge layer in the interconnect electrode is between 80nm and 120 nm.
According to some embodiments of the invention the thickness of the Ge layer in the interconnect electrode is 100 nm.
According to some embodiments of the invention, the first Au layer in the interconnection electrode has a thickness of 400nm to 600 nm.
According to some embodiments of the invention, the first Au layer in the interconnect electrode has a thickness of 50 nm.
According to some embodiments of the invention, the Ag layer in the interconnect electrode has a thickness of 1800nm to 2200 nm.
According to some embodiments of the invention, the Ag layer in the interconnect electrode has a thickness of 2000 nm.
According to some embodiments of the invention, the second Au layer in the interconnection electrode has a thickness of 400nm to 600 nm.
According to some embodiments of the invention, the second Au layer in the interconnect electrode has a thickness of 500 nm.
According to some embodiments of the invention, the glue layer has a thickness of less than 10 μm.
According to some embodiments of the invention, the glue layer has a thickness of 6 μm.
The glue layer mainly plays a role in insulation and support for bridging metal, so that the thickness of the glue layer cannot exceed that of an epitaxial layer, and the epitaxial thickness is not more than 12 mu m; the thickness can be selected to meet the requirements.
According to some embodiments of the invention, the first epitaxial layer comprises, in order:
the device comprises a GaInP cut-off layer, an N-type GaAs ohmic contact layer, a GaInP top battery, a GaAs/GaInP tunnel junction, a GaAs middle battery, a GaAs/GaAs tunnel junction, an AlGaInAs component gradient buffer layer, a GaInAs bottom battery and a P-type GaInAs ohmic contact layer.
According to some embodiments of the invention, the second epitaxial layer comprises, in order:
the device comprises a GaInP cut-off layer, an N-type GaAs ohmic contact layer, a GaInP top battery, a GaAs/GaInP tunnel junction, a GaAs middle battery, a GaAs/GaAs tunnel junction, an AlGaInAs component gradient buffer layer, a GaInAs bottom battery and a P-type GaInAs ohmic contact layer.
According to some embodiments of the invention, the first epitaxial layer surface portion is further provided with an antireflective coating layer.
According to some embodiments of the invention, a partial region of the surface of the first epitaxial layer away from the P-type GaInAs ohmic contact layer is further provided with an antireflective coating layer.
According to some embodiments of the invention, the anti-reflection coating layer is selected from at least one of a titanium dioxide layer, an aluminum oxide layer and a silicon dioxide layer.
According to some embodiments of the invention, the anti-reflection film layer is composed of a titanium dioxide layer and an aluminum oxide layer.
According to some embodiments of the invention, the antireflective coating layer is composed of a titanium dioxide layer and a silicon dioxide layer.
According to some embodiments of the invention, the thickness of the anti-reflection film layer is 100nm to 200 nm.
According to some embodiments of the invention, the titanium dioxide layer has a thickness of 50nm to 60 nm.
According to some embodiments of the invention, the aluminum oxide layer has a thickness of 80nm to 100 nm.
According to some embodiments of the invention, the silicon dioxide layer has a thickness of 80nm to 100 nm.
According to some embodiments of the present invention, the solar cell epitaxial region is formed by sequentially stacking the following layers:
the device comprises a PI layer, a first metal bonding layer, a P-type GaInAs ohmic contact layer, a GaInAs bottom battery, an AlGaInAs component gradient buffer layer, a first GaAs/GaAs tunnel junction, a GaAs middle battery, a second GaAs/GaInP tunnel junction and a GaInP top battery;
the partial area of the surface of the GaInP top battery is provided with an antireflection film; and the rest part region is provided with an N-type GaAs ohmic contact layer.
According to some embodiments of the present invention, the solar cell lower electrode region is formed by sequentially stacking the following layers:
a PI layer and a first metal bonding layer.
According to some embodiments of the present invention, the diode epitaxial region is formed by sequentially stacking the following layers:
the device comprises a PI layer, a second metal bonding layer, a P-type GaInAs ohmic contact layer, a GaInAs bottom battery, an AlGaInAs component gradient buffer layer, a first GaAs/GaAs tunnel junction, a GaAs middle battery, a second GaAs/GaInP tunnel junction, a GaInP top battery and an N-type GaAs ohmic contact layer.
According to some embodiments of the present invention, the diode lower electrode region is formed by sequentially stacking the following layers:
a PI layer and a second metal bonding layer.
According to some embodiments of the present invention, the isolation region is formed by sequentially stacking the following layers:
PI layer and glue line.
The invention provides a preparation method of the flexible solar cell chip, which comprises the following steps:
s1, growing a buffer layer, the epitaxial layer and a part of metal bonding layer on the surface of the substrate; preparing a first prefabricated part;
growing a residual metal bonding layer on the first surface of the PI layer; preparing a second prefabricated part;
s2, bonding the first prefabricated member and the second prefabricated member to obtain a third prefabricated member;
bonding part of the metal bonding layer in the first prefabricated part and the rest part of the metal bonding layer in the second prefabricated part to form a complete metal bonding layer;
s3, attaching an organic bonding layer and a supporting layer to the second surface of the PI layer to obtain a fourth prefabricated member;
s4, carrying out first etching on the fourth prefabricated member to completely remove the substrate; performing second etching to remove part of the epitaxial layer outside the region to form the first epitaxial layer and the second epitaxial layer;
performing third etching to remove the metal bonding layer in a partial area to form the first metal bonding layer, the second metal bonding layer and the through hole, and manufacturing a fifth prefabricated part;
s5, coating an organic glue material in the through hole area of the fifth prefabricated member to form a glue layer; preparing a sixth prefabricated part;
s6, growing an interconnected electrode on the partial surface area of the glue layer in the sixth prefabricated member;
s7, removing the organic bonding layer and the support layer.
According to one technical scheme of the preparation method, the preparation method at least has the following beneficial effects: according to the preparation process, the bypass diode and the solar cell chip are integrated together through the chip preparation process, the manufacture and the reverse parallel connection of the bypass diode are completed while the manufacture of the cell chip is completed, the bypass diode welding is not needed subsequently, the yield loss (10% -20%) caused by the subsequent process is reduced, and meanwhile, the manufactured solar cell chip can meet the requirements of space environment adaptability (high-energy particle irradiation resistance and ultraviolet irradiation resistance).
According to some embodiments of the invention, the metal bonding layer consists of a Pd layer, a Zn layer, an Au layer and a Cr layer in that order.
According to some embodiments of the invention, the Pd layer of the metal bonding layer is bonded to the epitaxial layer.
According to some embodiments of the invention the Cr layer is bonded to the PI layer in the metal bonding layer.
According to some embodiments of the invention, the Pd layer of the metal bonding layer has a thickness of 40nm to 60 nm.
According to some embodiments of the invention, the Pd layer of the metal bonding layer has a thickness of 50 nm.
According to some embodiments of the invention, the Zn layer in the metal bonding layer has a thickness of 80nm to 120 nm.
According to some embodiments of the invention, the Zn layer of the metal bonding layer has a thickness of 100 nm.
According to some embodiments of the invention, the Au layer in the metal bonding layer has a thickness of 1600nm to 2400 nm.
According to some embodiments of the invention, the Au layer of the metal bonding layer has a thickness of 2000 nm.
According to some embodiments of the invention, the Cr layer in the metal bonding layer has a thickness of 40nm to 60 nm.
According to some embodiments of the invention, the Cr layer in the metal bonding layer has a thickness of 50 nm.
According to some embodiments of the invention, the support layer is at least one of a silicon layer, a glass layer, a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer.
The supporting layer is made of rigid material, plays a role of temporary support in the process, and prevents the epitaxial layer from being damaged in the process; meanwhile, after the process is finished, the supporting layer is removed; so that the flexibility of the flexible solar cell chip is not affected.
According to some embodiments of the invention, the substrate is InP.
According to some embodiments of the invention, the support layer has a thickness of 100nm to 5000 nm.
According to some embodiments of the invention, the organic bonding layer is a pyrolytic glue layer or a UV glue layer.
According to some embodiments of the invention, the organic bonding layer has a thickness of 0.5mm to 2 mm.
According to some embodiments of the invention, the organic glue material comprises one of an organic silicone, a resin or a polyimide.
According to some embodiments of the invention, the epitaxial layer comprises, in order:
the solar cell comprises a GaInP cut-off layer, an N-type GaAs ohmic contact layer, a GaInP top battery, a GaAs/GaInP tunnel junction, a GaAs middle battery, a GaAs/GaAs tunnel junction, an AlGaInAs component gradient buffer layer, a GaInAs bottom battery and a P-type GaInAs ohmic contact layer.
According to some embodiments of the invention, the GaInP cut-off layer is located on a side away from the PI layer.
According to some embodiments of the invention, a part of the metal layer in the first preform consists of a Pd layer, a Zn layer and a part of an Au layer.
According to some embodiments of the invention, the thickness of the partial Au layer in the first preform is 800nm to 1200 nm.
According to some embodiments of the invention, the thickness of the partial Au layer in the first preform is 1000 nm.
According to some embodiments of the invention, a part of the metal layer in the second preform consists of a Cr layer and a part of an Au layer.
According to some embodiments of the invention, the thickness of the partial Au layer in the second preform is 800nm to 1200 nm.
According to some embodiments of the invention, the thickness of the partial Au layer in the second preform is 1000 nm.
According to some embodiments of the invention, the partial Au layer of the first preform and the partial Au layer of the second preform are bonded during the bonding process.
According to some embodiments of the invention, the bonding pressure in step S2 is between 40kN and 80 kN.
According to some embodiments of the invention, the bonding pressure in step S2 is 60 kN.
According to some embodiments of the invention, the temperature of the bonding in step S2 is 180 ℃ to 220 ℃.
According to some embodiments of the invention, the temperature of the bonding in step S2 is 200 ℃.
According to some embodiments of the invention, the bonding time in step S2 is 1600S to 2000S.
According to some embodiments of the present invention, the bonding time in step S2 is 1800S.
According to some embodiments of the present invention, the etching solution of the first etching in step S4 is composed of ammonia monohydrate, hydrogen peroxide and water.
According to some embodiments of the present invention, the etching solution for the first etching in step S4 is composed of the following raw materials in parts by mass: 0.8 to 1.2 parts of ammonia monohydrate, 0.8 to 1.2 parts of hydrogen peroxide and 10 parts of water.
According to some embodiments of the present invention, the second etching in step S4 is performed in two steps.
According to some embodiments of the invention, the second etching in step S4 is performed by using a hydrogen chloride solution; and etching by adopting a mixed acid solution.
According to some embodiments of the invention, the hydrogen chloride solution consists of 0.8 to 1.2 parts of hydrogen chloride and 10 parts of water.
According to some embodiments of the invention, the mixed acid solution is comprised of hydrochloric acid, nitric acid, phosphoric acid, hydrogen peroxide, and water.
According to some embodiments of the invention, the mixed acid solution consists of the following preparation raw materials in parts by volume:
1 part of hydrochloric acid, 2 to 4 parts of nitric acid, 2 to 4 parts of phosphoric acid, 3 to 5 parts of hydrogen peroxide and 5 to 7 parts of water.
According to some embodiments of the invention, the mixed acid solution consists of the following preparation raw materials in parts by volume:
1 part of hydrochloric acid, 3 parts of nitric acid, 3 parts of phosphoric acid, 4 parts of hydrogen peroxide and 6 parts of water.
According to some embodiments of the invention, the hydrochloric acid is present in an amount of 30% to 35% by weight.
According to some embodiments of the invention, the nitric acid is present in an amount of 60% to 70% by weight.
According to some embodiments of the invention, the hydrogen peroxide is 20 to 30% by weight.
According to some embodiments of the invention, the volume fraction of phosphoric acid is between 70% and 98%.
According to some embodiments of the present invention, the etching solution for the third etching in step S4 is prepared from the following raw materials: potassium iodide, elemental iodine and water.
According to some embodiments of the invention, the etching liquid for the third etching has a mass volume ratio of potassium iodide to water of 18g to 22 g: 100 mL.
According to some embodiments of the invention, the etching solution for the third etching has a mass-to-volume ratio of iodine to water of 2g to 4 g: 100 mL.
According to some embodiments of the invention, the organic glue material forms a glue layer after curing.
According to some embodiments of the invention, the temperature of the curing is from 70 ℃ to 80 ℃.
According to some embodiments of the invention, the curing time is between 4h and 5 h.
The invention also provides an application of the flexible solar cell chip in preparing a flexible solar cell.
Drawings
Fig. 1 is a schematic top view of a flexible solar cell chip manufactured in example 1 of the present invention.
Fig. 2 is a schematic sectional view of a portion of line a1 in fig. 1.
Fig. 3 is a schematic sectional view of a portion of a line a2 in fig. 1.
Fig. 4 is a schematic view of a partial structure of an epitaxial layer in the flexible solar cell chip manufactured in embodiment 1 of the present invention.
FIG. 5 is a schematic structural view of a third preform in example 1 of the present invention.
FIG. 6 is a schematic structural view of a fourth preform in example 1 of the present invention.
FIG. 7 is a schematic structural view of a fifth preform in example 1 of the present invention.
FIG. 8 is a schematic structural view of a sixth preform in example 1 of the present invention.
FIG. 9 is a schematic structural view of a seventh preform in example 1 of the present invention.
FIG. 10 is a schematic structural view of an eighth preform in example 1 of the present invention.
100. A substrate; 101. a buffer layer; 102. an epitaxial layer; 103. a metal bonding layer; 104. a PI layer; 105. an organic bonding layer; 106. a support layer; 107. a glue layer; 108. an interconnection electrode; 109. and (3) antireflection films.
1021. A GaInP cutoff layer; 1022. an N-type GaAs ohmic contact layer; 1023. a GaInP top cell; 1024. a second GaAs/GaInP tunnel junction; 1025. GaAs middle battery; 1026. a first GaAs/GaAs tunnel junction; 1027. AlGaInAs component gradual change buffer layer; 1028. a GaInAs bottom cell; 1029. a P-type GaInAs ohmic contact layer; 200. a solar cell epitaxial region; 201. and a solar cell lower electrode region.
300. A diode epitaxial region; 301. and a diode lower electrode region.
400. And (4) an isolation region.
Detailed Description
The concept and technical effects of the present invention will be clearly and completely described below in conjunction with the embodiments to fully understand the objects, features and effects of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and those skilled in the art can obtain other embodiments without inventive effort based on the embodiments of the present invention, and all embodiments are within the protection scope of the present invention.
In the description of the present invention, reference to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
Specific examples of the present invention are described in detail below.
Example 1
The embodiment is a flexible solar cell chip and a preparation method thereof.
The top view of the flexible solar cell chip in this embodiment is schematically shown in fig. 1, and the flexible solar cell chip is composed of a solar cell epitaxial region 200, a solar cell lower electrode region 201, a diode epitaxial region 300, a diode lower electrode region 301 and an isolation region 400;
the solar cell lower electrode region 201 is electrically connected with the diode epitaxial region 300 through a first interconnection electrode;
the solar cell epitaxial region 200 is electrically connected with the diode lower electrode region 301 through a second interconnection electrode;
the isolation region 400 is used to separate the solar cell epitaxial region 200 from the diode epitaxial region 300.
The solar cell epitaxial region 200 is formed by sequentially stacking the following layers:
the solar cell comprises a PI layer 104, a first metal bonding layer, a P-type GaInAs ohmic contact layer 1029, a GaInAs bottom cell 1028, an AlGaInAs composition graded buffer layer 1027, a first GaAs/GaAs tunnel junction, a GaAs middle cell 1025, a second GaAs/GaInP tunnel junction 1024 and a GaInP top cell 1023;
the partial area of the surface of the GaInP top battery 1023 is provided with an antireflection film 109; the remaining portion region is provided with an N-type GaAs ohmic contact layer 1022.
The solar cell lower electrode region 201 is formed by sequentially stacking the following films:
a PI layer 104 and a first metal bonding layer.
The diode epitaxial region 300 is formed by sequentially stacking the following layers:
the device comprises a PI layer 104, a second metal bonding layer, a P-type GaInAs ohmic contact layer 1029, a GaInAs bottom battery 1028, an AlGaInAs composition gradient buffer layer 1027, a first GaAs/GaAs tunnel junction, a GaAs middle battery 1025, a second GaAs/GaInP tunnel junction 1024, a GaInP top battery 1023 and an N-type GaAs ohmic contact layer 1022.
The diode lower electrode region 301 is formed by sequentially stacking the following layers:
a PI layer 104 and a second metal bonding layer.
The isolation region 400 is formed by sequentially stacking the following layers:
PI layer 104 and glue layer 107.
The schematic cross-sectional structure of the invention at a part of line a1 in fig. 1 is shown in fig. 2 and is composed of the following layers:
a PI layer 104;
a first metal bonding layer and a second metal bonding layer are arranged on the surface part of the PI layer 104;
the rest area of the surface of the PI layer 104 is also provided with a glue layer 107;
a first epitaxial layer is arranged on the surface part of the first metal bonding layer;
a second epitaxial layer is arranged on the surface part region of the second metal bonding layer;
a first interconnection electrode is arranged on the surface of the adhesive layer 107;
one end of the first interconnection electrode is arranged on the surface of the first epitaxial layer;
the other end of the first interconnection electrode is arranged on the surface of the second metal bonding layer.
The schematic cross-sectional structure of the invention at a part of line a2 in fig. 1 is shown in fig. 3 and is composed of the following layers:
a PI layer 104;
a first metal bonding layer and a second metal bonding layer are arranged on the surface part of the PI layer 104;
the rest area of the surface of the PI layer 104 is also provided with a glue layer 107;
a first epitaxial layer is arranged on part of the surface of the first metal bonding layer;
a second epitaxial layer is arranged on the surface part region of the second metal bonding layer;
a second interconnection electrode is arranged on the surface of the adhesive layer 107;
one end of the second interconnection electrode is arranged on the surface of the second epitaxial layer;
the other end of the second interconnection electrode is arranged on the surface of the first metal bonding layer.
A schematic cross-sectional structure of a portion of the epitaxial layer 102 in the flexible solar cell chip in this embodiment is shown in fig. 4, and is composed of the following layers:
a P-type GaInAs ohmic contact layer 1029, a GaInAs bottom battery 1028, an AlGaInAs composition gradient buffer layer 1027, a first GaAs/GaAs tunnel junction, a GaAs middle battery 1025, a second GaAs/GaInP tunnel junction 1024 and a GaInP top battery 1023;
the partial area of the surface of the GaInP top battery 1023 is provided with an antireflection film 109; the remaining portion region is provided with an N-type GaAs ohmic contact layer 1022.
The preparation method of the flexible solar cell chip in the embodiment comprises the following steps:
s1, providing an N-type GaAs substrate 100 (350-625 μm);
sequentially manufacturing a growth buffer layer 101 (a GaAs layer, 2 mu m), a GaInP cut-off layer 1021 (the thickness is 100nm), an N-type GaAs ohmic contact layer 1022 (the thickness is 300nm), a GaInP top battery 1023 (the thickness is 800nm), a second GaAs/GaInP tunnel junction 1024(25nm), a GaAs middle battery 1025(300nm), a first GaAs/GaAs tunnel junction (25nm), an AlGaInAs component gradient buffer layer 1027(3500nm), a GaInAs bottom battery 1028(3000nm) and a P-type GaInAs ohmic contact layer 1029(300nm) on the surface of an N-type GaAs substrate 100 to obtain an epitaxial layer 102;
sequentially evaporating a 50nm/100nm/1000nm Pd layer/Zn layer/Au layer on the surface of the P-type GaInAs ohmic contact layer 1029 of the epitaxial wafer to prepare a first prefabricated part;
sequentially evaporating a Cr layer/Au layer with the thickness of 50nm/1000nm on the first surface of the PI layer 104 to prepare a second prefabricated part;
bonding the Au layer of the first prefabricated part and the Au layer of the second prefabricated part into a whole in a metal bonding mode (the bonding pressure is 60 kN; the bonding time is 1800s, and the bonding temperature is 200 ℃); forming a metal bonding layer 103; producing a third preform as shown in fig. 5;
s2, pasting a pyrolytic film on the second surface of the PI layer 104 and temporarily bonding the pyrolytic film and the silicon wafer together; a fourth preform as shown in fig. 6 is produced;
s3, using a first etching solution (NH) 4 OH：H 2 O 2 ：H 2 O (mass ratio 1:1:10)) is etched into the GaInP stop layer 1021 on the GaAs substrate 100 higher in the fourth preform; obtaining a fifth preform as shown in fig. 7;
s4, and then using hydrochloric acid solution (HCl: H) 2 The mass ratio of O is 1:10) etching the GaInP cut-off layer 1021 in the partial region of the fifth prefabricated part to expose the N-type GaAs ohmic contact layer 1022; and then, carrying out mesa corrosion on the epitaxial layer 102 to the metal bonding layer 103 by using a mixed acid solution (the mixed acid solution is composed of the following preparation raw materials in parts by volume, namely 1 part of hydrochloric acid (the mass fraction is 35%), 3 parts of nitric acid (the mass fraction is 68%), 3 parts of phosphoric acid (the mass fraction is 85%), 4 parts of hydrogen peroxide (the mass fraction is 30%) and 6 parts of water) to form a solar cell epitaxial region 200, a solar cell lower electrode region 201 (the metal bonding layer 103 is exposed), a diode epitaxial region 300, a diode lower electrode region 201 (the metal bonding layer 103 is exposed), and an isolation region 400 between the diode and the diode for separating the cell from the diode.
Then using KI solution (the preparation raw material of KI solution is KI and I 2 And water; the mass-to-volume ratio of KI to water is 20 g: 100 mL; i is 2 And water massThe product ratio is 2 g: 100mL) of the metal bonding layer 103 of the isolation region 400 is etched to the polyimide film; a sixth preform as shown in fig. 8 is produced.
The reaction equation of potassium iodide solution with Au is as follows:
2Au+I 2 →2AuI；
AuI+KI→KAuI 2 。
s5, coating one of organic silica gels (zhonghao chen optical chemical research institute, adhesive silicone gel GN521) on the isolation area 400 of the sixth preform by using an automatic glue coater, and completing the curing (curing temperature is 75 ℃, curing time is 4h) with a thickness of 6 μm. Forming a seventh preform as shown in fig. 9;
s6, manufacturing Pd/Ge/Au/Ag/Au electrodes (interconnection electrodes 108) with the thickness of 50nm/100nm/500nm/2000nm/500nm on the surfaces of the solar cell epitaxial region 200 of the seventh prefabricated member, the N-type GaAs ohmic contact layer 1022 surface of the diode epitaxial region 300, the solar cell lower electrode metal exposed region, the diode lower electrode exposed region and the glue coating layer 107 surface of the isolation region 400, and manufacturing an eighth prefabricated member shown in the figure 10;
the interconnection electrode 108 includes a first interconnection electrode and a second interconnection electrode;
one end of the first interconnection electrode is in contact with the N-type GaAs ohmic contact layer 1022 of the diode epitaxial region 300, and functions as an N electrode;
the other end of the first interconnection electrode is in contact with the metal bonding layer 103 of the exposed region of the lower electrode of the solar cell, so that the electrical connection with the P-type GaAs ohmic contact layer is realized.
The middle part of the first interconnection electrode grows on the adhesive layer 107, the adhesive layer 107 plays a role of bridging, and the problems that the growth stress of the first interconnection electrode is large and the electrode is broken and the like due to the height difference between the solar cell epitaxial region 200 and the diode lower electrode exposed region in the growth process of the first interconnection electrode are solved; namely, the adhesive layer 107 not only plays a role of isolating the solar cell and the diode, but also plays a role of supporting the first interconnection electrode;
one end of the second interconnection electrode is in contact with the N-type GaAs ohmic contact layer 1022 of the solar cell epitaxial region 200, and functions as an N electrode;
the other end of the second interconnection electrode is in contact with the metal bonding layer 103 of the exposed region of the lower electrode of the diode, so that the second interconnection electrode is electrically connected with the P-type GaAs ohmic contact layer.
The middle part of the second interconnection electrode grows on the adhesive layer 107, the adhesive layer 107 plays a role of bridging, and the problems that the growth stress of the second interconnection electrode is large and the electrode is broken and the like caused by the height difference between the solar cell epitaxial region 200 and the diode lower electrode exposed region in the growth process of the second interconnection electrode are solved; namely, the adhesive layer 107 not only plays a role of isolating the solar cell and the diode, but also plays a role of supporting the second interconnection electrode;
s7, reusing citric acid and H 2 O 2 And H 2 Etching the N-type GaAs ohmic contact layer 1022 in the upper electrode region by using a mixed solution of O (the mass ratio of citric acid to hydrogen peroxide to water is 1:1:10) to expose the top cell; making TiO on the surface of top cell 2 /Al 2 O 3 Antireflection film 109 (TiO) 2 Layer thickness of 50nm, Al 2 O 3 The thickness of the layer is 90 nm);
and then carrying out heat treatment at 180 ℃ for 1min to remove the organic bonding layer 105, thus obtaining the flexible solar cell chip shown in figure 1.
Example 2
The embodiment is a flexible solar cell chip and a preparation method thereof.
The difference between the flexible solar cell chip in this embodiment and embodiment 1 is that:
the pyrolytic film of example 1 was replaced with UV glue (NBD-5172K from Nitto).
The UV glue removing method comprises the following steps: and removing the bonding between the organic bonding layer 105 and the PI layer 104 by UV illumination for 3 min.
Example 3
The embodiment is a flexible solar cell chip and a preparation method thereof.
The difference between the flexible solar cell chip in this embodiment and embodiment 1 is that:
the silicon wafer in example 1 was replaced with a glass wafer.
Example 4
The embodiment is a flexible solar cell chip and a preparation method thereof.
The difference between the flexible solar cell chip in this embodiment and embodiment 1 is that:
the silicone in example 1 was replaced with a resin.
Example 5
The embodiment is a flexible solar cell chip and a preparation method thereof.
The difference between the flexible solar cell chip in this embodiment and embodiment 1 is that:
the silicone in example 1 was replaced with a polyimide solution (from PAA-2, a new material in iran, chang).
Example 6
The embodiment is a flexible solar cell chip and a preparation method thereof.
The difference between the flexible solar cell chip in this embodiment and embodiment 1 is that:
the antireflection film 109 (TiO) in example 1 2 /Al 2 O 3 ) Replaced by an anti-reflection film 109 (TiO) 2 /SiO 2 Wherein, TiO 2 The thickness of the layer is 50nm, SiO 2 Is 100 nm).
In summary, the invention provides a flexible solar cell chip and a manufacturing method thereof, wherein a bypass diode and a cell chip are integrated together through a chip manufacturing process, the manufacturing and the reverse parallel connection of the bypass diode are completed while the manufacturing of the cell chip is completed, the bypass diode welding is not required to be performed subsequently, the yield loss caused by the subsequent process is reduced, and the adopted scheme can meet the requirement of space environment adaptability.
While the embodiments of the present invention have been described in detail with reference to the specific embodiments, the present invention is not limited to the embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art. Furthermore, the embodiments of the present invention and the features of the embodiments may be combined with each other without conflict.

Claims (10)

1. A flexible solar cell chip, characterized in that: the method comprises the following steps:
the surface of the PI layer (104) is provided with a first metal bonding layer and a second metal bonding layer in partial areas, an adhesive layer (107) is arranged in the first metal bonding layer and the second metal bonding layer, the first metal bonding layer and the second metal bonding layer are divided by the adhesive layer (107), a first epitaxial layer is arranged in partial areas of the surface of the first metal bonding layer, and a second epitaxial layer is arranged in partial areas of the surface of the second metal bonding layer;
interconnection electrode (108), interconnection electrode (108) are located the surface of glue film (107), interconnection electrode (108) include first interconnection electrode and second interconnection electrode, the one end of first interconnection electrode meets with the surface on first metal bonding layer, the other end of first interconnection electrode meets with the surface on second epitaxial layer, the one end of second interconnection electrode meets with the surface on second metal bonding layer, the other end of second interconnection electrode meets with the surface on first epitaxial layer.
2. The flexible solar cell chip of claim 1, wherein: the first metal bonding layer sequentially consists of a Pd layer, a Zn layer, an Au layer and a Cr layer; preferably, the first metal bonding layer is composed of a Pd layer, a Zn layer, an Au layer, and a Cr layer in this order.
3. The flexible solar cell chip of claim 1, wherein: the interconnection electrode (108) is sequentially provided with a Pd layer, a Ge layer, an Au layer, an Ag layer and an Au layer.
4. The flexible solar cell chip of claim 1, wherein: the partial area of the surface of the first epitaxial layer is also provided with an antireflection film layer.
5. A method of preparing a flexible solar cell chip according to any one of claims 1 to 4, characterized in that: the method comprises the following steps:
s1, growing a buffer layer (101), an epitaxial layer (102) and a partial metal bonding layer (103) on the surface of a substrate (100); preparing a first prefabricated part;
growing a remaining part of the metal bonding layer (103) on the first surface of the PI layer (104); preparing a second prefabricated part;
s2, bonding the first prefabricated member and the second prefabricated member to obtain a third prefabricated member;
bonding part of the metal bonding layer (103) in the first prefabricated part and the rest of the metal bonding layer (103) in the second prefabricated part to form a complete metal bonding layer (103);
s3, attaching an organic bonding layer (105) and a supporting layer (106) to the second surface of the PI layer (104) to obtain a fourth prefabricated member;
s4, carrying out first etching on the fourth prefabricated member to completely remove the substrate (100); then, carrying out second etching to remove the epitaxial layer (102) in a partial region to form the first epitaxial layer and the second epitaxial layer;
performing third etching to remove the metal bonding layer (103) in a partial area to form the first metal bonding layer, the second metal bonding layer and a through hole, and manufacturing a fifth prefabricated part;
s5, coating an organic glue material in the through hole area of the fifth prefabricated member to form the glue layer (107); preparing a sixth prefabricated part;
s6, growing an interconnected electrode (108) on the surface part of the glue layer (107) in the sixth prefabricated member;
s7, removing the organic bonding layer (105) and the support layer (106).
6. The method of claim 5, wherein: the support layer (106) is a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer or a glass layer.
7. The method of claim 5, wherein: the organic bonding layer (105) is a pyrolytic glue layer or a UV glue layer.
8. The method of claim 5, wherein: the organic glue material comprises one of organic silica gel, resin or polyimide.
9. The method of claim 5, wherein: the bonding pressure in the step S2 is 40 kN-80 KN; preferably, the bonding temperature is 180 ℃ to 220 ℃.
10. Use of a flexible solar cell chip according to any one of claims 1 to 4 for the production of a flexible solar cell.
CN202210419916.5A 2022-04-21 2022-04-21 Flexible solar cell chip and preparation method and application thereof Active CN114883435B (en)

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070096177A1 (en) * 2005-10-03 2007-05-03 Yoichi Okumura Semiconductor Chip Having a Photodiode, Semiconductor Device and Manufacturing Method Thereof
JP2013205991A (en) * 2012-03-27 2013-10-07 Toppan Printing Co Ltd Capacitive touch panel substrate formed on transparent base material and display device
US20150083202A1 (en) * 2012-03-28 2015-03-26 Soitec Manufacture of multijunction solar cell devices
CN105552140A (en) * 2016-01-29 2016-05-04 扬州乾照光电有限公司 High-specific-power GaAs multi-junction flexible thin film solar cell and preparation method therefor
CN108269864A (en) * 2018-01-25 2018-07-10 扬州乾照光电有限公司 A kind of flexible solar battery and preparation method thereof
US20190157497A1 (en) * 2017-11-20 2019-05-23 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Flexible Crystalline Ultra-Thin Si Solar Cells
US20190341512A1 (en) * 2018-05-07 2019-11-07 Amberwave, Inc. Solar cell via thin film solder bond
CN111524984A (en) * 2020-04-20 2020-08-11 中山德华芯片技术有限公司 Flexible gallium arsenide solar cell chip and manufacturing method thereof
CN111725340A (en) * 2020-06-11 2020-09-29 中山德华芯片技术有限公司 Ultrathin flexible gallium arsenide solar cell chip and preparation method thereof
US20210391484A1 (en) * 2020-06-16 2021-12-16 Jinko Green Energy (Shanghai) Management Co., LTD Functional part, photovoltaic module and method for manufacturing photovoltaic module

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070096177A1 (en) * 2005-10-03 2007-05-03 Yoichi Okumura Semiconductor Chip Having a Photodiode, Semiconductor Device and Manufacturing Method Thereof
JP2013205991A (en) * 2012-03-27 2013-10-07 Toppan Printing Co Ltd Capacitive touch panel substrate formed on transparent base material and display device
US20150083202A1 (en) * 2012-03-28 2015-03-26 Soitec Manufacture of multijunction solar cell devices
CN105552140A (en) * 2016-01-29 2016-05-04 扬州乾照光电有限公司 High-specific-power GaAs multi-junction flexible thin film solar cell and preparation method therefor
US20190157497A1 (en) * 2017-11-20 2019-05-23 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Flexible Crystalline Ultra-Thin Si Solar Cells
CN108269864A (en) * 2018-01-25 2018-07-10 扬州乾照光电有限公司 A kind of flexible solar battery and preparation method thereof
US20190341512A1 (en) * 2018-05-07 2019-11-07 Amberwave, Inc. Solar cell via thin film solder bond
CN111524984A (en) * 2020-04-20 2020-08-11 中山德华芯片技术有限公司 Flexible gallium arsenide solar cell chip and manufacturing method thereof
CN111725340A (en) * 2020-06-11 2020-09-29 中山德华芯片技术有限公司 Ultrathin flexible gallium arsenide solar cell chip and preparation method thereof
US20210391484A1 (en) * 2020-06-16 2021-12-16 Jinko Green Energy (Shanghai) Management Co., LTD Functional part, photovoltaic module and method for manufacturing photovoltaic module

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