CN114883343B - Thin film transistor, display substrate and preparation method of thin film transistor - Google Patents
Thin film transistor, display substrate and preparation method of thin film transistor Download PDFInfo
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- CN114883343B CN114883343B CN202210423517.6A CN202210423517A CN114883343B CN 114883343 B CN114883343 B CN 114883343B CN 202210423517 A CN202210423517 A CN 202210423517A CN 114883343 B CN114883343 B CN 114883343B
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- 239000010409 thin film Substances 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 195
- 239000002184 metal Substances 0.000 claims abstract description 195
- 239000004065 semiconductor Substances 0.000 claims abstract description 138
- 239000004020 conductor Substances 0.000 claims abstract description 107
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 238000009413 insulation Methods 0.000 claims abstract 4
- 238000000151 deposition Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 27
- 238000000059 patterning Methods 0.000 claims description 23
- 239000010408 film Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000010849 ion bombardment Methods 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 243
- 238000000034 method Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- -1 and at present Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003631 expected effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
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Abstract
The application discloses a thin film transistor, a display substrate and a preparation method of the thin film transistor, wherein the thin film transistor comprises a buffer layer, an active layer, a gate insulating layer, a gate metal layer, a source metal layer, a drain metal layer and a passivation layer which are sequentially arranged, the gate metal layer, the source metal layer and the drain metal layer are arranged at intervals, the active layer comprises at least two conductor parts and a first semiconductor part, and the two conductor parts are respectively arranged at two ends of the first semiconductor part and are electrically connected with the first semiconductor part; the projection of the grid metal layer covers the first semiconductor part, and the source metal layer and the drain metal layer are respectively connected with the two corresponding conductor parts through the first via hole and the second via hole of the grid insulation layer. The application is to set up conductor portion and semiconductor portion in order to form the active layer, does not need to carry out ion bombardment to the semiconductor layer in order to obtain the semiconductor layer of conductor, avoids the resistance of semiconductor layer of conductor to be big, leads to on-state current insufficient, causes the demonstration uneven.
Description
Technical Field
The application relates to the technical field of display, in particular to a thin film transistor, a display substrate and a preparation method of the thin film transistor.
Background
The characteristics of the oxide semiconductor thin film transistor, such as high mobility, low cost, and suitability for large, medium and small sizes, are sought after by various panel factories, and the thin film transistor display (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) formed by the oxide semiconductor thin film transistor has low power consumption, excellent picture quality, high production yield and other performances, and currently has gradually taken the dominant role in the display field.
In the fabrication of top-gate self-aligned thin film transistors, ion bombardment is generally used to perform a conductive treatment on a semiconductor layer, however, the semiconductor layer that has undergone a conductive treatment is significantly affected in a subsequent process, and the resistance after the conductive treatment is still large, so that the on-state current is not high enough, and the conductive uniformity is poor, so that the semiconductor layer cannot achieve the expected effect.
Disclosure of Invention
The object of the present application is to provide a thin film transistor, a display substrate, and a method for manufacturing a thin film transistor, which do not require a semiconductor layer to be made conductive, and which can reduce resistance by increasing a conductor portion, increase on-state current, and improve display effect.
The application discloses a thin film transistor, which comprises a buffer layer, an active layer, a gate insulating layer, a gate metal layer, a source metal layer, a drain metal layer and a passivation layer; the active layer is arranged on the buffer layer; the grid insulating layer is arranged on the buffer layer and the active layer in a covering mode, and a first via hole and a second via hole are formed in the grid insulating layer; the gate metal layer is arranged on the gate insulating layer; the source electrode metal layer is arranged on the gate insulating layer and is connected with the active layer through the first via hole; the drain electrode metal layer is arranged on the gate insulating layer and is connected with the active layer through the second via hole; the passivation layer is arranged on the gate metal layer, the source metal layer, the drain metal layer and the gate insulating layer in a covering manner; the active layer comprises at least two conductor parts and a first semiconductor part, wherein the two conductor parts are respectively arranged at two ends of the first semiconductor part and are electrically connected with the first semiconductor part; the projection of the grid metal layer covers the first semiconductor part, and the source metal layer and the drain metal layer are respectively connected with the two corresponding conductor parts through the first via hole and the second via hole.
Optionally, the conductor portion includes a transparent conductive film, and the transparent conductive film is formed by indium tin oxide.
Optionally, the conductor part is formed by preparing at least one metal material of molybdenum, titanium, copper, aluminum and the like.
Optionally, the thin film transistor further includes at least two second semiconductor portions, the second semiconductor portions are disposed on the conductor portions, the second semiconductor portions are connected with the first semiconductor portions, and are integrally formed, and the first via hole and the second via hole are connected with the two conductor portions through the corresponding two second semiconductor portions respectively.
Optionally, the thickness of the conductor part is d, wherein
Optionally, the thin film transistor includes a light shielding metal layer, the light shielding metal is disposed on a side of the buffer layer away from the gate insulating layer, a width of the light shielding metal layer is greater than a width of the first semiconductor portion, and the source metal layer is connected to the light shielding metal layer through a third via hole.
The application also discloses a display substrate, which comprises a substrate and the thin film transistor as described in any one of the above, wherein the thin film transistor is arranged on the substrate.
Optionally, the display substrate further includes a first metal layer and a second metal layer, the gate insulating layer further includes a fourth via hole, the second metal layer is connected with the first metal layer through the fourth via hole, the first metal layer and the light shielding metal layer are arranged in the same layer, and the second metal layer, the gate metal layer, the source metal layer and the drain metal layer are arranged in the same layer; the second metal is connected with the first metal layer through a via hole, a conductive layer and a semiconductor layer are arranged between the first metal layer and the second metal layer, the conductive layer and the conductor part are arranged on the same layer, and the semiconductor layer and the first semiconductor part are arranged on the same layer.
The application also discloses a preparation method of the thin film transistor, which is used for preparing the thin film transistor according to any one of the above steps:
forming a buffer layer on a substrate;
depositing a conductor material on the buffer layer, and performing patterning treatment to form at least two conductor parts which are arranged at intervals;
depositing a semiconductor material on the buffer layer and performing patterning treatment to form a first semiconductor part located between two conductor parts;
depositing an insulating material on the buffer layer, the conductor part and the first semiconductor part to form a gate insulating layer, and patterning to form a first via hole and a second via hole;
depositing a metal layer material on the gate insulating layer and patterning to form a gate metal layer, a source metal layer and a drain metal layer which are arranged at intervals; and
depositing a passivation layer material to form a passivation layer covering the gate insulating layer, the gate metal layer, the source metal and the drain metal layer;
the first semiconductor part and the conductor part form an active layer, the projection of the grid metal layer covers the first semiconductor part, and the source metal layer and the drain metal layer are respectively connected with the two corresponding conductor parts through the first via hole and the second via hole.
Optionally, in the step of depositing a conductor material on the buffer layer and performing patterning treatment to form at least two conductor parts arranged at intervals, the conductor material is indium zinc oxide; in the step of depositing a semiconductor material on the buffer layer and performing patterning to form a first semiconductor portion located between two conductor portions, a second semiconductor portion is formed overlying both conductor portions at the same time as the first semiconductor portion.
Compared with the scheme of conducting the original semiconductor layer by using ion bombardment, the method does not need to conduct ion bombardment on the semiconductor layer, and the conductor part is directly formed by using a conductor material at the connecting position of the corresponding source electrode metal layer and the drain electrode metal layer to realize electric connection, so that the phenomenon that the on-state current is insufficient and uneven display caused by large resistance of the conducted semiconductor layer formed by ion bombardment is avoided.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive faculty for a person skilled in the art. In the drawings:
fig. 1 is a schematic view of a thin film transistor according to a first embodiment of the present application;
fig. 2 is a schematic view of a thin film transistor (1) of a second embodiment of the present application;
fig. 3 is a schematic view of a thin film transistor (2) of a second embodiment of the present application;
fig. 4 is a schematic view of a thin film transistor (3) of a second embodiment of the present application;
fig. 5 is a schematic view of a thin film transistor (1) of a third embodiment of the present application;
fig. 6 is a schematic view of a thin film transistor (2) according to a third embodiment of the present application;
FIG. 7 is a schematic view of a display substrate according to a fourth embodiment of the present application;
fig. 8 is a flowchart of a method for manufacturing a thin film transistor according to a fifth embodiment of the present application.
Wherein, 100, the thin film transistor; 110. a buffer layer; 120. an active layer; 121. a first semiconductor portion; 122. a second semiconductor portion; 123. a conductor section; 1231. a transparent conductive film; 130. a gate insulating layer; 131. a first via; 132. a second via; 133. a third via; 134. a fourth via; 140. a gate metal layer; 150. a source metal layer; 160. a drain metal layer; 170. a passivation layer; 180. a light shielding metal layer; 190. a protective layer; 200. a display substrate; 210. a substrate; 220. a first metal layer; 230. a second metal layer; 240. a conductive layer; 250. and a semiconductor layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.
The present application is described in detail below with reference to the attached drawings and alternative embodiments.
As shown in fig. 1, as a first embodiment of the present application, a thin film transistor 100 is disclosed, the thin film transistor 100 including a buffer layer 110, an active layer 120, a gate insulating layer 130, a gate metal layer 140, a source metal layer 150, a drain metal layer 160, and a passivation layer 170; the active layer 120 is disposed on the buffer layer 110, and the gate insulating layer 130 is disposed on the buffer layer 110 and the active layer 120 in a covering manner, and is formed with a first via 131 and a second via 132; the gate metal layer 140 is disposed on the gate insulating layer 130; the source metal layer 150 is disposed on the gate insulating layer 130 and connected to the active layer 120 through the first via 131; the drain metal layer 160 is disposed on the gate insulating layer 130 and connected to the active layer 120 through the second via 132; the passivation layer 170 is disposed on the gate metal layer 140, the source metal layer 150, the drain metal layer 160, and the gate insulating layer 130, where the passivation layer 170 may be one layer or multiple layers, and may be disposed according to actual needs.
The gate metal layer 140, the source metal layer 150 and the drain metal layer 160 are arranged at the same layer and at intervals, the active layer 120 includes at least two conductor portions 123 and a first semiconductor portion 121, and the two conductor portions 123 are respectively arranged at two ends of the first semiconductor portion 121 and electrically connected with the first semiconductor portion 121; the projection of the gate metal layer 140 covers the first semiconductor portion 121, that is, the width of the first semiconductor portion 121 is smaller than or equal to the width of the gate metal layer 140, and of course, the width of the first semiconductor portion 121 may be set larger than the width of the gate metal layer 140, and may be set according to the specific situation, in the case of ensuring that no light is reflected to the first semiconductor portion 121; the source metal layer 150 and the drain metal layer 160 are connected to the corresponding two conductor portions 123 through the first via hole 131 and the second via hole 132, respectively.
The active layer 120 is formed by two conductor portions 123 and one semiconductor portion 123, and compared with the whole semiconductor layer 250 serving as the active layer 120, the resistance value can be further reduced by conducting part of the semiconductor layer 250 by ion bombardment; and the semiconductor surface is physically or chemically damaged to reduce the resistance, so that the difficulty is high, and poor uniformity of conductor formation is easily caused. Therefore, the present application directly selects the conductor portion 123 with a resistance value of 20-80 ohms, and compared with a semiconductor which is usually hundreds or thousands of ohms after being conductive, the resistance value of the conductor portion 123 is far smaller than that of the semiconductor portion 123, so that the on-state current can be improved without ion bombardment by directly adding the conductor portion 123 with a small resistance value, thereby preventing poor current uniformity caused by poor uniformity of ion bombardment conductive, and affecting the display effect.
Further, the first semiconductor layer 250 is formed by preparing indium gallium zinc oxide, the conductor portion 123 includes a transparent conductive film, and the transparent conductive film is formed by preparing indium tin oxide, that is, the material of the conductor portion 123 and the material of the pixel electrode layer are the same, the pixel electrode is transparent and conductive, and the square resistance is only tens or even smaller, so that the resistance of the whole active layer 120 can be greatly reduced. Of course, besides the pixel electrode, other metal layers with good conductivity and small resistance may be used as the conductor 123, and the conductor 123 may be formed by at least one metal material of molybdenum, titanium, copper, aluminum, or the like, that is, a metal layer formed by a single material, or a metal layer formed by mixing two or more materials, and at present, molybdenum and copper are generally mixed as the conductor 123, which not only has good conductivity, but also can save cost and is quite convenient to manufacture.
As shown in fig. 2, unlike the first embodiment, the thin film transistor 100 further includes at least two second semiconductor portions 122, the second semiconductor portions 122 are disposed on the conductor portions 123, the second semiconductor portions 122 are connected to the first semiconductor portions 121 and are integrally formed, the first via holes 131 and the second via holes 132 are respectively connected to the two conductor portions 123 through the corresponding two second semiconductor portions 122, and a distance from a connection point of the first via holes 131, the second via holes 132 and the corresponding conductor portions 123 to one end of the conductor portions 123 away from the first semiconductor portions 121 is between one fourth and one third of a width of the whole conductor portions 123, so that it is possible to avoid that a too small or too large distance between the connection point and the first semiconductor portions 121 affects a conductive effect.
In general, the widths of the second semiconductor portions 122 and the conductor portions 123 are the same such that the distance between the two ends of the two second semiconductor portions 122 that are apart from each other is equal to the distance between the two ends of the two conductor portions 123 that are apart from each other; in this embodiment, no change is actually made to the original semiconductor layer 250, and ion bombardment is not required to make a portion of the semiconductor layer 250 conductive, but a pixel electrode layer is added to two ends of the first conductor 123, so that the resistance values of two ends of the first conductor 123 are reduced.
Of course, the width of the second semiconductor portion 122 may be smaller than the width of the conductor portion 123, as shown in fig. 3; further, the thin film transistor 100 includes a light shielding metal layer 180, where the light shielding metal layer is disposed on a side of the buffer layer 110 away from the gate insulating layer 130, and the width of the light shielding metal layer 180 is greater than the width of the first semiconductor portion 121, and even greater than the distance between two ends of the two second semiconductor portions 122 that are away from each other, and the width of the light shielding metal layer 180 may be adjusted according to practical situations.
Further, as shown in fig. 4, the source metal layer 150 is connected to the light shielding metal layer 180 through a third via hole 133, and the light shielding metal layer 180 not only can play a role of shielding light, preventing the first semiconductor portion 121 from being irradiated by light, but also can serve as one of the gates of the dual-gate TFT, thereby further improving the stability of the TFT. In addition, the second semiconductor portion 122 and the conductor portion 123 near the third via hole 133 may extend to the via hole, so that the source metal layer 150 may be electrically connected to the first semiconductor portion 121 through the first via hole 131 and the third via hole 133, and the on time may be increased.
As shown in fig. 5, as a third embodiment of the present application, the difference between the first embodiment and the second embodiment is that the gate metal layer 140 and the source metal layer 150 and the drain metal layer 160 are not provided in the same layer, the gate insulating layer 130 is only provided on the first semiconductor portion 121, a protective layer 190 is laid on the gate metal layer 140, and the source metal layer 150 and the drain metal layer 160 are further provided on the protective layer 190, and in this embodiment, only two conductor portions 123 are disposed at two ends of the first semiconductor portion 121 to electrically connect the source and the drain.
In addition, the original active layer 120 may not be changed, two conductor portions 123 are added at two ends of the first semiconductor portion 121, i.e. a pixel electrode layer is added between the second semiconductor portion 122 and the buffer layer 110, so as to reduce the overall resistance of the active layer 120, as shown in fig. 6, and in this embodiment or other embodiments, the thickness of the conductor portion 123 is d, whereWhen the conductor portion 123 is a metal layer structure formed by preparing a metal material, a value having a smaller thickness may be selected in the range of d, and when the conductor portion 123 is a transparent conductor film formed by preparing indium zinc oxide, a value having a larger thickness may be selected in the range of d.
As shown in fig. 7, as a fourth embodiment of the present application, a display substrate 200 is disclosed, including a substrate 210 and the thin film transistor 100 according to any of the foregoing embodiments, where the thin film transistor 100 is disposed on the substrate 210, and the display substrate 200 may be an array substrate or a COA substrate.
The display substrate 200 further includes a first metal layer 220 and a second metal layer 230, the gate insulating layer 130 further includes a fourth via 134, the second metal layer 230 is connected to the first metal layer 220 through the fourth via 134, the first metal layer 220 and the light shielding metal layer 180 are disposed in the same layer, and the second metal layer 230 is disposed in the same layer as the gate metal layer 140, the source metal layer 150 and the drain metal layer 160;
the second metal is connected to the first metal layer 220 through a via hole, a conductive layer 240 and a semiconductor layer 250 are disposed between the first metal layer 220 and the second metal layer 230, the conductive layer 240 and the conductor portion 123 are disposed in the same layer, and the semiconductor layer 250 and the first semiconductor portion 121 are disposed in the same layer.
In the case where the conductive layer 240 and the semiconductor layer 250 provided in the first metal layer 220 and the second metal layer 230 are formed in the preparation of the conductive portion 123 and the first semiconductor portion 121, and the first metal layer 220 and the second metal layer 230 form a storage capacitance, the conductive layer and the semiconductor layer 250 also form a storage capacitance with the first metal layer 220 and the second metal layer 230, thereby further increasing the storage capacitance, and being advantageous in improving the pixel charging efficiency when the pixels of the display panel are charged.
As a fifth embodiment of the present application, as shown in fig. 8, there is disclosed a method for manufacturing a thin film transistor for manufacturing the thin film transistor according to any one of the above embodiments, comprising the steps of:
s1: forming a buffer layer on a substrate;
s2: depositing a conductor material on the buffer layer, and performing patterning treatment to form at least two conductor parts which are arranged at intervals;
s3: depositing a semiconductor material on the buffer layer and performing patterning treatment to form a first semiconductor part located between two conductor parts;
s4: depositing an insulating material on the buffer layer, the conductor part and the first semiconductor part to form a gate insulating layer, and patterning to form a first via hole and a second via hole;
s5: depositing a metal layer material on the gate insulating layer and patterning to form a gate metal layer, a source metal layer and a drain metal layer which are arranged at intervals; and
s6: depositing a passivation layer material to form a passivation layer covering the gate insulating layer, the gate metal layer, the source metal and the drain metal layer;
the first semiconductor part and the conductor part form an active layer, the projection of the grid metal layer covers the first semiconductor part, and the source metal layer and the drain metal layer are respectively connected with the two corresponding conductor parts through the first via hole and the second via hole.
Depositing a conductor material on the buffer layer, and performing patterning treatment to form at least two conductor parts arranged at intervals, wherein the conductor material is indium zinc oxide; in the step of depositing a semiconductor material on the buffer layer and performing patterning to form a first semiconductor portion located between two conductor portions, a second semiconductor portion is formed overlying both conductor portions at the same time as the first semiconductor portion.
The invention completes the upper grid electrode, the source electrode and the drain electrode of the TFT by adopting the same process, is different from the traditional grid electrode, and needs two processes (one grid electrode and one source/drain electrode), thereby increasing the production beat as much as possible, saving the cost, and simultaneously realizing the reduction of the resistance value of the whole active layer without ion bombardment on the semiconductor part after the conductor part is added, thereby solving the problem of insufficient on-state current of the TFT.
A sixth embodiment of the present application is a further refinement and expansion of the first embodiment, and the present embodiment also discloses a method for preparing a thin film transistor, or a method for preparing a display substrate, where the method includes the following steps:
depositing and patterning a first metal layer on a substrate to form a shading metal layer (a lower grid electrode of a TFT and playing a shading role) and the first metal layer;
step two, depositing a buffer layer;
depositing ITO on the buffer layer and patterning to form a conductor part and a conductive layer;
step four, depositing and patterning a semiconductor layer, namely a first semiconductor part and a semiconductor layer of a channel layer of the TFT are formed by indium gallium zinc oxide in the scheme example;
depositing and patterning a gate insulating layer to form a first via hole, a second via hole, a third via hole and a fourth via hole;
step six, depositing and patterning a grid metal layer, a source electrode metal layer, a drain electrode metal layer and a second layer metal to form a grid electrode, a source electrode, a drain electrode and a second metal layer on the TFT;
and step seven, forming one or more protective passivation layers.
It should be noted that, the limitation of each step in the present solution is not to be considered as limiting the sequence of steps on the premise of not affecting the implementation of the specific solution, and the steps written in the previous step may be executed before, may be executed after, or may even be executed simultaneously, so long as the implementation of the present solution is possible, all should be considered as falling within the protection scope of the present application.
The technical scheme of the application can be widely applied to various display panels, such as TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, MVA (Multi-Domain Vertical Alignment) display panels, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, mini/micro LED display panels and the like, can be applied to the scheme. The display panels listed above are only commonly used, and in some other display panels, as long as the thin film transistor of the present application is used, it is also within the scope of the present application.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (5)
1. A display substrate comprising a substrate, a thin film transistor disposed on the substrate, the thin film transistor comprising:
a buffer layer;
an active layer disposed on the buffer layer;
a gate insulating layer which is arranged on the buffer layer and the active layer in a covering manner and is provided with a first via hole and a second via hole;
a gate metal layer disposed on the gate insulating layer;
the source electrode metal layer is arranged on the gate insulating layer and is connected with the active layer through the first via hole;
the drain electrode metal layer is arranged on the gate insulating layer and is connected with the active layer through the second via hole; and
the passivation layer is arranged on the gate metal layer, the source metal layer, the drain metal layer and the gate insulating layer in a covering manner;
the active layer comprises at least two conductor parts and a first semiconductor part, wherein the two conductor parts are arranged on the buffer layer at intervals, and the first semiconductor part is arranged in the interval between the two conductor parts and is electrically connected with the two conductor parts; the projection of the grid metal layer covers the first semiconductor part, and the source metal layer and the drain metal layer are respectively connected with the two corresponding conductor parts through the first via hole and the second via hole;
the thin film transistor further comprises at least two second semiconductor parts, the second semiconductor parts are arranged on the conductor parts, the second semiconductor parts are connected with the first semiconductor parts and are integrally formed, the width of each second semiconductor part is smaller than that of the conductor part, a grid insulation layer is filled between one end of each second semiconductor part, which is far away from the first semiconductor part, and the first through hole or the second through hole, and the second semiconductor parts cover part of the conductor parts; the first via hole and the second via hole are respectively connected with the two conductor parts;
the conductor part comprises a transparent conductive film, and the transparent conductive film is formed by adopting indium tin oxide; the first semiconductor portion and the second semiconductor portion are formed of indium gallium zinc oxide;
the thin film transistor comprises a shading metal layer, the shading metal layer is arranged on one side, far away from the grid insulation layer, of the buffer layer, the width of the shading metal layer is larger than that of the first semiconductor part, and the source electrode metal layer is connected with the shading metal layer through a third via hole;
the display substrate further comprises a first metal layer and a second metal layer, the gate insulating layer further comprises a fourth via hole, the second metal layer is connected with the first metal layer through the fourth via hole, the first metal layer and the shading metal layer are arranged in the same layer, and the second metal layer, the gate metal layer, the source metal layer and the drain metal layer are arranged in the same layer;
the second metal layer is connected with the first metal layer through a via hole, a conductive layer and a semiconductor layer are arranged between the first metal layer and the second metal layer, the conductive layer and the conductor part are arranged on the same layer, and the semiconductor layer and the first semiconductor part are arranged on the same layer.
2. A display substrate comprising a substrate, a thin film transistor disposed on the substrate, the thin film transistor comprising:
a buffer layer;
an active layer disposed on the buffer layer;
a gate insulating layer which is arranged on the buffer layer and the active layer in a covering manner and is provided with a first via hole and a second via hole;
a gate metal layer disposed on the gate insulating layer;
the source electrode metal layer is arranged on the gate insulating layer and is connected with the active layer through the first via hole;
the drain electrode metal layer is arranged on the gate insulating layer and is connected with the active layer through the second via hole; and
the passivation layer is arranged on the gate metal layer, the source metal layer, the drain metal layer and the gate insulating layer in a covering manner;
the active layer comprises at least two conductor parts and a first semiconductor part, wherein the two conductor parts are arranged on the buffer layer at intervals, and the first semiconductor part is arranged in the interval between the two conductor parts and is electrically connected with the two conductor parts; a projection of the gate metal layer covers the first semiconductor portion;
the thin film transistor further comprises at least two second semiconductor parts, wherein the second semiconductor parts are arranged on the conductor parts, the second semiconductor parts are connected with the first semiconductor parts and are integrally formed, the width of each second semiconductor part is equal to the width of each conductor part, and the second semiconductor parts completely cover the conductor parts; the bottoms of the first via holes and the bottoms of the second via holes are respectively contacted with the top surfaces of the two second semiconductor parts;
the conductor part comprises a transparent conductive film, and the transparent conductive film is formed by adopting indium tin oxide; the first semiconductor portion and the second semiconductor portion are formed of indium gallium zinc oxide;
the thin film transistor comprises a shading metal layer, the shading metal layer is arranged on one side, far away from the grid insulation layer, of the buffer layer, the width of the shading metal layer is larger than that of the first semiconductor part, and the source electrode metal layer is connected with the shading metal layer through a third via hole;
the display substrate further comprises a first metal layer and a second metal layer, the gate insulating layer further comprises a fourth via hole, the second metal layer is connected with the first metal layer through the fourth via hole, the first metal layer and the shading metal layer are arranged in the same layer, and the second metal layer, the gate metal layer, the source metal layer and the drain metal layer are arranged in the same layer;
the second metal layer is connected with the first metal layer through a via hole, a conductive layer and a semiconductor layer are arranged between the first metal layer and the second metal layer, the conductive layer and the conductor part are arranged on the same layer, and the semiconductor layer and the first semiconductor part are arranged on the same layer.
3. The display substrate according to claim 1 or 2, wherein the conductor portion has a thickness value d, wherein
4. A method of manufacturing a thin film transistor according to any one of claims 1 to 3, comprising the steps of:
forming a buffer layer on a substrate;
depositing a conductor material on the buffer layer, and performing patterning treatment to form at least two conductor parts which are arranged at intervals;
depositing a semiconductor material on the buffer layer and performing patterning treatment to form a first semiconductor part located between two conductor parts;
depositing an insulating material on the buffer layer, the conductor part and the first semiconductor part to form a gate insulating layer, and patterning to form a first via hole and a second via hole;
depositing a metal layer material on the gate insulating layer and patterning to form a gate metal layer, a source metal layer and a drain metal layer which are arranged at intervals; and
depositing a passivation layer material to form a passivation layer covering the gate insulating layer, the gate metal layer, the source metal and the drain metal layer;
the first semiconductor part and the conductor part form an active layer, the projection of the grid metal layer covers the first semiconductor part, and the source metal layer and the drain metal layer are respectively connected with the two corresponding conductor parts through the first via hole and the second via hole.
5. The method of manufacturing a thin film transistor according to claim 4, wherein in the step of depositing a conductor material in the buffer layer and patterning the conductor material to form at least two conductor portions disposed at intervals, the conductor material is indium zinc oxide;
in the step of depositing a semiconductor material on the buffer layer and performing patterning to form a first semiconductor portion located between two conductor portions, a second semiconductor portion is formed overlying both conductor portions at the same time as the first semiconductor portion.
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| CN115377204B (en) * | 2022-10-25 | 2023-04-18 | Tcl华星光电技术有限公司 | Display panel, manufacturing method thereof and display device |
| CN115377202A (en) * | 2022-10-25 | 2022-11-22 | Tcl华星光电技术有限公司 | Display panel, manufacturing method thereof and display device |
| CN117580394A (en) * | 2023-12-13 | 2024-02-20 | 惠科股份有限公司 | Pixel structure, preparation method thereof, display substrate and display device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010199459A (en) * | 2009-02-27 | 2010-09-09 | Dainippon Printing Co Ltd | Method of manufacturing transistor element |
| JP2012191025A (en) * | 2011-03-11 | 2012-10-04 | Dainippon Printing Co Ltd | Thin-film transistor array substrate, thin-film integrated circuit device, and method for manufacturing them |
| CN103208526A (en) * | 2012-12-28 | 2013-07-17 | 南京中电熊猫液晶显示科技有限公司 | Semiconductor device and manufacture method thereof |
| CN106935658A (en) * | 2017-05-05 | 2017-07-07 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte |
| CN107046002A (en) * | 2017-03-24 | 2017-08-15 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte, display device |
| CN109273365A (en) * | 2018-10-23 | 2019-01-25 | 惠科股份有限公司 | Preparation method of thin film transistor, thin film transistor and display panel |
| CN109786257A (en) * | 2019-01-18 | 2019-05-21 | 惠科股份有限公司 | Manufacturing method of thin film transistor, array substrate and display panel |
| CN113782616A (en) * | 2019-01-10 | 2021-12-10 | 合肥鑫晟光电科技有限公司 | Thin film transistor, preparation method thereof, array substrate and display device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101830170B1 (en) * | 2011-05-17 | 2018-02-21 | 삼성디스플레이 주식회사 | Oxide semiconductor device, method of forming an oxide semiconductor device, and display device having an oxide semiconductor device, method of manufacturing a display device having an oxide semiconductor device |
| FR2998580B1 (en) * | 2012-11-26 | 2016-10-21 | Institut De Rech Pour Le Developpement Ird | MOLECULAR MARKERS AND METHODS FOR THE IDENTIFICATION OF GENOTYPES OF PALMIER DATTIER |
| KR102178766B1 (en) * | 2013-03-29 | 2020-11-13 | 엘지디스플레이 주식회사 | Thin film transistor, method for manufacturing the same and display device comprising the same |
| CN104900655A (en) * | 2015-04-14 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, and display device |
| CN108666218A (en) * | 2017-03-29 | 2018-10-16 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and display base plate and preparation method thereof, display device |
| KR20210157801A (en) * | 2020-06-22 | 2021-12-29 | 엘지디스플레이 주식회사 | Thin film transistor array substrate and display device |
-
2022
- 2022-04-21 CN CN202210423517.6A patent/CN114883343B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010199459A (en) * | 2009-02-27 | 2010-09-09 | Dainippon Printing Co Ltd | Method of manufacturing transistor element |
| JP2012191025A (en) * | 2011-03-11 | 2012-10-04 | Dainippon Printing Co Ltd | Thin-film transistor array substrate, thin-film integrated circuit device, and method for manufacturing them |
| CN103208526A (en) * | 2012-12-28 | 2013-07-17 | 南京中电熊猫液晶显示科技有限公司 | Semiconductor device and manufacture method thereof |
| CN107046002A (en) * | 2017-03-24 | 2017-08-15 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte, display device |
| CN106935658A (en) * | 2017-05-05 | 2017-07-07 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte |
| CN109273365A (en) * | 2018-10-23 | 2019-01-25 | 惠科股份有限公司 | Preparation method of thin film transistor, thin film transistor and display panel |
| CN113782616A (en) * | 2019-01-10 | 2021-12-10 | 合肥鑫晟光电科技有限公司 | Thin film transistor, preparation method thereof, array substrate and display device |
| CN109786257A (en) * | 2019-01-18 | 2019-05-21 | 惠科股份有限公司 | Manufacturing method of thin film transistor, array substrate and display panel |
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|---|---|
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