CN114879913A - Method for reliably storing EEPROM data - Google Patents
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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Abstract
The invention discloses a method for reliably storing EEPROM data, which comprises the following steps: 1) powering on the EEPROM; 2) after power-on, initializing an EEPROM memory; 3) and receiving the updating data, writing the updating data into the EEPROM to complete the data updating and storing of the EEPROM. The invention divides the EEPROM into high address and low address intervals, and adopts a data redundancy backup mode of the high address and low address intervals, thereby improving the reliability of data.
Description
Technical Field
The invention relates to the field of data storage, in particular to a method for reliably storing EEPROM data.
Background
When the EEPROM stores data, the data of a specified address is erased and then new data is written in, and written data errors can be caused due to unexpected power failure and electromagnetic interference in the process. To solve this problem, the existing scheme mainly adopts a method of reading and comparing immediately after writing bytes. However, if power is lost in the writing process, the method has no data backup, so that the reliability of data storage under the conditions of unexpected power failure and the like cannot be ensured. In addition, the method for storing data by adopting the fixed address of the EEPROM is limited by the erasing times of the EEPROM, and when the erasing times of one address reach the limit value, the address can not store data any more, so that the safety of the data can not be ensured.
Disclosure of Invention
The invention aims to provide a method for reliably storing EEPROM data, which comprises the following steps:
1) powering on the EEPROM;
the EEPROM memory comprises a high address storage interval and a low address storage interval; the low address interval is a main storage area, and the high address interval is a backup data area.
The high address storage interval and the low address storage interval are equal in size.
The high address storage interval and the low address storage interval both comprise a plurality of fields.
The number of fields in the high address storage section is equal to that in the low address storage section, and the number of bytes in each field is equal.
In each field, the first byte is a segment flag byte, and the last byte is a segment check byte;
the segment flag byte is used for representing field validity and comprises a segment valid flag byte, a segment damage flag byte and a segment null flag byte;
the segment check bytes are used to characterize the correctness of the field.
2) After power-on, initializing an EEPROM memory;
the step of initializing the EEPROM memory includes:
2.1) initializing a data segment retrieval segment address;
2.2) reading the segment flag byte of the EEPROM according to the index address;
2.3) checking whether the segment flag byte of the EEPROM is a segment valid flag byte, if so, entering a step 2.6), otherwise, entering a step 2.4);
2.4) adding the segment length to the data segment retrieval segment address so as to update the data segment retrieval segment address;
2.5) checking whether the address of the data segment retrieval segment is larger than the highest address of the low address storage interval, if so, jumping to the step 2.14), otherwise, returning to the step 2.2);
2.6) reading the data content and segment check bytes of the current data segment in the low address storage interval of the EEPROM;
2.7) calculating the check code of the data content of the low address storage interval;
2.8) comparing the calculated data content check code of the low address storage interval with the read check byte of the low address storage interval to determine whether the check byte is consistent, if so, entering the step 2.9), otherwise, returning to the step 2.4);
2.9) reading the data content and segment check bytes of the current data segment in the high-address storage interval of the EEPROM;
2.10) calculating a data content check code of the high address storage interval;
2.11) comparing the calculated data content check code of the high address storage interval with the read check byte of the high address storage interval to determine whether the data content check code of the high address storage interval is consistent with the read check byte of the high address storage interval, if so, entering the step 12), otherwise, returning to the step 2.4);
2.12) comparing whether the data contents of the read low address interval and the read high address interval are consistent, if so, entering a step 2.13), otherwise, entering a step 2.16);
2.13) retrieving valid data, and copying the read segment data content into a RAM memory;
2.14) judging that the current EEPROM memory does not retrieve valid data;
2.15) copying the default parameters of the EEPROM stored by the Flash into a RAM memory;
2.16) writing the EEPROM data stored in the RAM and to be written into the EEPROM memory.
3) And receiving the updating data, writing the updating data into the EEPROM to complete the data updating and storing of the EEPROM.
The method for completing data updating and storing of the EEPROM memory comprises the following steps: and circularly storing the data between the fields, writing the effective mark word of the field into the initial address of the field after confirming that the data of the current field is normally stored, and erasing the effective mark of the previous data field.
The step of completing data updating and storing of the EEPROM memory comprises the following steps:
3.1) the application program updates the EEPROM data to be written in the RAM and calculates check bytes;
3.2) adding the segment length to the current segment address, thereby leading the data storage address to point to the next field;
3.3) judging whether the segment address is larger than or equal to the highest address of the low address storage interval, if so, entering a step 3.4), and if not, entering a step 3.5);
3.4) setting the segment address as an initialization segment address;
3.5) reading a segment mark of the current data segment;
3.6) checking whether the data segment mark is a null mark byte, if so, entering a step 3.7), otherwise, returning to the step 3.2);
3.7) writing data content and check bytes into the segment of the low address storage interval according to the byte sequence;
3.8) reading the data content written into the low address storage interval;
3.9) comparing whether the data content read in the step 3.8) is consistent with the data content of the EEPROM to be written in the RAM, if so, entering the step 3.11), otherwise, determining that the data transmission is wrong, and entering the step 3.10);
3.10) judging whether the accumulated times of the data transmission errors are larger than a preset threshold value, if so, entering a step 3.15), and if not, returning to the step 3.7);
3.11) writing data content and check bytes into the high address storage interval according to the byte sequence;
3.12) reading the data content of the written high address section;
3.13) comparing whether the data content read in the step 3.12) is completely consistent with the data content of the EEPROM to be written in the RAM, if so, entering a step 3.16), otherwise, determining that the data transmission is wrong, and entering a step 3.14);
3.14) judging whether the accumulated times of the data transmission errors are larger than a preset threshold value, if so, entering a step 3.15), and if not, returning to the step 3.11);
3.15) writing the segment damage flag byte into the segment flag byte address of the low address storage interval;
3.16) writing the segment valid flag byte into the segment flag byte address of the low address storage interval;
3.17) erasing the data of the last segment of the flag byte address in the low address storage interval, wherein the data of the address comprises the segment of the null flag byte.
The segment corruption flag byte comprises 0x 55; the segment valid flag byte comprises 0 xAA; the segment null flag byte comprises 0 xFF; the initialization address of the data segment includes 0x 0000.
The technical effects of the invention are undoubted, and the beneficial effects of the invention are as follows:
the invention provides a data storage method of an EEPROM (electrically erasable programmable read-only memory), which improves the reliability of data by dividing the EEPROM into a high address interval and a low address interval and adopting a data redundancy backup mode of the high address interval and the low address interval.
The invention divides the interval into sections, and the data of the adjacent sections are used as redundant backup, when the data of the section is not correctly written, the data of the previous section is continuously effective, thereby improving the reliability of the data.
The invention also writes the check code of the calculated data content into the EEPROM and takes the check code as a check means when reading, thereby improving the accuracy of data writing;
the invention adopts a mode of circularly writing and checking to each section, thereby prolonging the service life of the EEPROM.
Drawings
FIG. 1 is a schematic diagram of EEPROM memory area division.
FIG. 2 is a flow chart of an EEPROM data reliable storage method.
Fig. 3 is a power-on initialization flowchart.
Fig. 4 is a data storage flow chart.
Detailed Description
The present invention is further illustrated by the following examples, but it should not be construed that the scope of the above-described subject matter is limited to the following examples. Various substitutions and alterations can be made without departing from the technical idea of the invention and the scope of the invention is covered by the present invention according to the common technical knowledge and the conventional means in the field.
Example 1:
referring to fig. 1 to 4, a method for reliably storing EEPROM (electrically erasable programmable read only memory) data includes the following steps:
1) electrifying the EEPROM;
the EEPROM memory comprises a high address storage interval and a low address storage interval; the low address interval is a main storage area, and the high address interval is a backup data area.
The high address storage interval and the low address storage interval are equal in size.
The high address storage interval and the low address storage interval both comprise a plurality of fields.
The number of fields in the high address storage section is equal to that in the low address storage section, and the number of bytes in each field is equal.
In each field, the first byte is a segment flag byte, and the last byte is a segment check byte;
the segment flag byte is used for representing field validity and comprises a segment valid flag byte, a segment damage flag byte and a segment null flag byte;
the segment check bytes are used to characterize the correctness of the field.
2) After power-on, initializing an EEPROM memory;
the step of initializing the EEPROM memory includes:
2.1) initializing a data segment retrieval segment address;
2.2) reading the segment flag byte of the EEPROM according to the index address;
2.3) checking whether the segment flag byte of the EEPROM is a segment valid flag byte, if so, entering a step 2.6), otherwise, entering a step 2.4);
2.4) adding the segment length to the data segment retrieval segment address so as to update the data segment retrieval segment address;
2.5) checking whether the address of the data segment retrieval segment is larger than the highest address of the low address storage interval, if so, jumping to the step 2.14), otherwise, returning to the step 2.2);
2.6) reading the data content and segment check bytes of the current data segment in the low address storage interval of the EEPROM;
2.7) calculating the check code of the data content of the low address storage interval;
2.8) comparing the calculated data content check code of the low address storage interval with the read check byte of the low address storage interval to determine whether the check byte is consistent, if so, entering the step 2.9), otherwise, returning to the step 2.4);
2.9) reading the data content and segment check bytes of the current data segment in the high-address storage interval of the EEPROM;
2.10) calculating a data content check code of the high address storage interval;
2.11) comparing the calculated data content check code of the high address storage interval with the read check byte of the high address storage interval to determine whether the data content check code of the high address storage interval is consistent with the read check byte of the high address storage interval, if so, entering the step 2.12), otherwise, returning to the step 2.4);
2.12) comparing whether the data contents of the read low address interval and the read high address interval are consistent, if so, entering a step 2.13), otherwise, entering a step 2.16);
2.13) retrieving valid data, and copying the read segment data content into a RAM memory;
2.14) judging that the current EEPROM memory does not retrieve valid data;
2.15) copying the default parameters of the EEPROM stored by the Flash into a RAM (Ramdom Access Memory) Memory;
2.16) writing the EEPROM data stored in the RAM and to be written into the EEPROM memory.
3) And receiving the updating data, writing the updating data into the EEPROM to complete the data updating and storing of the EEPROM.
The method for completing data updating and storing of the EEPROM memory comprises the following steps: and circularly storing the data between the fields, writing the effective mark word of the field into the initial address of the field after confirming that the data of the current field is normally stored, and erasing the effective mark of the previous data field.
The step of completing data updating and storing of the EEPROM memory comprises the following steps:
3.1) the application program updates the EEPROM data to be written in the RAM and calculates check bytes;
3.2) adding the segment length to the current segment address, thereby leading the data storage address to point to the next field;
3.3) judging whether the segment address is larger than or equal to the highest address of the low address storage interval, if so, entering a step 3.4), and if not, entering a step 3.5);
3.4) setting the segment address as an initialization segment address;
3.5) reading a segment mark of the current data segment;
3.6) checking whether the data segment mark is 0xFF, if so, entering a step 3.7), otherwise, returning to the step 3.2);
3.7) writing data content and check bytes into the segment of the low address storage interval according to the byte sequence;
3.8) reading the data content written into the low address storage interval;
3.9) comparing whether the data content read in the step 3.8) is consistent with the data content of the EEPROM to be written in the RAM, if so, entering the step 3.11), otherwise, determining that the data transmission is wrong, and entering the step 3.10);
3.10) judging whether the accumulated times of the data transmission errors are larger than a preset threshold value, if so, entering a step 3.15), and if not, returning to the step 3.7);
3.11) writing data content and check bytes into the high address storage interval according to the byte sequence;
3.12) reading the data content of the written high address section;
3.13) comparing whether the data content read in the step 3.12) is completely consistent with the data content of the EEPROM to be written in the RAM, if so, entering a step 3.16), otherwise, determining that the data transmission is wrong, and entering a step 3.14);
3.14) judging whether the accumulated times of the data transmission errors are larger than a preset threshold value, if so, entering a step 3.15), and if not, returning to the step 3.11);
3.15) writing the segment damage flag byte into the segment flag byte address of the low address storage interval;
3.16) writing the segment valid flag byte into the segment flag byte address of the low address storage interval;
3.17) erasing the data of the last flag byte address of the low address storage interval, wherein the data of the address is 0 xFF.
The segment corruption flag byte comprises 0x 55; the segment valid flag byte comprises 0 xAA; the initialization address of the data segment includes 0x 0000.
Example 2:
as shown in fig. 1, the main content of a reliable storage method for EEPROM data is shown in embodiment 1, wherein the EEPROM is divided into two equal sections, namely, a high address section and a low address section, the low address section is used as a main storage area, the high address section is used as a backup data area, and the data of the two sections are collated with each other; each interval is divided into a plurality of segments with equal length bytes according to the total length of the actually stored data, the first byte of each segment is a segment valid flag byte, the last byte of each segment is a segment check byte, and the data content is arranged between the segment valid flag byte and the segment check byte.
The EEPROM comprises the following steps when being electrified and operated:
and step A, searching the EEPROM when the EEPROM is electrified and started, and checking whether reliably stored data exists or not.
And B, writing the updated data into the EEPROM.
Example 3:
the main contents of an EEPROM data reliable storage method are shown in an embodiment 1-2, wherein the EEPROM storage method is implemented by the following processes:
the total storage space of the EEPROM is 64Kbit and is divided into 4 kbyte low address interval and 4 kbyte interval, the storage length of the application data is 500 bytes, and each segment is divided according to 512 bytes, so that the low address interval and the high address interval have 8 segments respectively. The starting addresses of the low address block section are respectively as follows: 0x000, 0x0200, 0x0400, 0x0600, 0x0800, 0x0A00, 0x0C00, 0x0E 00; the highest address of the low address interval 0x0 FFF.
The steps of power-on starting are as follows:
a01, setting the address of the data segment search segment to 0x 0000;
a02, reading the segment flag byte of EEPROM according to the index address;
a03, checking whether the segment flag byte of the EEPROM is 0 xAA;
a04, adding the segment address of the data segment to the segment length 512;
a05, checking whether the address of the data segment searching segment is larger than the highest address 0xFFF of the low address interval;
a06, reading the data content and check byte in the low address interval of EEPROM;
a07, calculating the check code of the data content of the low address interval;
a08, comparing the calculated low address interval data content check code with the read low address interval check byte to see if they are consistent;
a09, reading the data content and check byte of EEPROM high address interval;
a10, calculating the data content check code of the high address interval;
a11, comparing whether the calculated check code of the high address interval data content is consistent with the read check byte of the high address interval;
a12, comparing whether the data content of the read low address interval and the read high address interval is consistent;
a13, retrieving valid data, and copying the read segment data content to the RAM;
a14, no valid data is retrieved;
a15, copying the default parameters of the EEPROM stored in the Flash into the RAM;
a16 writing the EEPROM data to be written stored in the RAM into the EEPROM.
The steps of writing the updated data into the EEPROM are as follows:
b01 the application updates the RAM data and calculates the check bytes.
b02 segment address plus segment length 512 so that the memory address points to the next segment.
b03 whether the segment address is equal to or greater than the low address range highest address 0 xFFF.
b04 when the segment address is greater than 0xFFF segment, set the address to 0x 0000.
b05, reading the data segment mark.
b06, check if the data segment flag is 0 xFF.
b07 writing the data content and check bytes to the segments of the lower address interval in byte order.
b08, reading the data content of the lower address block section just written.
b09 comparing the read-back data with the written data.
b10, judging whether the accumulated error times is more than three.
b11 writing the data content and check bytes to the segments of the high address interval in byte order.
b12 reading the data content of the high address block section just written.
b13, comparing whether the read-back high address interval section data and the written data are completely consistent.
b14, judging whether the accumulated error times is more than three.
b15, writing 0x55 to the flag byte address of the current segment of the low address interval.
b16, writing 0xAA to the flag byte address of the current segment of the low address interval.
b17 erasing the data of the flag byte address in the upper part of the low address interval.
Claims (10)
1. A method for reliably storing EEPROM data is characterized by comprising the following steps:
1) the EEPROM memory is powered up.
2) And initializing the EEPROM after powering on.
3) And receiving the updating data, writing the updating data into the EEPROM to complete the data updating and storing of the EEPROM.
2. The method of claim 1, wherein said EEPROM memory comprises high address storage sections and low address storage sections; the low address interval is a main storage area, and the high address interval is a backup data area.
3. The method of claim 2, wherein the sizes of said high address storage interval and said low address storage interval are equal.
4. The method of claim 3, wherein each of said high address storage interval and said low address storage interval comprises a plurality of fields.
5. The method of claim 4, wherein the number of fields in the high address storage section and the low address storage section is equal, and the number of bytes in each field is equal.
6. The method of claim 4 wherein in each field, the first byte is a segment flag byte and the last byte is a segment check byte;
the segment flag byte is used for representing field validity and comprises a segment valid flag byte, a segment damage flag byte and a segment null flag byte;
the segment check bytes are used to characterize the correctness of the field.
7. The method of claim 1, wherein the step of initializing the EEPROM memory comprises:
1) initializing a data segment search segment address;
2) reading the segment flag byte of the EEPROM according to the index address;
3) checking whether the segment flag byte of the EEPROM is a segment valid flag byte, if so, entering a step 6), and if not, entering a step 4);
4) adding the segment length to the data segment retrieval segment address so as to update the data segment retrieval segment address;
5) checking whether the address of the data segment retrieval segment is larger than the highest address of the low address storage interval, if so, jumping to the step 14), otherwise, returning to the step 2);
6) reading the data content and segment check bytes of the current data segment in the low address storage interval of the EEPROM;
7) calculating a check code of data content of a low address storage interval;
8) comparing the calculated data content check code of the low address storage interval with the read check byte of the low address storage interval to determine whether the data content check code of the low address storage interval is consistent with the read check byte of the low address storage interval, if so, entering the step 9), and if not, returning to the step 4);
9) reading the data content and segment check bytes of the current data segment in the high-address storage interval of the EEPROM;
10) calculating a data content check code of a high address storage interval;
11) comparing the calculated high address storage interval data content check code with the read high address storage interval check byte to determine whether the high address storage interval data content check code is consistent with the read high address storage interval check byte, if so, entering the step 12), otherwise, returning to the step 4);
12) comparing whether the data contents of the read low address interval and the read high address interval are consistent, if so, entering a step 13), and if not, entering a step 16);
13) retrieving valid data, and copying the read segment data content to a RAM memory;
14) judging that valid data are not retrieved from the current EEPROM memory;
15) copying EEPROM default parameters stored by Flash to an RAM memory;
16) and writing the EEPROM data to be written stored in the RAM into the EEPROM memory.
8. The method of claim 1, wherein the method comprises the following steps: the method for completing data updating and storing of the EEPROM memory comprises the following steps: and circularly storing the data between the fields, writing the effective mark word of the field into the initial address of the field after confirming that the data of the current field is normally stored, and erasing the effective mark of the previous data field.
9. The method of claim 1, wherein the step of updating and storing the data of the EEPROM memory comprises:
1) updating the EEPROM data to be written in the RAM by the application program, and calculating check bytes;
2) adding a segment length to the current segment address, thereby causing the data storage address to point to the next field;
3) judging whether the segment address is larger than or equal to the highest address of the low address storage interval, if so, entering a step 4), and otherwise, entering a step 5);
4) setting the segment address as an initialization segment address;
5) reading a segment flag of a current data segment;
6) checking whether the data segment flag is a null flag byte, if so, entering a step 7), otherwise, returning to the step 2);
7) writing data content and check bytes into the segment of the low address storage interval according to the byte sequence;
8) reading the data content written into the low address storage interval;
9) comparing whether the data content read in the step 8) is consistent with the data content of the EEPROM to be written in the RAM, if so, entering a step 11), otherwise, determining that the data transmission is wrong, and entering a step 10);
10) judging whether the accumulated times of the data transmission errors are larger than a preset threshold value, if so, entering a step 15), and otherwise, returning to the step 7);
11) writing data content and check bytes into the high address storage interval according to the byte sequence;
12) reading the data content of the written high address block section;
13) comparing whether the data content read in the step 12) is completely consistent with the data content of the EEPROM to be written in the RAM, if so, entering a step 16), otherwise, determining that the data transmission is wrong, and entering a step 14);
14) judging whether the accumulated times of the data transmission errors are larger than a preset threshold value, if so, entering a step 15), and otherwise, returning to the step 11);
15) writing the segment damage flag byte into the segment flag byte address of the low address storage interval;
16) writing the segment valid flag byte into the segment flag byte address of the low address storage interval;
17) and erasing the data of the last segment of the flag byte address in the low address storage interval, wherein the data of the address comprises a segment of the null flag byte.
10. The method of claim 8 for reliable storage of EEPROM data, comprising: the segment corruption flag byte comprises 0x 55; the segment valid flag byte comprises 0 xAA; the segment null flag byte comprises 0 xFF; the initialization address of the data segment includes 0x 0000.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117742588A (en) * | 2023-11-30 | 2024-03-22 | 武汉芯必达微电子有限公司 | Data storage method and system using Flash simulation EEPROM |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117742588A (en) * | 2023-11-30 | 2024-03-22 | 武汉芯必达微电子有限公司 | Data storage method and system using Flash simulation EEPROM |
| CN117742588B (en) * | 2023-11-30 | 2024-06-04 | 武汉芯必达微电子有限公司 | Data storage method and system using Flash simulation EEPROM |
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