CN114879809B - Low-dropout linear voltage stabilizing circuit - Google Patents
Low-dropout linear voltage stabilizing circuit Download PDFInfo
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- CN114879809B CN114879809B CN202210396146.7A CN202210396146A CN114879809B CN 114879809 B CN114879809 B CN 114879809B CN 202210396146 A CN202210396146 A CN 202210396146A CN 114879809 B CN114879809 B CN 114879809B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a low-dropout linear voltage stabilizing circuit, which relates to the technical field of low-dropout linear voltage stabilizing and comprises the following components: the input end of the first reference current source is connected with the power supply, and the output end of the first reference current source is connected with the reference circuit through a first switching tube so as to provide reference voltage; the drain electrode of the second switching tube is connected with a power supply, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube, and the source electrode of the second switching tube is connected with a voltage stabilizing output port; when external disturbance current flowing outwards is applied to the voltage-stabilizing output port, the output voltage of the voltage-stabilizing output port is controlled to be stable relative to the reference voltage by controlling the first switching tube and the second switching tube; the feedback circuit is respectively connected with the reference circuit, the voltage stabilizing output port and the ground; when an external disturbance current flowing inwards is applied to the regulated output port, the feedback circuit is used for controlling the output voltage of the regulated output port to be stable relative to the reference voltage. The bidirectional high-interference-resistance output device has the beneficial effects that the bidirectional high-interference-resistance output device is realized; the circuit area is small; the response speed of the circuit is high.
Description
Technical Field
The invention relates to the technical field of low-dropout linear voltage stabilization, in particular to a low-dropout linear voltage stabilizing circuit.
Background
LDO (low dropout regulator) is a low dropout linear regulator, which is an integrated circuit regulator, and typically has very low self-noise and a high power supply rejection ratio PSRR (Power Supply Rejection Ratio) relative to conventional linear regulators. LDOs are a very low-consumption miniature system-on-chip, and are widely used because of various advantages.
However, the existing LDO circuit can only realize unidirectional anti-interference capability, i.e. when the load has interference of inputting large current, the circuit can not stabilize the output voltage, i.e. the LDO fails, and the anti-interference response speed is very slow.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a low-dropout linear voltage stabilizing circuit, which comprises:
the output end of the first reference current source is connected with a reference circuit through a first switch tube so as to provide a reference voltage;
the drain electrode of the first switching tube is respectively connected with the output end of the first reference current source and the grid electrode of the first switching tube, and the source electrode of the first switching tube is connected with the reference circuit;
the drain electrode of the second switching tube is connected with the power supply, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube, and the source electrode of the second switching tube is connected with a voltage stabilizing output port;
when external disturbance current flowing outwards is applied to the voltage stabilizing output port, the output voltage of the voltage stabilizing output port is controlled to be stable relative to the reference voltage by controlling the first switching tube and the second switching tube;
the feedback circuit is respectively connected with the reference circuit, the voltage stabilizing output port and the ground;
when an interference current flowing inwards is externally applied to the voltage stabilizing output port, the feedback circuit is used for controlling the output voltage of the voltage stabilizing output port to be stable relative to the reference voltage.
Preferably, the feedback circuit includes:
the source electrode of the third switching tube is connected with the voltage stabilizing output port, and the grid electrode of the third switching tube is connected with the reference circuit;
the grid electrode of the fourth switching tube is connected with the drain electrode of the third switching tube, the drain electrode of the fourth switching tube is respectively connected with the source electrode of the third switching tube and the voltage stabilizing output port, and the source electrode of the fourth switching tube is grounded;
and one end of the first resistor is respectively connected with the drain electrode of the third switching tube and the grid electrode of the fourth switching tube, and the other end of the first resistor is grounded.
Preferably, the reference circuit includes:
the grid electrode of the fifth switching tube is respectively connected with the grid electrode of the third switching tube and the drain electrode of the fifth switching tube;
one end of the second reference current source is respectively connected with the grid electrode of the third switching tube and the drain electrode of the fifth switching tube, and the other end of the second reference current source is grounded;
and one end of the second resistor is respectively connected with the source electrode of the first switching tube and the source electrode of the fifth switching tube, and the other end of the second resistor is grounded.
Preferably, the third switching tube and the fifth switching tube are PMOS tubes arranged in a mirror image mode, and the gate-on voltages of the third switching tube and the fifth switching tube are the same.
Preferably, the fourth switching tube is an NMOS tube.
Preferably, the circuit further comprises a first capacitor, one end of the first capacitor is respectively connected with the grid electrode of the third switching tube, the grid electrode of the fifth switching tube, the drain electrode of the fifth switching tube and one end of the second reference current source, and the other end of the first capacitor is grounded.
Preferably, the reference voltage is calculated as follows:
V ref ＝(I ref1 -I ref2 )*R 2
wherein V is ref For representing the reference voltage, I ref1 For representing a first reference current value provided by the first reference current source, I ref2 For representing a second reference current value provided by the second reference current source, R 2 For representing the resistance value of the second resistor.
Preferably, the circuit further comprises a second capacitor, one end of the second capacitor is respectively connected with the grid electrode of the first switch tube, the grid electrode of the second switch tube and the output end of the first reference current source, and the other end of the second capacitor is grounded.
Preferably, the first switching tube and the second switching tube are NMOS tubes arranged in a mirror image mode, and the gate-on voltages of the first switching tube and the second switching tube are the same.
Preferably, the device further comprises a load current source, wherein one end of the load current source is connected with the voltage stabilizing output port, and the other end of the load current source is grounded.
The technical scheme has the following advantages or beneficial effects: the output bidirectional strong anti-interference performance can be realized; the circuit area is small; aiming at output change, the feedback voltage can change according to the square rate of the overdrive voltage of the switching tube, so that the response speed of the circuit is greatly improved.
Drawings
FIG. 1 is a schematic diagram of a low dropout linear voltage regulator circuit according to a preferred embodiment of the present invention;
fig. 2 is a schematic diagram of voltage waveforms of circuit key points when the circuit is disturbed in the preferred embodiment of the present invention.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples. The present invention is not limited to the embodiment, and other embodiments may fall within the scope of the present invention as long as they conform to the gist of the present invention.
In accordance with the foregoing problems of the prior art, the present invention provides a low dropout linear voltage regulator circuit, as shown in fig. 1, comprising:
the input end of the first reference current source Iref1 is connected with a power supply VDD, and the output end of the first reference current source Iref1 is connected with a reference circuit 1 through a first switch tube M1 so as to provide a reference voltage Vref;
the drain electrode of the first switching tube M1 is respectively connected with the output end of the first reference current source Iref1 and the grid electrode of the first switching tube M1, and the source electrode of the first switching tube M1 is connected with the reference circuit 1;
the drain electrode of the second switching tube M2 is connected with the power supply VDD, the grid electrode of the second switching tube M2 is connected with the grid electrode of the first switching tube M1, and the source electrode of the second switching tube M2 is connected with a voltage-stabilizing output port 2;
when external disturbance current flowing outwards is applied to the regulated output port 2, the output voltage of the regulated output port 2 is controlled to be stable relative to the reference voltage by controlling the first switching tube M1 and the second switching tube M2;
and the feedback circuit 3 is respectively connected with the reference circuit 1, the regulated output port 2 and the ground, and the feedback circuit 3 is used for controlling the output voltage of the regulated output port 2 to be stable relative to the reference voltage when the external disturbance current flowing inwards is applied to the regulated output port 2.
Specifically, in this embodiment, the low dropout linear voltage regulator circuit of this technical solution is adopted, so that the circuit works in a static state, i.e. works normally, and when no external interference exists, the output voltage Vout of the voltage-stabilizing output port 2 is kept equal to the reference voltage Vref, so as to realize voltage stabilization. Further, when the regulated output port 2 is subjected to external strong interference, for example, when a strong CMTI current exists, the current value of the CMTI current can reach 10mA, the current lasts for 20ns, the direction of the current is random, and the low dropout linear regulator circuit still maintains a relatively stable output voltage Vout. In other words, the low dropout linear voltage stabilizing circuit of the present technical solution can effectively control the output voltage Vout of the voltage stabilizing output port 2 to be stable relative to the reference voltage Vref, so as to realize bidirectional strong anti-interference output.
In a preferred embodiment of the invention, the feedback circuit 3 comprises:
the source electrode of the third switching tube M3 is connected with the voltage stabilizing output port 2, and the grid electrode of the third switching tube M3 is connected with the reference circuit 1;
the grid electrode of the fourth switching tube M4 is connected with the drain electrode of the third switching tube M3, the drain electrode of the fourth switching tube M4 is respectively connected with the source electrode of the third switching tube M3 and the regulated output port 2, and the source electrode of the fourth switching tube M4 is grounded;
one end of the first resistor R1 is respectively connected with the drain electrode of the third switching tube M3 and the grid electrode of the fourth switching tube M4, and the other end of the first resistor R1 is grounded.
In a preferred embodiment of the invention, the reference circuit 1 comprises:
the grid electrode of the fifth switching tube M5 is respectively connected with the grid electrode of the third switching tube M3 and the drain electrode of the fifth switching tube M5;
one end of the second reference current source Iref2 is respectively connected with the grid electrode of the third switch tube M3 and the drain electrode of the fifth switch tube M5, and the other end of the second reference current source Iref2 is grounded;
and one end of the second resistor R2 is respectively connected with the source electrode of the first switching tube M1 and the source electrode of the fifth switching tube M5, and the other end of the second resistor R2 is grounded.
In the preferred embodiment of the present invention, the third switching tube M3 and the fifth switching tube M5 are PMOS tubes arranged in mirror image, and the gate turn-on voltages of the third switching tube M3 and the fifth switching tube M5 are the same.
In a preferred embodiment of the present invention, the fourth switching tube M4 is an NMOS tube.
In a preferred embodiment of the present invention, the circuit further includes a first capacitor C1, wherein one end of the first capacitor C1 is connected to the gate of the third switch tube M3, the gate of the fifth switch tube M5, the drain of the fifth switch tube M5 and one end of the second reference current source Iref2, respectively, and the other end of the first capacitor C1 is grounded.
In a preferred embodiment of the present invention, the reference voltage is calculated as follows:
V ref ＝(I ref1 -I ref2 )*R 2
wherein V is ref For indicating reference voltage, I ref1 For representing a first reference current value, I, provided by a first reference current source Iref1 ref2 For representing a second reference current value provided by a second reference current source Iref2, R 2 For representing the resistance value of the second resistor R2.
In a preferred embodiment of the present invention, the circuit further includes a second capacitor C2, wherein one end of the second capacitor C2 is connected to the gate of the first switch tube M1, the gate of the second switch tube M2 and the output end of the first reference current source Iref1, respectively, and the other end of the second capacitor C2 is grounded.
In a preferred embodiment of the present invention, the first switching tube M1 and the second switching tube M2 are NMOS tubes disposed in mirror image, and the gate turn-on voltages of the first switching tube M1 and the second switching tube M2 are the same.
In a preferred embodiment of the present invention, the present invention further includes a load current source Iload, one end of the load current source Iload is connected to the regulated output port 2, and the other end of the load current source Iload is grounded.
Specifically, when the low dropout linear voltage stabilizing circuit of the present technical solution works in a static state, i.e. normal operation, and no external interference exists, the first switching tube M1 and the fifth switching tube M5 are controlled to be turned on, and the first switching tube M1 and the fifth switching tube M5 both adopt a diode connection method of gate and drain short circuit, which is equivalent to a diode and has a smaller voltage drop, based on this, the first reference current source Iref1 and the second reference current source Iref2 generate the reference voltage Vref through the second resistor R2, and the calculation formula is as follows:
V ref ＝(I ref1 -I ref2 )*R 2
wherein V is ref For indicating reference voltage, I ref1 For representing a first reference current value, I, provided by a first reference current source Iref1 ref2 For representing a second reference current value provided by a second reference current source Iref2, R 2 For representing the resistance value of the second resistor R2.
Since the second switching tube M2 and the first switching tube M1 are the same two NMOS tubes arranged in mirror image, the gate-source voltage of the second switching tube M2 is the same as the gate-source voltage of the first switching tube M1. Similarly, since the third switching tube M3 and the fifth switching tube M5 are the same two PMOS tubes arranged in a mirror image manner, the gate-source voltage of the third switching tube M3 is the same as the gate-source voltage of the fifth switching tube M5, and therefore, when the low dropout linear voltage regulator circuit of the present technical solution works in a static state, the output voltage Vout of the regulated output port 2 is equal to the reference voltage Vref.
When the regulated output port 2 is subjected to external strong interference, for example, in the application of a digital isolator, there is a strong CMTI current, the current can reach 10mA, lasting for 20ns, the current flows outwards, the second switching tube M2 and the first switching tube M1 are controlled to be turned on, the third switching tube M3 and the fourth switching tube M4 are controlled to be turned off, and the node voltage Vnb1 is kept motionless due to the existence of the capacitor C2, according to the saturation region current formula of the NMOS tube as shown in the following:
wherein i is ds Represents the source leakage current of the NMOS tube, beta represents the transconductance coefficient of the NMOS tube, V gs Represents the gate-source voltage of NMOS tube, V th Represents the threshold voltage of NMOS tube, V ov Indicating the overdrive voltage of the NMOS transistor.
The calculation formula of the amount of change in the output voltage Vout of the regulated output port can be obtained as follows:
wherein DeltaV out Indicating the change amount of the output voltage Vout, i ds2 Indicating the source leakage current, i, of the NMOS transistor when externally applied current disturbances ds Representing the source-drain current of the NMOS transistor in a static state, k representing the change of the source-drain current of the NMOS transistor in the case of external disturbance, e.g. designing the overdrive voltage V of the NMOS transistor ov When the source leakage current of the NMOS tube is 200uA and the interference current of CMTIinterference is 10.2mA in static operation, the change amount k of the source leakage current of the NMOS tube is = (10.2-0.2)/0.2 = 50; then Δvout=0.35V.
It can be seen that the low dropout linear voltage regulator circuit adopting the technical scheme can realize that the output voltage of Vout has very small variation even if the output current varies by 50 times.
When the regulated output port 2 is subjected to external strong disturbance, for example, there is a strong reverse CMTI current (second disturbance current) which can reach 10mA for 20ns, and the current flows inward, the node voltage Vpb1 is kept still due to the capacitor C1, and Vout rapidly generates an upward voltage according to the node voltage V as shown below fb Calculation formula of (feedback voltage):
V fb ＝i dsp ·R 1 ＝0.5·R 1 ·β p ·(V gsp -V thp ) 2
wherein i is dsp Represents the source leakage current, beta, flowing through the third switching tube M3 p Representing the transconductance coefficient, V, of the third switching tube M3 gsp Represents the source gate voltage, V, of the third switching transistor M3 thp The threshold voltage of the third switching transistor M3 is shown.
In the static state, V is preferably selected from fb Is set to 0.7Vth, wherein Vth is the threshold voltage of the fourth switching tube M4, and at the moment, the fourth switching tube M4 is in an off state as long as the output voltage Vout changes by more than 4V ovp (overdrive voltage V of third switch tube M3) ovp ，V ovp ＝V gsp -V thp ) I is then dsp The current change of (2) is 16 times, then V is caused fb Becomes 11.2Vth; at this time, the fourth switching tube M4 is turned on to rapidly drain the interfering CMTI current through the fourth switching tube M4, thereby keeping the variation of the output voltage Vout small. It will be appreciated that V as described above fb The value of (2) is not limited to 0.7Vth, and may be set as required. It can be seen that the feedback voltage V for output variations fb Can be according to overdrive voltage V ovp (V ovp ＝V gsp -V thp ) The square rate of the circuit is changed, and the response speed of the circuit is greatly improved.
Further specifically, considering that when the feedback circuit adopts the PMOS transistor, if the feedback circuit adopts the same structure as the two NMOS transistors of the first switching transistor M1 and the second switching transistor M2, the PMOS transistor needs a larger area, and the drain-source current ids of the PMOS transistor is small, which results in a larger output voltage change, and if the feedback circuit adopts a larger PMOS transistor, a larger capacitor C1 needs to be configured to keep the voltage of the node voltage Vpb1 unchanged, which also needs a larger area; based on the PMOS tube, the circuit adopts the third switching tube M3, the first resistor R1 and the fourth switching tube M4 to form a feedback circuit, and the PMOS tube can be in a small area at the moment, so that the low-dropout linear voltage stabilizing circuit of the technical scheme has a smaller circuit area than the traditional low-dropout linear voltage stabilizing circuit.
As shown in FIG. 2, the circuit of the present invention operates in a static state during a period from t0 to t1, i.e. the load current Iload is I0 (which may be small, e.g. 200 uA), and suddenly changes to Imax (which may be large, e.g. 10 mA) due to external disturbance when the period reaches t1, such as overdrive voltage V of NMOS transistor ov The analysis shows that the source leakage current of the NMOS tube is 200uA, the first interference current of the CMTII interference is 10.2mA when in static operation, and Vout is changed downwards by 0.35V, the third switch tube M3 is closed, and the feedback voltage V fb Quickly changing into 0V, and when the time reaches the time t2, the current is recovered to the normal condition; when the time reaches the time t3, the load current Iload is regulated to output due to external interferenceThe port is charged with a large current and suddenly changes to Imin, such as overdrive voltage V of the third switch tube M3 ovp At 50mV, if the output voltage Vout increases by 0.2V, the feedback voltage V fb Rapidly increasing to 3V, and simultaneously rapidly opening the fourth switching tube M4; when the time reaches the time t4, the circuit returns to the static state, i.e. the feedback voltage V fb =0.7vth, and the output voltage Vout returns to a normal value.
It can be seen that, no matter the direction of the external interference current, the low dropout linear voltage stabilizing circuit of the technical scheme can effectively control the output voltage Vout of the voltage stabilizing output port 2 to keep stable relative to the reference voltage Vref, so as to realize the bidirectional strong interference resistance of output.
The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and drawings, and are intended to be included within the scope of the present invention.
Claims (10)
1. A low dropout linear voltage regulator circuit, comprising:
the output end of the first reference current source is connected with a reference circuit through a first switch tube so as to provide a reference voltage;
the drain electrode of the first switching tube is respectively connected with the output end of the first reference current source and the grid electrode of the first switching tube, and the source electrode of the first switching tube is connected with the reference circuit;
the drain electrode of the second switching tube is connected with the power supply, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube, and the source electrode of the second switching tube is connected with a voltage stabilizing output port;
when external disturbance current flowing outwards is applied to the voltage stabilizing output port, the output voltage of the voltage stabilizing output port is controlled to be stable relative to the reference voltage by controlling the first switching tube and the second switching tube;
the feedback circuit is respectively connected with the reference circuit, the voltage stabilizing output port and the ground;
when an interference current flowing inwards is externally applied to the voltage stabilizing output port, the feedback circuit is used for controlling the output voltage of the voltage stabilizing output port to be stable relative to the reference voltage.
2. The low dropout linear regulator circuit according to claim 1, wherein said feedback circuit comprises:
the source electrode of the third switching tube is connected with the voltage stabilizing output port, and the grid electrode of the third switching tube is connected with the reference circuit;
the grid electrode of the fourth switching tube is connected with the drain electrode of the third switching tube, the drain electrode of the fourth switching tube is respectively connected with the source electrode of the third switching tube and the voltage stabilizing output port, and the source electrode of the fourth switching tube is grounded;
and one end of the first resistor is respectively connected with the drain electrode of the third switching tube and the grid electrode of the fourth switching tube, and the other end of the first resistor is grounded.
3. The low dropout linear regulator circuit according to claim 2, wherein said reference circuit comprises:
the grid electrode of the fifth switching tube is respectively connected with the grid electrode of the third switching tube and the drain electrode of the fifth switching tube;
one end of the second reference current source is respectively connected with the grid electrode of the third switching tube and the drain electrode of the fifth switching tube, and the other end of the second reference current source is grounded;
and one end of the second resistor is respectively connected with the source electrode of the first switching tube and the source electrode of the fifth switching tube, and the other end of the second resistor is grounded.
4. The low dropout linear voltage regulator circuit according to claim 3, wherein the third switching tube and the fifth switching tube are PMOS tubes arranged in a mirror image, and gate-on voltages of the third switching tube and the fifth switching tube are the same.
5. The low dropout linear voltage regulator circuit according to claim 4, wherein said fourth switching tube is an NMOS tube.
6. The low dropout linear voltage regulator circuit according to claim 3, further comprising a first capacitor, wherein one end of the first capacitor is connected to the gate of the third switching tube, the gate of the fifth switching tube, the drain of the fifth switching tube, and one end of the second reference current source, respectively, and the other end of the first capacitor is grounded.
7. The low dropout linear regulator circuit according to claim 3, wherein the reference voltage is calculated as follows:
V ref ＝(I ref1 -I ref2 )*R 2
wherein V is ref For representing the reference voltage, I ref1 For representing a first reference current value provided by the first reference current source, I ref2 For representing a second reference current value provided by the second reference current source, R 2 For representing the resistance value of the second resistor.
8. The low dropout linear voltage regulator circuit according to claim 1, further comprising a second capacitor, wherein one end of the second capacitor is connected to the gate of the first switching tube, the gate of the second switching tube, and the output end of the first reference current source, respectively, and the other end of the second capacitor is grounded.
9. The low dropout linear voltage regulator circuit according to claim 1, wherein the first switching tube and the second switching tube are NMOS tubes arranged in mirror image, and gate turn-on voltages of the first switching tube and the second switching tube are the same.
10. The low dropout linear regulator circuit according to claim 1, further comprising a load current source, wherein one end of the load current source is connected to the regulated output port, and the other end of the load current source is grounded.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102681584A (en) * | 2012-05-30 | 2012-09-19 | 昆山锐芯微电子有限公司 | Low noise bandgap reference circuit and reference source generation system |
| CN104122931A (en) * | 2014-07-25 | 2014-10-29 | 电子科技大学 | Low dropout linear regulator with large power supply rejection ratio |
| CN104201881A (en) * | 2014-09-28 | 2014-12-10 | 圣邦微电子（北京）股份有限公司 | Control circuit for step-down DCDC converter |
| CN110858083A (en) * | 2018-08-24 | 2020-03-03 | 株式会社东芝 | Constant voltage circuit |
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| CN106774614B (en) * | 2016-12-05 | 2017-11-14 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with super transconductance structure |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102681584A (en) * | 2012-05-30 | 2012-09-19 | 昆山锐芯微电子有限公司 | Low noise bandgap reference circuit and reference source generation system |
| CN104122931A (en) * | 2014-07-25 | 2014-10-29 | 电子科技大学 | Low dropout linear regulator with large power supply rejection ratio |
| CN104201881A (en) * | 2014-09-28 | 2014-12-10 | 圣邦微电子（北京）股份有限公司 | Control circuit for step-down DCDC converter |
| CN110858083A (en) * | 2018-08-24 | 2020-03-03 | 株式会社东芝 | Constant voltage circuit |
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