CN114844827B - Shared storage-based spanning tree routing hardware architecture and method for network-on-chip - Google Patents
Shared storage-based spanning tree routing hardware architecture and method for network-on-chip Download PDFInfo
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Abstract
The invention belongs to the field of on-chip network routing of integrated circuit chips, and discloses a spanning tree routing hardware architecture and a method based on shared storage for an on-chip network chip, wherein the spanning tree routing hardware architecture comprises an input channel, control logic and a cross switch, the control logic controls a single routing process, and the cross switch controls cross interconnection of the input channel and an output channel; the input channel comprises a route calculation module, a route table and an input buffer area; the route calculation module carries out route calculation through spanning tree route calculation according to the destination node label of each input data packet, outputs the corresponding output channel direction to the cross switch, and controls the cross interconnection of the input channel and the output channel. The fault-tolerant routing method of the spanning tree mainly constructs the spanning tree with breadth-first search in a Mesh type network and transmits a data packet along the spanning tree. The architecture enables large scale reduction of routing table hardware resources in a global topology.
Description
Technical Field
The invention belongs to the field of network-on-chip routing of integrated circuit chips, and particularly relates to a spanning tree routing hardware architecture and a method based on shared storage for a network-on-chip.
Background
In recent years, with the increasing development of integrated circuit process size, the number of transistors integrated on a single chip is gradually increased, and the continuous shrinkage of transistor technology allows more and more electronic systems to be integrated in a single chip. At present, technologies such as artificial intelligence, big data, cloud computing and the internet of things continuously urge more and more complex emerging applications, wherein an integrated circuit chip is a computing support for constructing various service scenes, and meanwhile, with the appearance of a multi-core computing chip and a many-core parallel system, the demand on computing performance is remarkably improved. Network-on-Chip (NoC) provides a communication system between components of a single Chip, and the Network-based communication system is a communication mode which is more extensible than the traditional bus-based communication. However, the lower technology node will cause hardware faults in the chip to be more and more likely to occur, so the fault-tolerant routing method based on the network on chip is applied to a single chip, and the fault-tolerant routing can avoid the faults in the network on chip through a fault-tolerant mechanism.
The fault-tolerant routing method can be divided into types of space redundancy fault tolerance, information redundancy fault tolerance, time redundancy fault tolerance and the like. The spatial redundancy fault tolerance is carried out by finding an alternative path. Path redundancy functionality can be provided directly in many NoC topologies, and the redundancy of such paths can be used directly to provide spatial redundancy without implementing redundancy by replicating hardware modules. For example, for a Mesh-type topology, a sub-rectangle formed for two nodes may dynamically switch to an alternate path using a different one of the rectangles if the standard path fails. Such redundancy mechanisms do not, therefore, reduce the overhead of duplicating packets, but they generate additional hardware overhead because some additional logic is required for troubleshooting and route reconfiguration to enable alternate paths compared to normal NoC implementations.
Wherein, the irregular topology caused by the fault can be explored by topology exploration to construct a spanning tree in the spatial redundancy fault tolerance. When a fault is detected, the whole NoC starts breadth-first search, and selects a central node or a nearby healthy node as a root of a spanning tree. And constructing a deadlock-free spanning tree virtual network through breadth-first search traversal. In this process, each node transmits a packet along the spanning tree route. However, the hardware implementation of the existing spanning tree routing method requires a very large storage space to store the routing table necessary for the method, and therefore, the hardware area of the router is too large for the final NoC hardware implementation.
Therefore, the existing spanning tree routing method mainly aims at theoretical implementation, and is not based on hardware implementation of the network-on-chip router, so that hardware resource evaluation is lacked. Meanwhile, the existing spanning tree routing method stays at the method level, and the hardware configuration process of the network on chip is not designed.
Disclosure of Invention
The present invention is directed to a spanning tree routing hardware architecture and method based on shared storage for a network-on-chip, so as to solve the above technical problems.
In order to solve the above technical problems, the specific technical solution of the spanning tree routing hardware architecture and method based on shared storage for a network-on-chip of the present invention is as follows:
a spanning tree routing hardware architecture based on shared storage for a network-on-chip comprises an input channel, control logic and a cross switch, wherein the control logic controls a single routing process, and the cross switch controls cross interconnection of the input channel and an output channel; the input channel comprises three sub-modules which are respectively a route calculation module, a route table and an input buffer area; the route calculation module performs path calculation through spanning tree route calculation according to the destination node label of each input data packet, outputs the corresponding output channel direction to the cross switch, and controls the cross interconnection of the input channel and the output channel.
Further, the routing table uses a block of SRAM with the same space to replace the original register.
Furthermore, local nodes share a routing table, in the Mesh-type topology, 4 adjacent nodes share the same routing table, and the 4 adjacent nodes can query the same routing table to obtain a global spanning tree ID.
Furthermore, the shared routing table is connected with 4 adjacent nodes through 4 interface modules, the address of the specific routing table accessed by each interface is analyzed and converted into an actual physical address through an address decoding module, and a request is sent to a corresponding physical Bank through cross interconnection, wherein the physical Bank module has an arbiter for arbitrating the condition that different interfaces request the same Bank, the request priority of each module is configured through a register, the address of the physical Bank is addressed through a high order, namely the physical address of a single Bank is progressive by 4, and adjacent addresses are distributed in different banks.
The invention also discloses a spanning tree routing method based on shared storage for the network-on-chip, which needs to perform breadth-first search to configure the spanning tree ID before routing, wherein the breadth-first search comprises the following steps:
step 1: determining a current search mode, wherein if the X direction is selected to be preferred, the east-west direction is preferred to search each time, and the south-north direction is firstly searched if the Y direction is preferred, and the following steps take the X direction as an example;
and 2, step: selecting a central node or other healthy nodes in the current topology as a root node, adding the root node or other healthy nodes into a queue, and marking the spanning tree ID, wherein at the moment, 1 node of the root node exists in the queue and only 1 node of the root node exists in the queue;
and step 3: setting a head node of a queue as a current node, and if the node in the east-west direction of the current node is not marked, enqueuing and marking the node; if the node in the south-north direction of the current node is not marked, enqueuing and marking the node, and when 4 neighbors of the node in the east, west, south and north directions are searched, dequeuing the current node;
and 4, step 4: and repeating the step 3 until the queue is empty, and at the moment, all the nodes which are positioned in the same connected graph with the root node are marked by the spanning tree.
Further, the theory of the method is based on spanning tree ID to find shared branch nodes, and routes the data packet "up" to the branch node first, and then routes "down" to the destination node.
Further, the routing method is divided into the following situations: when the destination node and the source node are positioned on the same sub-branch and the destination node is positioned at the downstream of the sub-branch where the current node is positioned, the destination node is moved to the destination node along the current sub-branch downwards; when the destination node and the source node are positioned on the same sub-branch and the destination node is positioned at the upstream of the sub-branch where the current node is positioned, the destination node is moved to the destination node along the current sub-branch upwards; when the destination node and the source node are not located in the same sub-branch, the current node goes upwards along the sub-branch where the current node is located, the current node and the shared branch node closest to the destination node go to, and then the current node and the source node go downwards from the shared branch node along the sub-branch where the destination node is located.
The spanning tree routing hardware architecture and method based on shared storage for the network-on-chip have the following advantages: the invention optimizes the routing table and reduces the area. The invention provides a network-on-chip architecture based on shared storage, which can reduce routing table hardware resources in global topology in a large scale.
Drawings
FIG. 1 is a schematic diagram of a spanning tree construction structure in a Mesh-type topology according to the present invention;
FIG. 2 is a diagram illustrating a hardware architecture of a router according to the spanning tree routing method of the present invention;
FIG. 3 is a representation of a desired routing for spanning tree routing of the present invention;
FIG. 4 is a schematic diagram of a node-shared routing table interconnect architecture of the present invention;
FIG. 5 is a diagram of a hardware architecture of a shared routing table according to the present invention.
Detailed Description
For better understanding of the purpose, structure and function of the present invention, the following describes a spanning tree routing hardware architecture and method based on shared memory for network-on-chip in detail with reference to the accompanying drawings.
The spanning tree fault-tolerant routing method mainly constructs a spanning tree with breadth-first search in a Mesh type network and transmits a data packet along the spanning tree. As shown in fig. 1, by designating the central node O as a root node and by breadth-first search, spanning tree growth is performed on the global topology. The breadth-first search is divided into X-direction-first search and Y-direction-first search, the spanning tree shapes finally formed by the two search modes are different, the X-direction-first search has better connectivity in the X direction, and the Y-direction-first search has better connectivity in the Y direction. After the breadth-first search is carried out, each node has a corresponding ID in the spanning tree, the ID identifies the position of the node in the spanning tree relative to a root node, and simultaneously identifies the affiliated sub-branch and depth, and each node has a globally unique ID. The invention provides a specific configuration process of breadth-first search.
Routing can be performed according to the ID. For the transmission between the source node and the destination node, according to the IDs of the source node and the destination node, the nearest shared branch node of the two nodes is first found, and the data packet is first routed "upward" to the shared branch node and then transmitted "downward" to the destination node. The invention provides a specific route calculation mode based on the ID and provides detailed calculation steps.
The hardware implementation of spanning tree routing is based on a routing table in each node, the routing table records spanning tree IDs of all nodes in the topology, the routing table needs to be searched in each routing, and the spanning tree IDs of a source node and a destination node are obtained for calculation. Therefore, in the actual large-scale topological network-on-chip, the routing table in each node occupies a large part of resources and area of the network-on-chip. Meanwhile, the invention provides a network-on-chip architecture based on shared storage, which can reduce the routing table hardware resources in the global topology in a large scale.
The spanning tree routing method requires breadth-first search to configure a spanning tree ID before routing. As shown in fig. 1, breadth-first search has two modes with different directional priorities, and based on the different modes, the present invention proposes a specific implementation of search, which includes the following steps:
1. determining the current search mode, wherein if the X direction is selected to be preferred, the east-west direction is preferred to search each time, and the south-north direction is searched first if the Y direction is preferred.
2. The central node (or other healthy nodes) in the current topology is selected as the root node, and added into the queue, and the spanning tree ID is marked, wherein only 1 node is in the queue.
3. And setting the head node of the queue as the current node. If the node in the east-west direction of the current node is not marked, enqueuing and marking the node; and if the node in the north-south direction of the current node is not marked, enqueuing and marking the node. And when the east-west-south-north 4 neighbors of the node are searched, the current node is dequeued.
4. Repeat step 3 until the queue is empty. All nodes that are in the same connectivity graph as the root node are marked by the spanning tree at this time.
The theory of the spanning tree routing method is based on spanning tree ID to find shared branch nodes, and route data packets to the branch nodes "upwards" first, and then route data packets to destination nodes "downwards". The invention provides a specific routing calculation mode based on a spanning tree ID, which generally refers to that a branch goes to a destination node from a current node along a branch according to the growing form of the spanning tree. The routing method mainly includes the following situations: when the destination node and the source node are positioned on the same sub-branch and the destination node is positioned at the downstream of the sub-branch where the current node is positioned, the destination node is moved to the destination node along the current sub-branch downwards; when the destination node and the source node are positioned on the same sub-branch and the destination node is positioned at the upstream of the sub-branch where the current node is positioned, the destination node is moved upwards along the current sub-branch; when the destination node and the source node are not located in the same sub-branch, the current node goes upwards along the sub-branch where the current node is located, the current node and the shared branch node closest to the destination node go to, and then the current node and the source node go downwards from the shared branch node along the sub-branch where the destination node is located.
Furthermore, the invention provides a router implementation hardware architecture of the spanning tree routing method. As shown in fig. 2, the router architecture mainly comprises the following modules, which are input channels, control logic and crossbar switches. Wherein the control logic controls a single routing process and the crossbar controls the cross-interconnection of the input channels and the output channels. The input channel comprises three submodules, namely a routing calculation module, a routing table and an input buffer area. The route calculation module performs path calculation through the spanning tree route calculation steps according to the destination node label of each input data packet, outputs the corresponding output channel direction to the cross switch, and controls the cross interconnection of the input channels and the output channels. It can be seen from the above method that the method requires a routing table, and the ID information of the global spanning tree is stored in each node for determining the relative position of the current node and the destination node each time, so the routing table module is used to store the routing table required by the method, as shown in fig. 3, wherein the width of each entry can be defined by parameters, and a larger width can increase the coverage rate or fault tolerance rate of the spanning tree, but increase the storage space and area of the hardware.
Further, in order to reduce the hardware area, the memory space of the router needs to be further optimized. Because the routing table is large, it can be realized by using a Static Random-Access Memory (SRAM) with the same space to replace the original register, and the area can be greatly reduced.
Furthermore, the required hardware area can be further reduced by sharing the routing table by local nodes. As shown in fig. 4, in the Mesh-type topology, 4 neighboring nodes may share the same routing table, because for the spanning tree routing method, the contents of the routing table entries stored in the global node are all the same and are all the same spanning tree ID, therefore, the 4 neighboring nodes may query the same routing table to obtain the global spanning tree ID.
Further, the invention provides a hardware architecture of the shared routing table. As shown in fig. 5, the shared routing table is connected to the adjacent 4 nodes through 4 interface modules, and the address of the specific routing table accessed by each interface is resolved and converted into an actual physical address through an address decoding module, and a request is issued to the corresponding physical Bank through cross-connection. The physical Bank module has an arbitrator for arbitrating the condition that different interfaces request the same Bank, wherein the request priority of each module can be configured through a register. The addresses of the physical banks are addressed by high bits, namely the physical addresses of a single Bank are progressive by 4, and adjacent addresses are distributed in different banks, so that the condition that a certain physical Bank is blocked frequently due to the fact that different interfaces request the adjacent addresses frequently can be relieved.
It is to be understood that the present invention has been described with reference to certain embodiments, and that various changes in the features and embodiments, or equivalent substitutions may be made therein by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (6)
1. A spanning tree routing hardware architecture based on shared storage for a network-on-chip comprises an input channel, a control logic and a cross switch, wherein the control logic controls a single routing process, and the cross switch controls cross interconnection of the input channel and an output channel; the input channel comprises three sub-modules which are respectively a route calculation module, a route table and an input buffer area; the input buffer area is used for storing input data packets, the route calculation module carries out path calculation through spanning tree route calculation according to the destination node label of each input data packet, outputs the corresponding output channel direction to the cross switch, controls the cross interconnection of the input channels and the output channels, local nodes share a route table, and nodes sharing the same route table inquire the same route table to obtain a global spanning tree ID.
2. The shared-storage-based spanning tree routing hardware architecture for network-on-chip chips of claim 1, wherein the routing table uses a block of same-space SRAM to replace the original registers.
3. The shared-storage-based spanning tree routing hardware architecture for network-on-chip chips of claim 1, wherein local nodes share a routing table, and in Mesh-type topology, neighboring 4 nodes share the same routing table, and the neighboring 4 nodes query the same routing table to obtain a global spanning tree ID.
4. The hardware architecture of claim 1, wherein the shared routing table is connected to 4 adjacent nodes through 4 interface modules, the address decoding module parses and converts the specific routing table address accessed by each interface into an actual physical address, and issues a request to the corresponding physical Bank through cross-connection, wherein the physical Bank module has an arbiter that arbitrates the case that different interfaces request the same Bank, the request priority of each module is configured by a register, the addresses of the physical banks are addressed by high bits, that is, the physical addresses of a single Bank are progressive with 4, and the adjacent addresses are distributed in different banks.
5. A method for spanning tree routing using the shared storage based spanning tree routing hardware architecture for network-on-chip chips of any of claims 1 to 4, wherein the spanning tree routing method finds shared branch nodes based on spanning tree IDs and routes packets first "up" to the branch nodes and then "down" to the destination node; before routing, breadth-first search is required to be carried out to configure a spanning tree ID, and the breadth-first search comprises the following steps:
step 1: determining a current search mode, wherein if the X direction is selected to be preferred, the east-west direction is preferred to search each time, and the south-north direction is firstly searched if the Y direction is preferred, and the following steps take the X direction as an example;
and 2, step: selecting a central node or other healthy nodes in the current topology as a root node, adding the root node or other healthy nodes into a queue, and marking the spanning tree ID, wherein at the moment, 1 node of the root node exists in the queue and only 1 node of the root node exists in the queue;
and step 3: setting a head node of a queue as a current node, and enqueuing and marking the node in the east-west direction of the current node if the node in the east-west direction of the current node is not marked; if the node in the south-north direction of the current node is not marked, enqueuing and marking the node, and when 4 neighbors of the node in the east, west, south and north directions are searched, dequeuing the current node;
and 4, step 4: and repeating the step 3 until the queue is empty, and at the moment, all the nodes which are positioned in the same connected graph with the root node are marked by the spanning tree.
6. The method according to claim 5, wherein the routing method is divided into the following cases: when the destination node and the source node are positioned on the same sub-branch and the destination node is positioned at the downstream of the sub-branch where the current node is positioned, the destination node is moved to the destination node along the current sub-branch downwards; when the destination node and the source node are positioned on the same sub-branch and the destination node is positioned at the upstream of the sub-branch where the current node is positioned, the destination node is moved to the destination node along the current sub-branch upwards; when the destination node and the source node are not located in the same sub-branch, the current node goes upwards along the sub-branch where the current node is located, the current node and the shared branch node closest to the destination node go to, and then the current node and the source node go downwards from the shared branch node along the sub-branch where the destination node is located.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5522045A (en) * | 1992-03-27 | 1996-05-28 | Panasonic Technologies, Inc. | Method for updating value in distributed shared virtual memory among interconnected computer nodes having page table with minimal processor involvement |
| US7480303B1 (en) * | 2005-05-16 | 2009-01-20 | Pericom Semiconductor Corp. | Pseudo-ethernet switch without ethernet media-access-controllers (MAC's) that copies ethernet context registers between PCI-express ports |
| CN104335535A (en) * | 2012-06-26 | 2015-02-04 | 英特尔公司 | Methods, apparatus, and systems for routing information flows in networks using spanning trees and network switching element resources |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6370145B1 (en) * | 1997-08-22 | 2002-04-09 | Avici Systems | Internet switch router |
| US20070110024A1 (en) * | 2005-11-14 | 2007-05-17 | Cisco Technology, Inc. | System and method for spanning tree cross routes |
| CN102035723A (en) * | 2009-09-28 | 2011-04-27 | 清华大学 | On-chip network router and realization method |
| CN103929782B (en) * | 2014-04-28 | 2017-06-06 | 西北工业大学 | A kind of resources balance multi-path route method suitable for industrial wireless sensor network |
| CN103986664B (en) * | 2014-05-15 | 2017-06-27 | 厦门大学 | A kind of mixing for network-on-chip interconnects Mesh topological structures and its routing algorithm |
| KR102287520B1 (en) * | 2015-01-27 | 2021-08-09 | 한국전자통신연구원 | Method for Managing Domain Routing Table in Router on Network Structure Based on Hierarchical Domain |
| US9571395B2 (en) * | 2015-02-09 | 2017-02-14 | Cavium, Inc. | Reconfigurable interconnect element with local lookup tables shared by multiple packet processing engines |
| CN105577539B (en) * | 2016-01-27 | 2018-08-10 | 中国科学院计算技术研究所 | A kind of method for routing and system towards irregular three dimensional integrated circuits network-on-chip |
| CN105871742B (en) * | 2016-03-24 | 2018-12-21 | 合肥工业大学 | Adaptive router based on virtual output queue mechanism in a kind of network-on-chip |
| CN106302163B (en) * | 2016-09-30 | 2019-05-10 | 南京航空航天大学 | A kind of network-on-chip router and method for routing with multiple-working mode |
-
2022
- 2022-05-05 CN CN202210479368.5A patent/CN114844827B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5522045A (en) * | 1992-03-27 | 1996-05-28 | Panasonic Technologies, Inc. | Method for updating value in distributed shared virtual memory among interconnected computer nodes having page table with minimal processor involvement |
| US7480303B1 (en) * | 2005-05-16 | 2009-01-20 | Pericom Semiconductor Corp. | Pseudo-ethernet switch without ethernet media-access-controllers (MAC's) that copies ethernet context registers between PCI-express ports |
| CN104335535A (en) * | 2012-06-26 | 2015-02-04 | 英特尔公司 | Methods, apparatus, and systems for routing information flows in networks using spanning trees and network switching element resources |
Non-Patent Citations (1)
| Title |
|---|
| 支持共享存储的千兆机群网络的实现;胡明昌等;《小型微型计算机***》;20070121(第01期);全文 * |
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