CN114844603A

CN114844603A - Signal detection method and device and memory

Info

Publication number: CN114844603A
Application number: CN202210448673.8A
Authority: CN
Inventors: 杨伟
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2022-08-02

Abstract

The embodiment of the application discloses a detection method, a detection device and a memory; the method comprises the following steps: acquiring a data signal and a data selection pulse; the data signal is controlled by a data selection pulse; determining a sampling moment set based on a preset detection mode; the sampling time set comprises a plurality of sampling times, wherein adjacent sampling times are different by a preset interval period; and sampling at least one of the data signal and the data selection pulse according to the sampling time set to obtain a corresponding sampling value. The method and the device can expand the detection result and improve the detection accuracy.

Description

Signal detection method and device and memory

Technical Field

The present application relates to, but is not limited to, a signal detection method, apparatus, and memory.

Background

In the memory, during the operation of the memory, a drift between the data select pulse and the data signal may occur, so that the relative time delay may be out of range, so that errors may occur in the read/write process. Therefore, the relative time delay between the data select pulse and the data signal needs to be measured and adjusted.

In the related art, the relative time delay between the data selection pulse and the data signal cannot be accurately reflected and is difficult to be effectively controlled.

Disclosure of Invention

In view of this, embodiments of the present application provide a signal detection method, a signal detection device, and a memory, which can extend a detection result and improve detection accuracy.

The technical scheme of the embodiment of the application is realized as follows:

the embodiment of the application provides a signal detection method, which comprises the following steps:

acquiring a data signal and a data selection pulse; the data signal is controlled by the data selection pulse;

determining a sampling moment set based on a preset detection mode; the sampling time set comprises a plurality of sampling times, wherein adjacent sampling times are different by a preset interval period;

and sampling at least one of the data signal and the data selection pulse according to the sampling time set to obtain a corresponding sampling value.

In the foregoing solution, after obtaining the corresponding sampling value, the method further includes: determining and storing a boundary location based on the sample value; the boundary position characterizes a first relative time delay of the data signal and the data select pulse.

In the foregoing solution, the determining and storing the boundary position based on the sampling value includes: and if the plurality of sampling values corresponding to any sampling time set are not completely the same, determining the boundary position of at least one of the data signal and the data selection pulse based on the plurality of sampling values corresponding to the sampling time set.

In the foregoing solution, if a plurality of sampling values corresponding to any sampling time set are not identical, determining a boundary position of at least one of the data signal and the data selection pulse based on the plurality of sampling values corresponding to the sampling time set includes:

if a plurality of sampling values corresponding to any sampling time set are not identical, determining two difference sampling values in the plurality of sampling values; the two different sampling values are two adjacent and different sampling values;

if the two difference sampling values belong to the data signal, determining that the boundary position of the data signal is located between two sampling moments corresponding to the two difference sampling values; and/or if the two difference sampling values belong to the data selection pulse, determining that the boundary position of the data selection pulse is positioned between two sampling moments corresponding to the two difference sampling values.

In the foregoing solution, the boundary position includes: a left boundary or a right boundary; if the two difference sample values belong to the data signal, determining that the boundary position of the data signal is located between two sampling moments corresponding to the two difference sample values, including:

if the two difference sampling values belong to the data signal, and the two difference sampling values are characterized in sequence: determining that the left boundary of the data signal is located between two sampling moments corresponding to the two difference sampling values if the data signal is at a low level-a high level; or, if the two difference sampling values belong to the data signal, and the two difference sampling values are sequentially characterized: determining that the right boundary of the data signal is located between two sampling moments corresponding to the two difference sampling values if the data signal is at a high level-a low level;

if the two difference sampling values belong to the data selection pulse, determining that the boundary position of the data selection pulse is located between two sampling moments corresponding to the two difference sampling values, including:

if the two difference sampling values belong to the data selection pulse, and the two difference sampling values are characterized in sequence: determining that the left boundary of the data selection pulse is positioned between two sampling moments corresponding to the two difference sampling values if the data selection pulse is at a low level-a high level; or, if the two difference sampling values belong to the data selection pulse, and the two difference sampling values are characterized in sequence: high level-low level, then it is determined that the right boundary of the data selection pulse is between the two sampling instants corresponding to the two difference sample values.

In the above scheme, the step of obtaining the sampling value includes:

determining a sampling range based on a preset detection mode;

determining an ith sampling time instant set within the sampling range; the ith set of sampling instants comprises a plurality of sampling instants; i is a positive integer;

sampling at least one of the data signal and the data select pulse based on the ith set of sampling instants to obtain a plurality of sampling values corresponding to the ith set of sampling instants;

and continuing to sample the next sampling time set until the Nth sampling time set exceeds the sampling range, and obtaining a plurality of sampling values corresponding to the N-1 sampling time sets.

In the foregoing solution, the determining an ith sampling time set in the sampling range includes:

selecting a pulse delay sampling delay time period from the data signal or the data to generate a plurality of first sampling signals; the sampling delay period is determined based on a pulse width of the data signal; the phases of the plurality of first sampling signals sequentially differ by the preset interval period;

a plurality of target boundary positions of the plurality of first sampling signals form a1 st sampling time set; each target boundary position is a first boundary position of each corresponding first sampling signal in the sampling range;

and delaying the plurality of first sampling signals by i-1 times of sampling period, and forming the ith sampling time set by the delayed target boundary positions.

selecting pulse frequency multiplication for the data signal or the data to generate a frequency multiplication data signal; the period of the frequency multiplication data signal is a sampling period;

delaying the frequency-doubled data signal to generate a plurality of second sampling signals; the phases of the plurality of second sampling signals sequentially differ by the preset interval period;

a plurality of ith boundary positions of the plurality of second sampling signals constitute the ith sampling time instant set; each ith boundary position is the ith boundary position of each corresponding second sampling signal in the sampling range.

In the foregoing solution, the preset detection mode includes: a tracking mode; the determining a sampling range based on a preset detection mode comprises: based on the tracking mode, determining a sampling range as a tracking sampling range taking a default boundary position as a reference; the default boundary position is the boundary position stored for the last signal detection.

In the foregoing solution, the preset detection mode includes: a scanning mode; the determining a sampling range based on a preset detection mode comprises: determining a sampling range as a scanning sampling range based on the scanning mode; the width of the scanning sampling range is the pulse width of the data signal or the pulse width of the data selection pulse.

In the foregoing solution, after determining and storing the boundary position based on the sampling value, the method further includes: adjusting at least one of the data signal and the data selection pulse based on the boundary position until a compensation parameter meets a preset compensation parameter range; the compensation parameter is used for compensating the first relative time delay to a standard relative time delay.

The embodiment of the present application further provides a signal detection apparatus, including:

a processor configured to acquire a data signal and a data selection pulse; the data signal is controlled by the data selection pulse; determining a sampling moment set based on a preset detection mode; the sampling time set comprises a plurality of sampling times, wherein adjacent sampling times are different by a preset interval period; and sampling at least one of the data signal and the data selection pulse according to the sampling time set to obtain a corresponding sampling value.

In the above scheme, the signal detection apparatus further includes: a storage unit; the processor further configured to determine and store a boundary location based on the sampled value; the boundary position characterizes a first relative time delay of the data signal and the data selection pulse; and adjusting at least one of the data signal and the data selection pulse based on the boundary position until a compensation parameter meets a preset compensation parameter range; the compensation parameter is used for compensating the first relative time delay to a standard relative time delay; the storage unit is configured to store the boundary position.

In the above solution, the storage unit includes: the device comprises a first storage module, a second storage module and a third storage module; the first storage module configured to store a pattern identification and to store a sampling delay period; the mode identification represents the preset detection mode; the sampling delay period is determined based on a pulse width of the data signal; the second storage module and the third storage module configured to store the boundary location; wherein the second storage module is configured to store a reduction of the current first relative delay with respect to the first relative delay obtained from the last signal detection, and to store a left boundary of the data signal; the third storage module is configured to store an increase of the current first relative delay with respect to the first relative delay obtained from the last signal detection, and to store a right boundary of the data signal.

In the above scheme, the signal detection apparatus further includes: a control register configured to control a start and an end of the signal detection.

In the above scheme, the processor is a system on chip SOC.

The embodiment of the application also provides a memory, and the memory comprises the signal detection device in the scheme.

Therefore, the embodiment of the application provides a signal detection method, a signal detection device and a memory, which can acquire a data signal and a data selection pulse, wherein the data signal is controlled by the data selection pulse; then, based on a preset detection mode, determining a sampling time set; the sampling time set comprises a plurality of sampling times, wherein adjacent sampling times are different by a preset interval period; and then, sampling at least one of the data signal and the data selection pulse according to the sampling time set to obtain a corresponding sampling value. Because the sampling performed each time is performed according to a plurality of sampling moments which are different by a preset interval period, the sampling value obtained each time can reflect not only the level of the signal, but also the change trend of the signal level, namely the phase relation of the signal. Therefore, by sampling at least one of the data signal and the data selection pulse, the current phase relation of the data signal and the data selection pulse can be detected in real time, so that the detection result is expanded, and the detection accuracy is improved.

Drawings

FIGS. 1A and 1B are schematic diagrams of a signal detection method in the related art;

fig. 2 is a first flowchart of a signal detection method according to an embodiment of the present disclosure;

fig. 3 is a second flowchart of a signal detection method according to an embodiment of the present disclosure;

fig. 4 is a first diagram illustrating an effect of a signal detection method according to an embodiment of the present disclosure;

fig. 5 is a flowchart of a signal detection method according to an embodiment of the present application;

fig. 6 is a fourth flowchart of a signal detection method according to an embodiment of the present application;

fig. 7 is a second effect diagram of a signal detection method according to an embodiment of the present application;

fig. 8 is a fifth flowchart of a signal detection method according to an embodiment of the present application;

fig. 9 is a sixth flowchart of a signal detection method according to an embodiment of the present application;

fig. 10 is a seventh flowchart of a signal detection method according to an embodiment of the present application;

fig. 11 is an eighth flowchart of a signal detection method according to an embodiment of the present application;

fig. 12 is a flowchart nine of a signal detection method according to an embodiment of the present application;

fig. 13 is a first schematic structural diagram of a signal detection apparatus according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a signal detection apparatus according to an embodiment of the present application;

fig. 15 is a schematic structural diagram of a memory according to an embodiment of the present application.

Detailed Description

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further described in detail with reference to the drawings and the embodiments, the described embodiments should not be considered as limiting the present application, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

To the extent that similar descriptions of "first/second" appear in this patent document, the description below will be added, where reference is made to the term "first \ second \ third" merely to distinguish between similar items and not to imply a particular ordering with respect to the items, it being understood that "first \ second \ third" may be interchanged with respect to a particular order or sequence as permitted, to enable the embodiments of the application described herein to be practiced in an order other than that illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.

In a memory, such as a DRAM (dynamic random access memory), the data selection pulse DQS is used to accurately distinguish each transmission cycle within one clock cycle so that the data signal DQ is accurately received, i.e., the data selection pulse DQS is used to control the reception of the data signal DQ. Relative time delay t between data signal DQ and data control signal DQS _DQSDQ It needs to be controlled within a certain range, otherwise, it may cause the data signal DQ to be received at the wrong time node, thereby causing errors in the read/write process in the DRAM. While in the operation of DRAMDue to the variation of the temperature and voltage of the particles, a drift between the data selection pulse DQS and the data signal DQ occurs, resulting in a relative time delay t _DQSDQ May be out of range and therefore, the relative time delay t needs to be adjusted _DQSDQ Measurements and adjustments are made.

In the related art, the delay of the DQS is adjusted according to the set curve of DQSOSC corresponding to a specific supplier, so the actual condition may not match the set curve of DQSOSC. Taking fig. 1A and 1B as an example, fig. 1A and 1B both represent the delay time of the data selection pulse DQS as a function of temperature, wherein the horizontal axis represents temperature and the vertical axis represents delay time. In fig. 1A, the variation trends of the actual curves a and B are substantially fitted to the variation trend of the set curve, so that the delay of the data selection pulse DQS may be adjusted according to the set curve. However, in fig. 1B, the variation trend of the actual curves C and D is very different from that of the set curve, and if the delay of the data selecting pulse DQS is adjusted according to the set curve, an error may be caused, and thus an error may occur in the read/write process of the memory granule. Meanwhile, since the data signal DQ also has a delay, it is difficult to adjust the delay of the data selection pulse DQs only for the relative delay t _DQSDQ And performing effective control.

In addition, the related art also has a problem that the relationship between the data signal DQ and the data control signal DQs inside the memory cell cannot be accurately reflected.

Fig. 2 is an alternative flow chart of a signal detection method provided in an embodiment of the present application, which will be described with reference to the steps shown in fig. 2.

S101, acquiring a data signal and a data selection pulse; the data signal is controlled by a data selection pulse.

In the embodiment of the present application, the signal detection method may be performed by a signal detection apparatus, and the signal detection apparatus may be integrated on a DRAM, and is used to detect the data signal DQ and the data selection pulse DQs in the DRAM. The signal detection device comprises a processor and a storage unit, wherein the storage unit is used for storing data related to signal detection, the processor is used for executing logic functions in the signal detection method, and the processor can be a system on chip SOC.

The processor may obtain a data signal DQ and a data selection pulse DQs from the DRAM, where the data selection pulse DQs is used to accurately distinguish each transmission cycle within one clock cycle, so that the data signal DQ is accurately received, that is, the data selection pulse DQs is used to control the reception of the data signal DQ.

S102, determining a sampling moment set based on a preset detection mode; the sampling time set comprises a plurality of sampling times, wherein adjacent sampling times are different by a preset interval period.

In this embodiment of the application, the preset detection mode may include: a tracking mode and a scanning mode. The storage unit of the signal detection device stores a mode identifier, and the mode identifier is used for representing a preset detection mode. The processor of the signal detection device may read the pattern identification from the memory unit to determine the preset detection pattern. For example, when the tracking mode is required, the mode identifier is set to 1, and after the processor reads the mode identifier which is 1 from the storage unit, the processor determines that the preset detection mode is the tracking mode; when the scanning mode is needed, the mode identifier is set to be 0, and after the processor reads the mode identifier which is 0 from the storage unit, the preset detection mode is determined to be the scanning mode.

It should be noted that, in the case that the preset detection mode only includes two modes, only one bit (bit) may be used in the storage unit to store the mode identifier. When the preset detection mode includes more than two modes, a plurality of bits are needed in the storage unit to store the mode identifier.

In this embodiment of the application, the processor may determine the set of sampling moments based on the determined preset detection mode. The sampling time set includes a plurality of sampling times, i.e., discrete time points on the signal timing diagram. The adjacent sampling moments are different by a preset interval time, the preset interval time can be set to be an integral multiple of the minimum interval time 2PI, and the minimum interval time 2PI can be determined according to the clock frequency in the DRAM.

In this embodiment, the processor may first determine the sampling range based on a preset detection mode. If the preset detection mode is the scan mode, the processor may determine that the sampling range is a scan sampling range, where a width of the scan sampling range is a pulse width of the data signal DQ or a pulse width of the data selection pulse DQs. If the preset detection mode is the tracking mode, the processor may determine that the sampling range is a tracking sampling range based on a default boundary position, where the default boundary position is a boundary position stored in the last signal detection. Here, the boundary position, i.e., the position where the signal changes, includes a left boundary and a right boundary, where the left boundary represents the position where the signal changes from low level to high level, and the right boundary represents the position where the signal changes from high level to low level.

Then, the processor may delay the data signal DQ or the data selection pulse DQs by a sampling delay period to generate a plurality of first sampling signals, where phases of the plurality of first sampling signals sequentially differ by a preset interval period. Here, the sampling delay period is determined based on the pulse width of the data signal, which may be stored in the storage unit. The processor may obtain a sampling delay period from the storage unit, delay the data signal DQ or the data selection pulse DQs by the sampling delay period, and sequentially delay by a preset interval period, thereby obtaining a plurality of first sampling signals.

And forming a1 st sampling time set by a plurality of target boundary positions of the plurality of first sampling signals, wherein each target boundary position is a first boundary position of each corresponding first sampling signal in a sampling range. For example, DQS _ a and DQS _ B are the first sampled signals generated by the processor, then DQS _ a is the first boundary position within the sample range as one target boundary position and DQS _ B is the first boundary position within the sample range as another target boundary position.

Furthermore, the processor may delay the plurality of first sampling signals by a sampling period of i-1 times, and the delayed target boundary positions may form an ith sampling time set, that is, the ith sampling time set is obtained by delaying the 1 st sampling time set by a sampling period of i-1 times, where i is a positive integer.

S103, sampling at least one of the data signal and the data selection pulse according to the sampling time set to obtain a corresponding sampling value.

In this embodiment of the application, the processor may obtain at least one corresponding signal value of the data signal DQ and the data selection pulse DQs at the sampling time in the sampling time set according to the sampling time set, that is, sample at least one of the data signal DQ and the data selection pulse DQs, and obtain a corresponding sampling value. Here, sampling at least one of the data signal DQS and the data selection pulse DQS includes sampling one of the data signal DQ or the data selection pulse DQS and sampling both the data signal DQ and the data selection pulse DQS. For example, in the first signal detection after the DRAM chip is turned on, the data selection pulse DQS is a preset standard value whose boundary position is known, and thus, only the data signal DQ needs to be sampled; in the first and subsequent signal detections, both the data signal DQ and the data select pulse DQs need to be sampled.

The sampled value represents the level of the signal at the sampling instant and may comprise 1 or 0, where 1 represents a high level and 0 represents a low level. One sampling instant corresponds to one sample value, so that a plurality of sample values can be obtained by the processor according to sampling performed by the sampling instant set.

In the embodiment of the application, the processor may perform sampling based on the ith sampling time set to obtain a plurality of sampling values corresponding to the ith sampling time set, and then continue sampling of the next sampling time set until the nth sampling time set exceeds the sampling range, thereby obtaining a plurality of sampling values corresponding to the N-1 sampling time sets within the sampling range. In this way, the processor completes the scan of the sample range.

It can be understood that, since each sampling is performed according to a plurality of sampling moments different by a preset interval period, each acquired sampling value can reflect not only the level of the signal, but also the variation trend of the signal level, i.e., the phase relationship of the signal. Therefore, by sampling at least one of the data signal and the data selection pulse, the current phase relation of the data signal and the data selection pulse can be detected in real time, so that the detection result is expanded, and the detection accuracy is improved.

In some embodiments of the present application, S104 shown in fig. 3 is further included after S103 shown in fig. 2, and will be described with reference to each step.

S104, determining and storing the boundary position based on the sampling value; the boundary position characterizes a first relative time delay of the data signal and the data select pulse.

In the embodiment of the application, the processor may determine the boundary position based on the sampling value, and store the boundary position in the storage unit. Wherein the boundary position may characterize a first relative time delay of the data signal and the data select pulse. The boundary position comprises the boundary position of the data signal DQ and the boundary position of the data selection pulse DQS, and the processor can determine a first relative delay, namely the relative delay t, according to the difference value of the boundary positions of the two signals after obtaining the boundary positions of the two signals _DQSDQ 。

In the embodiment of the application, after the processor obtains the boundary position, the processor can obtain the compensation parameter Offset, and store the compensation parameter Offset in the storage unit; the compensation parameter Offset represents a variation of the current boundary position with respect to the default boundary position adjusted by the previous signal detection, and may reflect an Offset degree of the current boundary position.

In the embodiment of the present application, if a plurality of sampling values corresponding to any sampling time set are not identical, the plurality of sampling values include two differential sampling values, and the two differential sampling values are two adjacent and different sampling values. For example, the difference sample value "01" is included in the plurality of sample values "0011", the difference sample value "10" is included in the plurality of sample values "1000", and the plurality of sample values "0000" and "1111" are identical, and the difference sample value is not included.

The processor, after determining that two difference sample values are included in the plurality of sample values, may determine that the boundary position is between two sample times corresponding to the two difference sample values. As illustrated in fig. 4, a plurality of sets of sampling instants may be derived from first sampling signals DQS _ a and DQS _ B (not shown in the figure), wherein the first set of sampling instants comprises sampling instants a1 and B1, the second set of sampling instants comprises sampling instants a2 and B2, the third set of sampling instants comprises sampling instants A3 and B3, and the fourth set of sampling instants comprises sampling instants a4 and B4. Since the preset interval period of the phase difference between the first sampling signals DQS _ a and DQS _ B is 2PI, the phase difference between the sampling times a1 and B1 is 2PI, the phase difference between the sampling times a2 and B2 is 2PI, the phase difference between the sampling times A3 and B3 is 2PI, and the phase difference between the sampling times a4 and B4 is 2 PI.

The processor samples the data signal DQ according to the first sampling time set to obtain a sampling value of 01; sampling the data signal DQ according to the second sampling time set to obtain a sampling value of '11'; sampling the data signal DQ according to the third sampling time set to obtain a sampling value of '10'; and sampling the data signal DQ according to the fourth sampling time set to obtain a sampling value of '00'. Thus, the processor may determine that the left boundary of the data signal DQ is located between the sampling times a1 and B1 because its corresponding sampling value represents that the data signal DQ changes from a low level to a high level; it can be determined that the right boundary of the data signal DQ is located between the sample times a3 and B3 because its corresponding sample value represents that the data signal DQ changes from high level to low level.

It can be understood that the current phase relationship between the data signal and the data selection pulse can be determined by processing the sampling value and determining the boundary position of the data signal and the data selection pulse from the sampling value, so that the detection result is expanded and the detection accuracy is improved.

In some embodiments of the present application, S104 shown in fig. 3 may be implemented by S1041, which will be described in conjunction with various steps.

S1041, if the plurality of sampling values corresponding to any sampling time set are not identical, determining a boundary position of at least one of the data signal and the data selection pulse based on the plurality of sampling values corresponding to the sampling time set.

In the embodiment of the present application, if a plurality of sampling values corresponding to any sampling time set are not identical, the plurality of sampling values include two differential sampling values, and the two differential sampling values are two adjacent and different sampling values. The processor, after determining that two difference sample values are included in the plurality of sample values, may determine that the boundary position is between two sample times corresponding to the two difference sample values. If the two difference sampling values represent that the signal is changed from low level to high level, the processor can determine that the left boundary of the signal is located between two sampling moments corresponding to the two difference sampling values; if the two difference sample values indicate that the signal changes from a high level to a low level, the processor may determine that the right boundary of the signal is between the two sampling instants corresponding to the two difference sample values.

In some embodiments of the present application, the foregoing S1041 may be implemented by S201 to S203 shown in fig. 5, and will be described with reference to each step.

S201, if a plurality of sampling values corresponding to any sampling time set are not identical, determining two different sampling values in the plurality of sampling values; the two different sampling values are two adjacent and different sampling values.

In the embodiment of the present application, if a plurality of sampling values corresponding to any sampling time set are not identical, the plurality of sampling values include two differential sampling values, and the two differential sampling values are two adjacent and different sampling values. For example, the difference sample value "01" is included in the plurality of sample values "0011", the difference sample value "10" is included in the plurality of sample values "1000", and the plurality of sample values "0000" and "1111" are identical, and the difference sample value is not included. The processor may determine two difference sample values from a plurality of sample values corresponding to the set of sample times.

S202, if the two difference sampling values belong to the data signal, determining that the boundary position of the data signal is located between two sampling moments corresponding to the two difference sampling values.

In the embodiment of the application, the processor can determine the boundary position of the corresponding signal according to the two difference sampling values. If the two differential sampling values belong to the data signal DQ, the processor may determine that the boundary position of the data signal DQ is located between two sampling instants corresponding to the two differential sampling values.

And S203, if the two difference sampling values belong to the data selection pulse, determining that the boundary position of the data selection pulse is positioned between two sampling moments corresponding to the two difference sampling values.

In the embodiment of the application, the processor can determine the boundary position of the corresponding signal according to the two difference sampling values. If the two differential sample values belong to the data selection pulse DQS, the processor may determine that the boundary position of the data selection pulse DQS is between two sampling times corresponding to the two differential sample values.

It can be understood that the boundary position of the signal corresponding to the difference sampling value is determined according to the difference sampling value, so that the boundary position of the data signal and the data selection pulse can be determined from the sampling value, that is, the current phase relationship between the data signal and the data selection pulse can be determined, and thus, the detection result is expanded, and the detection accuracy is improved.

In some embodiments of the present application, S202 shown in fig. 5 may be implemented by S2021 and S2022, which will be described in conjunction with the respective steps.

S2021, if the two difference sampling values belong to the data signal, and the two difference sampling values are characterized in sequence: low-high, it is determined that the left boundary of the data signal lies between the two sampling instants corresponding to the two difference sample values.

In the embodiment of the present application, if two differential sampling values belong to a data signal and the two differential sampling values are "01", that is, the two differential sampling values are sequentially characterized: low level-high level; the processor may determine that the left boundary of the data signal lies between two sample times corresponding to two difference sample values.

S2022, if the two difference sampling values belong to data signals, and the two difference sampling values are sequentially characterized: high-low, the right boundary of the data signal is determined to be between two sampling instants corresponding to the two difference sample values.

In the embodiment of the present application, if two difference sampling values belong to a data signal and the two difference sampling values are "10", that is, the two difference sampling values are sequentially characterized: high-low, the processor may determine that the right boundary of the data signal is between two sample times corresponding to two difference sample values.

In some embodiments of the present application, S203 shown in fig. 5 may be implemented by S2031 and S2032, which will be described in conjunction with the respective steps.

S2031, if the two difference sampling values belong to the data selection pulse, and the two difference sampling values are characterized in sequence: low-high, it is determined that the left boundary of the data select pulse is between two sample times corresponding to two difference sample values.

In the embodiment of the present application, if two difference sampling values belong to the data selection pulse, and the two difference sampling values are "01", that is, the two difference sampling values are sequentially characterized: low-high, the processor may determine that the left boundary of the data select pulse is between two sample times corresponding to two difference sample values.

S2032, if the two difference sampling values belong to the data selection pulse, and the two difference sampling values are characterized in sequence: high level-low level, it is determined that the right boundary of the data selection pulse is between two sampling instants corresponding to the two difference sample values.

In the embodiment of the present application, if two difference sampling values belong to the data selection pulse and the two difference sampling values are "10", that is, the two difference sampling values are sequentially characterized: high-low, the processor may determine that the right boundary of the data select pulse is between two sample times corresponding to two difference sample values.

It can be understood that the boundary positions of the data signal and the data selection pulse are respectively determined according to the difference sampling value, that is, the current phase relationship between the data signal and the data selection pulse can be determined, so that the detection result is expanded, and the detection accuracy is improved.

In some embodiments of the present application, the signal detection method further includes S301 to S304 shown in fig. 6, which will be described in conjunction with the respective steps.

S301, determining a sampling range based on a preset detection mode.

In this embodiment of the application, the preset detection mode may include: a tracking mode and a scanning mode. If the preset detection mode is the scan mode, the processor may determine, based on the scan mode, that the sampling range is a scan sampling range, where a width of the scan sampling range is a pulse width of the data signal DQ or a pulse width of the data selection pulse DQs. If the preset detection mode is the tracking mode, the processor may determine that the sampling range is a tracking sampling range based on a default boundary position, where the default boundary position is a boundary position stored in the last signal detection.

As illustrated in fig. 7, the pulse width of the data signal DQ is UI, i.e., the length of the time interval from the left boundary to the right boundary of the data signal DQ, and the width of the scan sampling range may be set to-UI to UI. Meanwhile, the pulse width UI of the data signal DQ may also be used as a measurement unit for measuring the time on the signal timing chart. For example, the default boundary position of the data select pulse DQS stored at the last signal detection may be represented as 1/2UI, representing that it has a time interval length of 1/2UI with the left boundary of the data signal DQ, and accordingly, the tracking sampling range may be set to a range of 1/2UI ± 1/4UI, i.e., a range of 1/4UI to 3/4 UI.

S302, determining an ith sampling moment set in a sampling range; the ith set of sampling instants comprises a plurality of sampling instants; i is a positive integer.

In this embodiment, after determining the sampling range, the processor may determine the 1 st sampling time set within the sampling range. Furthermore, the processor may also determine an ith sampling time set, a time interval between adjacent sampling time sets is a sampling period, and i is a positive integer. Each sampling moment set comprises a plurality of sampling moments, wherein the time interval between adjacent sampling moments is a preset interval period.

S303, sampling at least one of the data signal and the data selection pulse based on the ith sampling time set to obtain a plurality of sampling values corresponding to the ith sampling time set.

In this embodiment of the application, after determining the ith sampling time set, the processor may sample at least one of the data signal and the data selection pulse based on the ith sampling time set to obtain a plurality of sampling values corresponding to the ith sampling time set.

S304, continuing to sample the next sampling time set until the Nth sampling time set exceeds the sampling range, and obtaining a plurality of sampling values corresponding to the N-1 sampling time sets.

In the embodiment of the application, after the sampling of the ith sampling time set is completed, the processor can continue to sample the next sampling time set until the nth sampling time set exceeds the sampling range, and a plurality of sampling values corresponding to the N-1 sampling time sets are obtained. In this way, the processor completes the scan of the sample range.

It can be understood that different preset detection modes are adopted according to the detection requirement, different sampling ranges are correspondingly determined, and the flexibility of the detection method is improved. Meanwhile, the sampling result is obtained by scanning the sampling range, so that the sampling rate in the sampling range is improved, and the accuracy of the detection result can be improved.

In some embodiments of the present application, S302 shown in fig. 6 may be implemented by S401 to S404 shown in fig. 8, which will be described in conjunction with the steps.

S401, selecting a pulse delay sampling delay time period for a data signal or data to generate a plurality of first sampling signals; the sampling delay period is determined based on a pulse width of the data signal; the phases of the plurality of first sampling signals are sequentially different by a preset interval period.

In this embodiment, the processor may delay the data signal or the data selection pulse by a sampling delay period to generate a plurality of first sampling signals, where the sampling delay period is determined based on a pulse width of the data signal. Here, the sampling delay period is determined based on the pulse width of the data signal, which may be stored in the storage unit. The processor may obtain a sampling delay period from the storage unit, delay the data signal DQ or the data selection pulse DQs by the sampling delay period, and sequentially delay by a preset interval period, thereby obtaining a plurality of first sampling signals.

S402, forming a1 st sampling moment set by a plurality of target boundary positions of a plurality of first sampling signals; each target boundary position is a first boundary position of each corresponding first sampling signal in the sampling range.

In the embodiment of the present application, a plurality of target boundary positions of a plurality of first sampling signals form a1 st sampling time set, where each target boundary position is a first boundary position of each corresponding first sampling signal within a sampling range. For example, DQS _ a and DQS _ B are the first sampling signals generated by the processor, then the first sampling signal DQS _ a is at the first boundary position within the sampling range as one target boundary position, and the first sampling signal DQS _ B is at the first boundary position within the sampling range as another target boundary position.

And S403, delaying the plurality of first sampling signals by i-1 times of sampling period, and forming an ith sampling time set by the delayed target boundary positions.

In this embodiment, the processor may delay the plurality of first sampling signals by i-1 times of a sampling period, and the delayed target boundary position may form an ith sampling time set, that is, the ith sampling time set is obtained by delaying the 1 st sampling time set by i-1 times of the sampling period, where i is a positive integer.

It can be understood that a plurality of first sampling signals differing by a preset interval period are obtained by delaying a data signal or a data selection pulse, and a plurality of sampling moments differing by the preset interval period are obtained. Sampling is carried out at a plurality of sampling moments which differ by preset interval time periods, and a sampling value reflecting the phase relation of signals can be obtained, so that the detection result is expanded, and the detection accuracy is improved.

In some embodiments of the present application, S302 shown in fig. 6 may be implemented by S501 to S504 shown in fig. 9, which will be described in conjunction with the steps.

S501, selecting pulse frequency multiplication for the data signal or data to generate a frequency multiplication data signal; the period of the frequency multiplied data signal is the sampling period.

In this embodiment, the processor may frequency-multiply the data signal DQ or the data selection pulse DQs to generate a frequency-multiplied data signal. The period of the frequency-doubled data signal is a sampling period which is much shorter than the period of the data signal DQ or the data selection pulse DQs, and therefore, a plurality of boundary positions including the frequency-doubled data signal are correspondingly included in the sampling range.

S502, delaying the frequency multiplication data signal to generate a plurality of second sampling signals; the phases of the plurality of second sampling signals are sequentially different by a preset interval period.

In this embodiment of the application, the processor may sequentially delay the frequency-doubled data signal by a preset interval period to generate a plurality of second sampling signals. Since each second sampling signal has the same frequency as the frequency-multiplied data signal, a plurality of boundary positions including each second sampling signal are also corresponded within the sampling range.

S503, forming an ith sampling time set by a plurality of ith boundary positions of the plurality of second sampling signals; each ith boundary position is the ith boundary position of each corresponding second sampling signal in the sampling range.

In the embodiment of the present application, a plurality of ith boundary positions of a plurality of second sampling signals form an ith sampling time set, where each ith boundary position is an ith boundary position of each corresponding second sampling signal within a sampling range. For example, the DQS _ C and DQS _ D are second sampling signals generated by the processor, then the second sampling signals DQS _ C and DQS _ D both have multiple boundary positions within the sampling range, further, the 1 st boundary position of the second sampling signal DQS _ C within the sampling range and the 1 st boundary position of the second sampling signal DQS _ D within the sampling range form the 1 st sampling time set, and so on, the i th boundary position of the second sampling signal DQS _ C within the sampling range and the i th boundary position of the second sampling signal DQS _ D within the sampling range form the i th sampling time set.

Since the phases of the plurality of second sampling signals sequentially differ by the preset interval period, adjacent ith boundary positions in the ith sampling time set also differ by the preset interval period.

It can be understood that, by performing frequency multiplication and time delay on the data signal or the data selection pulse, a plurality of first sampling signals different by a preset interval period are obtained, and then a plurality of sampling moments different by the preset interval period are obtained. Sampling is carried out at a plurality of sampling moments which differ by preset interval time periods, and a sampling value reflecting the phase relation of signals can be obtained, so that the detection result is expanded, and the detection accuracy is improved.

In some embodiments of the present application, S301 shown in fig. 6 may be implemented by S601, which will be described in conjunction with various steps.

S601, based on the tracking mode, determining a sampling range as a tracking sampling range taking a default boundary position as a reference; the default boundary position is the boundary position stored for the last signal detection.

In the embodiment of the present application, the preset detection mode includes a tracking mode, and the tracking mode may be referred to as a tracking mode. The processor may determine, based on the tracking mode, the sampling range to be a tracking sampling range referenced to a default boundary position, wherein the default boundary position is a boundary position stored for a last signal detection. As illustrated in fig. 7, the default boundary position of the data select pulse DQS stored at the last signal detection may be represented as 1/2UI, representing that it has a time interval length of 1/2UI with the left boundary of the data signal DQ, and accordingly, the tracking sampling range may be set to a range of 1/2UI ± 1/4UI, i.e., a range of 1/4UI to 3/4 UI.

In the embodiment of the present application, when the data signal DQ and the data selecting pulse DQs are not known standard values, the processor needs to adopt a tracking mode, and at this time, the processor needs to sample both the data signal DQ and the data selecting pulse DQs.

In some embodiments of the present application, S301 shown in fig. 6 may be implemented by S602, which will be described in conjunction with various steps.

S602, determining a sampling range as a scanning sampling range based on a scanning mode; the width of the scanning sampling range is the pulse width of the data signal or the pulse width of the data selection pulse.

In the embodiment of the present application, the preset detection mode includes a scanning mode, and the tracking mode may be referred to as a shmoo mode. The processor may determine the sampling range as a scan sampling range based on the scan pattern, wherein the width of the scan sampling range is a pulse width of the data signal DQ or a pulse width of the data selection pulse DQs. As illustrated in fig. 7, the pulse width of the data signal DQ is UI, i.e., the length of the time interval from the left boundary to the right boundary of the data signal DQ, and the width of the scan sampling range may be set to-UI to UI.

In the embodiment of the present application, the processor may adopt a scan mode in the first signal detection after the DRAM chip is turned on. At this time, since the data selecting pulse DQS is a preset standard value and the boundary position thereof is known, the processor needs to determine the width of the scan sampling range according to the pulse width of the data signal DQ, and only sample the data signal DQ.

It can be understood that different preset detection modes are adopted according to the detection requirement, different sampling ranges are correspondingly determined, and the flexibility of the detection method is improved.

In some embodiments of the present application, S105 shown in fig. 10 is further included after S104 shown in fig. 3, and will be described in conjunction with various steps.

S105, based on the boundary position, adjusting at least one of the data signal and the data selection pulse until the compensation parameter meets a preset compensation parameter range; the compensation parameter is used for compensating the first relative time delay to the standard relative time delay.

In this embodiment, after determining the boundary position of the data signal DQ and the boundary position of the data selection pulse DQs, the processor may adjust at least one of the data signal and the data selection pulse based on the boundary positions, so as to adjust the first relative delay t between the data signal and the data selection pulse _DQSDQ Close to the standard relative time delay,so that the compensation parameter Offset satisfies the preset compensation parameter range, for example, the compensation parameter Offset is 0, i.e. the first relative time delay t _DQSDQ Equal to the standard relative time delay.

In the embodiment of the present application, the boundary position of the adjusted data selection pulse DQS may be stored in the storage unit as a default boundary position, so as to provide a reference for determining the tracking sampling range in the next tracking mode.

It can be understood that, by providing a reference for determining the tracking sampling range in the next tracking mode by adjusting at least one of the data signal and the data selection pulse, the determination process of the tracking sampling range in the next signal detection process can be optimized, and waste caused by an excessively large tracking sampling range is avoided.

In some embodiments of the present application, when the processor adopts the tracking mode, the method of signal detection may be implemented according to S611 to S616 shown in fig. 11, which will be described with reference to the steps.

S611, Sample Refresh (Sample Refresh). The processor may obtain a current data signal DQ and a data selection pulse DQs as a signal sample to be detected, i.e. refresh the signal sample to be detected.

S612, a Mode Register (Set Mode Register) is Set. After obtaining the current data signal DQ and the data selection pulse DQs, the processor may set data in a mode register (i.e., a memory cell) based on the current data signal DQ and the data selection pulse DQs, so as to perform current signal detection.

S613, signal detection and adjustment in the tracking mode (tracking mode) are performed. The processor may start the signal detection and adjustment in the tracking mode under the control of the control register MPC. The processor may perform trace mode detection on the signal sample to be detected based on the data in the mode register whose setting is completed, and adjust the current data signal DQ and the data selection pulse DQs according to the detection result.

And S614, confirming the Offset of the compensation parameter. The processor may read the Offset parameter from the mode register after completing the signal detection and adjustment once, and confirm the value of the Offset parameter.

And S615, uploading the adjusted signal. If Offset! If the value of the Offset parameter is not 0, the processor may upload the adjusted data signal DQ and the data select pulse DQs to perform the signal detection and adjustment in the tracking mode again.

And S616, ending and exiting detection. The processor may terminate and quit the detection under the control of the control register MPC after performing the signal detection and adjustment of the tracking mode at least once until the Offset is confirmed to be 0.

In some embodiments of the present application, when the processor adopts the scan mode, the method of signal detection may be implemented according to S621 to S625 shown in fig. 12, which will be described with reference to each step.

S621, Sample Refresh (Sample Refresh). The processor may obtain the current data signal DQ as a signal sample to be detected, i.e. refresh the signal sample to be detected.

S622, Set Mode Register (Set Mode Register) is Set. After acquiring the current data signal DQ, the processor may set data in a mode register (i.e., a memory cell) based on the current data signal DQ to perform current signal detection.

S623, signal detection and adjustment in the scan mode (shmoo mode) are performed. The processor may start the signal detection and adjustment of the scan mode under the control of the control register MPC. Under signal detection and adjustment in the scan mode, it is necessary to use the reference voltage Vref as a reference, which is located in the middle of the eye diagram. If the reference voltage Vref is calibrated, the processor may directly perform signal detection and adjustment in the scan mode, perform detection in the trace mode on a signal sample to be detected based on data in the mode register in which the setting is completed, and adjust the current data signal DQ and the data selection pulse DQs according to the detection result.

S624, Set the reference voltage (Set Vref). If the reference voltage Vref is not calibrated, the processor needs to calibrate the reference voltage Vref first, that is, set the reference voltage, and then perform signal detection and adjustment in the scan mode.

And S625, ending and exiting detection. After the signal detection and adjustment of the scan mode, the processor may terminate and quit the detection under the control of the control register MPC.

It can be understood that, according to the detection requirement, the signal detection and adjustment under different modes are carried out, thus enriching the detection method and improving the flexibility of the detection method.

Fig. 13 is an alternative structural schematic diagram of a signal detection apparatus according to an embodiment of the present application, and as shown in fig. 13, a signal detection apparatus 800 includes: a processor 801 and a memory unit 802. Wherein:

a processor 801 configured to acquire a data signal and a data selection pulse; the data signal is controlled by a data selection pulse; determining a sampling moment set based on a preset detection mode; the sampling time set comprises a plurality of sampling times, wherein adjacent sampling times are different by a preset interval period; sampling at least one of the data signal and the data selection pulse according to the sampling time set to obtain a corresponding sampling value;

the storage unit 802 is configured to store the boundary position and other data required to be stored in the signal detection apparatus 800.

In some embodiments of the present application, the processor 801 is further configured to determine and store the boundary location based on the sampled values; the boundary position represents a first relative time delay of the data signal and the data selection pulse; and adjusting at least one of the data signal and the data selection pulse based on the boundary position until the compensation parameter satisfies a preset compensation parameter range; the compensation parameter is used for compensating the first relative time delay to the standard relative time delay.

In some embodiments of the present application, as shown in fig. 14, the storage unit 802 includes: a first storage module 803, a second storage module 804, and a third storage module 805. Wherein:

a first storage module 803 configured to store a pattern identification and to store a sampling delay period; the mode identification represents a preset detection mode; the sampling delay period is determined based on a pulse width of the data signal;

a second storage module 804 and a third storage module 805 configured to store boundary locations; wherein the second storage module 804 is configured to store a reduction of the current first relative delay with respect to the first relative delay obtained from the last signal detection, and to store a left boundary of the data signal; the third storing module 805 is configured to store an increase amount of the current first relative delay with respect to the first relative delay obtained from the last signal detection, and store the right boundary of the data signal.

In this embodiment of the application, the first storage module 803 stores a mode identifier, where the mode identifier is used to represent a preset detection mode. The processor 801 may read the mode identification from the first storage module 803 to determine the preset detection mode. In the case that the preset detection mode only includes two modes, namely the tracking mode and the scanning mode, the first storage module 803 may store the mode identifier with only one bit, for example, 0 is used for characterizing the scanning mode, and 1 is used for characterizing the tracking mode.

In this embodiment, the first storage module 803 further stores the sampling delay time period. The processor 801 may read the sample delay period from the first memory module 803 and delay the data signal DQ or the data select pulse DQs by the sample delay period to generate a plurality of first sample signals. The first storage module 803 may store the sampling delay period with two bits; the first storage module 803 may also store the sampling delay period with more than two bits, enabling the sampling delay period to be more accurate.

In this embodiment of the application, the second storage module 804 may store, by using 3 bits, a reduction amount (i.e., an advance amount of a time) of the current first relative delay with respect to the first relative delay obtained by the last signal detection, so as to be read and used by the processor 801 in the tracking mode. The second memory block 804 also stores the left boundary of the data signal with two registers for the processor 801 to read and use in scan mode.

In this embodiment, the third storage module 805 may store, by using 3 bits, an increase amount (i.e., a delay amount of a time) of the current first relative delay with respect to the first relative delay obtained by the last signal detection, so as to be read and used by the processor 801 in the tracking mode. The second memory block 804 also stores the right boundary of the data signal with two registers for the processor 801 to read and use in scan mode.

In some embodiments of the present application, the signal detection apparatus 800 further comprises: a control register (MPC)806 configured to control the start and end of signal detection.

In some embodiments of the present application, processor 801 is a system on chip SOC.

It should be noted that fig. 15 is an alternative structural schematic diagram of the memory provided in the embodiment of the present application, and as shown in fig. 15, the memory 900 includes a signal detection apparatus 800. The signal detection apparatus 800 may be integrated on the memory 900 for detecting signals in the memory 900, so that real-time detection of the memory 900 is realized, and the integration level of the memory 900 is improved.

Here, it should be noted that: the above description of the memory and device embodiments, similar to the above description of the method embodiments, has similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the storage medium and apparatus of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.

In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of signal detection, comprising:

2. The signal detection method of claim 1, wherein after obtaining the corresponding sample value, the method further comprises:

determining and storing a boundary location based on the sample value; the boundary position characterizes a first relative time delay of the data signal and the data select pulse.

3. The signal detection method of claim 2, wherein said determining and storing boundary locations based on said sampled values comprises:

and if the plurality of sampling values corresponding to any sampling time set are not completely the same, determining the boundary position of at least one of the data signal and the data selection pulse based on the plurality of sampling values corresponding to the sampling time set.

4. The signal detection method of claim 3, wherein if the plurality of sampling values corresponding to any sampling time set are not identical, determining the boundary position of at least one of the data signal and the data selection pulse based on the plurality of sampling values corresponding to the sampling time set comprises:

if the two difference sampling values belong to the data signal, determining that the boundary position of the data signal is located between two sampling moments corresponding to the two difference sampling values; and/or the presence of a gas in the gas,

and if the two difference sampling values belong to the data selection pulse, determining that the boundary position of the data selection pulse is positioned between two sampling moments corresponding to the two difference sampling values.

5. The signal detection method of claim 4, wherein the boundary position comprises: a left boundary or a right boundary; if the two difference sample values belong to the data signal, determining that the boundary position of the data signal is located between two sampling moments corresponding to the two difference sample values, including:

if the two difference sampling values belong to the data signal, and the two difference sampling values are characterized in sequence: determining that the left boundary of the data signal is located between two sampling moments corresponding to the two difference sampling values if the data signal is at a low level-a high level; alternatively, the first and second electrodes may be,

if the two difference sampling values belong to the data signal, and the two difference sampling values are characterized in sequence: determining that the right boundary of the data signal is located between two sampling moments corresponding to the two difference sampling values if the data signal is at a high level-a low level;

if the two difference sampling values belong to the data selection pulse, and the two difference sampling values are characterized in sequence: determining that the left boundary of the data selection pulse is positioned between two sampling moments corresponding to the two difference sampling values if the data selection pulse is at a low level-a high level; alternatively, the first and second electrodes may be,

if the two difference sampling values belong to the data selection pulse, and the two difference sampling values are characterized in sequence: high level-low level, then it is determined that the right boundary of the data selection pulse is between the two sampling instants corresponding to the two difference sample values.

6. The signal detection method of claim 1, wherein the step of obtaining the sampled values comprises:

determining a sampling range based on a preset detection mode;

7. The signal detection method of claim 6, wherein determining the ith set of sampling instants within the sampling range comprises:

delaying the first sampling signals by i-1 times of sampling period, and forming the ith sampling time set by the delayed target boundary positions.

8. The signal detection method of claim 6, wherein determining the ith set of sampling instants within the sampling range comprises:

9. The signal detection method of claim 6, wherein the preset detection mode comprises: a tracking mode; the determining a sampling range based on a preset detection mode comprises:

based on the tracking mode, determining a sampling range as a tracking sampling range taking a default boundary position as a reference; the default boundary position is the boundary position stored for the last signal detection.

10. The signal detection method of claim 6, wherein the preset detection mode comprises: a scanning mode; the determining the sampling range based on the preset detection mode comprises the following steps:

determining a sampling range as a scanning sampling range based on the scanning mode; the width of the scanning sampling range is the pulse width of the data signal or the pulse width of the data selection pulse.

11. The signal detection method of claim 2, wherein after determining and storing the boundary location based on the sampled value, the method further comprises:

adjusting at least one of the data signal and the data selection pulse based on the boundary position until a compensation parameter meets a preset compensation parameter range; the compensation parameter is used for compensating the first relative time delay to a standard relative time delay.

12. A signal detection device, comprising:

13. The signal detection device of claim 12, further comprising: a storage unit;

the processor further configured to determine and store a boundary location based on the sampled value; the boundary position characterizes a first relative time delay of the data signal and the data selection pulse; and adjusting at least one of the data signal and the data selection pulse based on the boundary position until a compensation parameter meets a preset compensation parameter range; the compensation parameter is used for compensating the first relative time delay to a standard relative time delay;

the storage unit is configured to store the boundary position.

14. The signal detection device according to claim 13, wherein the storage unit includes: the device comprises a first storage module, a second storage module and a third storage module;

the first storage module configured to store a pattern identification and to store a sampling delay period; the mode identification represents the preset detection mode; the sampling delay period is determined based on a pulse width of the data signal;

the second storage module and the third storage module configured to store the boundary location; wherein the second storage module is configured to store a reduction of the current first relative delay with respect to the first relative delay obtained from the last signal detection, and to store a left boundary of the data signal; the third storage module is configured to store an increase of the current first relative delay with respect to the first relative delay obtained from the last signal detection, and to store a right boundary of the data signal.

15. The signal detection device of claim 12, further comprising:

a control register configured to control a start and an end of the signal detection.

16. The signal detection device of claim 12, wherein the processor is a system on a chip (SOC).

17. A memory, characterized in that the memory comprises a signal detection device according to any one of claims 12 to 16.