CN114826165A - Compact Doherty power amplifier - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/04—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers
- H03F1/06—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers to raise the efficiency of amplifying modulated radio frequency waves; to raise the efficiency of amplifiers acting also as modulators
- H03F1/07—Doherty-type amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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Abstract
The invention relates to a compact Doherty power amplifier, belongs to the technical field of radio frequency power amplifiers, and solves the problems of low working efficiency and low circuit gain of the conventional Doherty power amplifier. The Doherty power amplifier comprises: the driving power amplifying circuit is connected to the input end of the power divider; the carrier power amplifying circuit is connected to one output end of the power divider and comprises a carrier output matching network; and the peak power amplifying circuit is connected to the other output end of the power divider and comprises a peak output matching network and a pi-shaped microstrip compensation line. The double-impedance point matching of the carrier power amplifier is realized, and the working efficiency of the carrier power amplifier in the working process of a backspacing power point and a saturation working point is improved.
Description
Technical Field
The invention relates to the technical field of radio frequency power amplifiers, in particular to a compact Doherty power amplifier.
Background
Currently, 5G technology has become a hot spot for countless research workers, however, the implementation of 5G technology requires an excessively hard hardware infrastructure. A small base station is one of the hardware infrastructures implementing the 5G technology. The radio frequency power amplifier is a core component in a 5G small base station and plays an important role in the small base station. In order to find a radio frequency power amplifier architecture capable of meeting the current requirements of the 5G small base station, a radio frequency power amplifier based on a Doherty architecture gradually appears in the visual field of people. The power amplifier with the framework has higher efficiency and better linearity at a power amplifier backspacing working point, so that the Doherty power amplifier becomes a hot spot of current research.
The traditional Doherty power amplifier has low working efficiency and small circuit gain, and cannot meet the requirement of a current 5G communication system on a radio frequency power amplifier, so that a compact high-efficiency high-gain Doherty power amplifier suitable for a 5G communication base station in the future is lacked.
Disclosure of Invention
In view of the foregoing, embodiments of the present invention provide a compact Doherty power amplifier to solve the problems of low operating efficiency and low circuit gain of the conventional Doherty power amplifier.
In one aspect, an embodiment of the present invention provides a compact Doherty power amplifier, including:
the driving power amplifying circuit is connected to the input end of the power divider;
the carrier power amplifying circuit is connected to one output end of the power divider and comprises a carrier output matching network;
and the peak power amplifying circuit is connected to the other output end of the power divider and comprises a peak output matching network and a pi-shaped microstrip compensation line.
Further, when a first power signal is input to the driving power amplification circuit, the carrier output matching network matches the load impedance of the carrier power transistor to the combining point impedance, the pi-type microstrip compensation line matches the load impedance of the peak power transistor to infinity, and the carrier power amplification circuit amplifies the first power signal;
when a second power signal is input to the driving power amplification circuit, the carrier output matching network matches the load impedance of the carrier power transistor to 150 ohms, the peak output matching network matches the load impedance of the peak power transistor to 75 ohms, and the carrier power amplification circuit and the peak power amplification circuit jointly achieve amplification of the second power signal.
Further, the carrier power amplifying circuit further comprises a carrier input matching network connected between one input end of the power divider and the carrier power transistor;
the carrier input matching network comprises a first inductor, a first capacitor and a second capacitor; one end of the first inductor is connected with one end of the first capacitor and one end of the second capacitor at the same time, the other end of the first inductor is connected with a grid electrode of the carrier power transistor, the other end of the first capacitor is an input end of the carrier input matching network, and the other end of the second capacitor is grounded.
Further, the carrier output matching network is connected between the carrier power transistor and the combining point and comprises a first microstrip line, a third capacitor and a fourth capacitor, one end of the first microstrip line is connected with one end of the third capacitor, the other end of the first microstrip line is an output end of the carrier output matching network, the output end of the carrier output matching network is further connected with one end of the fourth capacitor, one end of the third capacitor is connected with a drain electrode of the carrier power transistor, and the other end of the fourth capacitor is grounded.
Furthermore, the carrier power amplifying circuit also comprises a pi-type phase compensation network connected between one output end of the power divider and the carrier input matching network;
the pi-type phase compensation network comprises a second inductor, a fifth capacitor and a sixth capacitor, and the fifth capacitor and the sixth capacitor are respectively connected to two ends of the second inductor; one end of the second inductor is an input end of the pi-type phase compensation network, and the other end of the second inductor is an output end of the pi-type phase compensation network.
Further, the peak power amplifying circuit further comprises a peak input matching network;
the peak value input matching network comprises a second microstrip line, a seventh capacitor and an eighth capacitor, one end of the second microstrip line is simultaneously connected with one end of the seventh capacitor and one end of the eighth capacitor, the other end of the seventh capacitor is an input end of the peak value input matching network, the other end of the eighth capacitor is grounded, and the other end of the second microstrip line is an output end of the peak value input matching network.
Further, the peak output matching network includes a third microstrip line, a ninth capacitor and a tenth capacitor, the third microstrip line is connected to one end of the ninth capacitor and one end of the tenth capacitor, the other end of the ninth capacitor is an input end of the peak output matching network, and the other end of the tenth capacitor is grounded.
Further, the pi-type microstrip compensation line comprises a fourth microstrip line and an eleventh capacitor, and shares a tenth capacitor with the peak output matching network; the tenth capacitor and the eleventh capacitor are respectively connected to two ends of a fourth microstrip line, and the two ends of the fourth microstrip line are respectively an input end and an output end of the pi-shaped microstrip compensation line.
Further, the driving power amplifying circuit comprises a driving input matching network, a driving power transistor and a driving output matching network;
the driving input matching network comprises a first resistor, a third inductor, a twelfth capacitor, a thirteenth capacitor and a fourteenth capacitor; the first resistor is connected with the twelfth capacitor in parallel, one end of the first resistor after the parallel connection is an output end of the driving input matching network, the other end of the first resistor after the parallel connection is connected with one end of the third inductor, the other end of the third inductor is simultaneously connected with one end of the thirteenth capacitor and one end of the fourteenth capacitor, the other end of the thirteenth capacitor is an input end of the driving input matching network, and the other end of the fourteenth capacitor is grounded;
the drive output matching network comprises a fifth microstrip line, a fifteenth capacitor and a sixteenth capacitor; one end of the fifth microstrip line is connected with one end of a fifteenth capacitor, the other end of the fifth microstrip line is an output end of the driving output matching network, the other end of the fifteenth capacitor is an input end of the driving output matching network, and the sixteenth capacitor is connected between the output end of the driving output matching network and the ground.
Further, the device also comprises an input bias circuit connected with the grids of the carrier power transistor, the peak power transistor and the driving power transistor; the input bias network comprises a fourth inductor, a second resistor and a first direct-current voltage source; one end of the fourth inductor is an input end of the input bias network, the other end of the fourth inductor is connected with one end of the second resistor, the other end of the second resistor is connected with a positive polarity end of the direct current voltage source, and a negative polarity end of the direct current voltage source is grounded;
the output bias circuit is connected to the drains of the carrier power transistor, the peak power transistor and the driving power transistor; the output bias network comprises a fifth inductor and a second direct current voltage source; one end of the fifth inductor is an input end of the output bias network, the other end of the fifth inductor is connected with a positive polarity end of the second direct-current voltage source, and a negative polarity end of the second direct-current voltage source is grounded.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. a compact Doherty power amplifier provides driving power for a power divider, a carrier power amplifying circuit and a peak power amplifying circuit through a driving power amplifying circuit, and improves the gain of the whole circuit. Meanwhile, through the mutual matching of the carrier output matching network, the peak output matching network and the pi-shaped microstrip compensation line, the double-impedance point matching of the carrier power amplifier is realized, and the working efficiency of the carrier power amplifier in the working process of a backspacing power point and a saturation working point is improved. When a low-power signal is input, the carrier output matching network matches the load impedance of the carrier power amplifier to the combining point impedance, and when a high-power signal is input, the carrier output matching network and the peak output matching network are matched with each other, so that the effect of matching the parallel load impedance of the carrier power amplifying circuit and the peak power amplifying circuit to the combining point impedance is realized, the matching network is not needed after the combining point is set, the size of the whole amplifier is reduced, and the compact layout is realized.
2. The n-shaped phase compensation network in the carrier power amplifying circuit is used for compensating the phase difference between the carrier power amplifying circuit and the peak power amplifying circuit, and the gain of the whole circuit is improved.
3. The output power of the carrier power amplifying circuit is ensured not to leak when the peak power amplifier is not started through the pi-shaped microstrip compensation line, namely, when the carrier power amplifier works at a backspacing point, the load impedance of the peak power transistor is in a high-impedance state. Meanwhile, the pi-type microstrip compensation line and the peak output matching network share the capacitor C17, so that the circuit size can be reduced, and the cost is saved.
4. By arranging the input bias circuit and the output bias circuit of the drain electrode which are connected with the grid electrodes of the carrier power transistor, the peak power transistor and the driving power transistor, stable direct-current voltage is provided for the grid electrode and the drain electrode of the transistor, the interference of radio-frequency signals to a direct-current power supply is prevented, and the stability of the whole circuit is improved.
In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
Fig. 1 is a schematic diagram of the overall structure of a compact Doherty power amplifier in one embodiment;
fig. 2 is a schematic diagram of the internal structure of the compact Doherty power amplifier in one embodiment.
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.
The traditional Doherty power amplifier has low working efficiency and small circuit gain, and cannot meet the requirement of the current 5G communication system on radio frequency power amplification, so that the application provides a compact Doherty power amplifier. The drive power amplifying circuit, the carrier power amplifying circuit and the peak power amplifying circuit are matched with each other, so that the amplification of an input signal is realized, and the working efficiency and the circuit gain of the Doherty power amplifier are improved.
A specific embodiment of the present invention discloses a compact Doherty power amplifier, as shown in fig. 1, including: the driving power amplifying circuit is connected to the input end of the power divider;
the carrier power amplifying circuit is connected to one output end of the power divider and comprises a carrier output matching network;
the peak power amplifying circuit is connected to the other output end of the power divider and comprises a peak output matching network and a pi-shaped microstrip compensation line;
when a first power signal is input to the drive power amplification circuit, the carrier output matching network matches the load impedance of the carrier power transistor to the combining point impedance, the pi-type microstrip compensation line matches the load impedance of the peak power transistor to infinity, and the carrier power amplification circuit amplifies the first power signal;
when a second power signal is input to the driving power amplification circuit, the load impedance of the carrier power transistor is matched to 150 ohms by the carrier output matching network, the load impedance of the peak power transistor is matched to 75 ohms by the peak output matching network, and the amplification of the second power signal is realized by the carrier power amplification circuit and the peak power amplification circuit together.
Specifically, the power of the first power signal is lower than the power of the second power signal. The first power signal is a low power signal, so that the signal when the carrier power transistor is turned on is a low power signal. The second power signal is a high power signal, so that the signal when the peak power transistor is turned on is a high power signal. When a low-power signal is input into the driving power amplifying circuit, the carrier power amplifying circuit works at a power back-off point, at the moment, the carrier output matching network matches the load impedance of the carrier power transistor to 50 ohms, the pi-type microstrip compensation line matches the load impedance of the peak power transistor to infinity, and the carrier power amplifying circuit amplifies the first power signal. When a high-power signal is input into the driving power amplifying circuit, the carrier power amplifying circuit works at a power saturation point, the carrier output matching network matches the load impedance of the carrier power transistor to 150 ohms, the peak output matching network matches the load impedance of the peak power transistor to 75 ohms, the parallel load impedance of the carrier power amplifying circuit and the peak power amplifying circuit is 50 ohms, and the carrier power amplifying circuit and the peak power amplifying circuit jointly achieve amplification of a second power signal.
In implementation, the carrier power transistor and the peak power transistor are both GaN HEMT transistors.
Compared with the prior art, the compact Doherty power amplifier provided by the embodiment provides driving power for the power divider, the carrier power amplifying circuit and the peak power amplifying circuit through the driving power amplifying circuit, so that the gain of the whole circuit is improved. Meanwhile, through the mutual matching of the carrier output matching network, the peak output matching network and the pi-shaped microstrip compensation line, the double-impedance point matching of the carrier power amplifier is realized, and the working efficiency of the carrier power amplifier at a backspacing power point and the higher working efficiency of the carrier power amplifier when the carrier power amplifier works at a saturation working point are improved. When a low-power signal is input, the carrier output matching network matches the load impedance of the carrier power amplifier to the combining point impedance, and when a high-power signal is input, the carrier output matching network and the peak output matching network are matched with each other, so that the effect of matching the parallel load impedance of the carrier power amplifying circuit and the peak power amplifying circuit to the combining point impedance is realized, the matching network is not needed after the combining point is set, the size of the whole amplifier is reduced, and the compact layout is realized.
Preferably, as shown in fig. 2, the carrier power amplifying circuit further includes a carrier input matching network IMN2 connected between one input terminal of the power divider and the carrier power transistor. The carrier input matching network IMN2 includes a first inductor L5, a first capacitor C10, and a second capacitor C11; one end of the first inductor L5 is connected to one end of the first capacitor C10 and one end of the second capacitor C11 at the same time, the other end of the first inductor L5 is connected to the gate of the carrier power transistor, the other end of the first capacitor C10 is the input end of the carrier input matching network, and the other end of the second capacitor C11 is grounded.
The carrier output matching network OMN2 is connected between the carrier power transistor and the combining point and comprises a first microstrip line Z2, a third capacitor C12 and a fourth capacitor C13, one end of the first microstrip line Z2 is connected with one end of the third capacitor C12, the other end of the first microstrip line Z2 is an output end of the carrier output matching network, the output end of the carrier output matching network is further connected with one end of the fourth capacitor C13, one end of the third capacitor C12 is connected with a drain electrode of the carrier power transistor, and the other end of the fourth capacitor C13 is grounded.
Specifically, to improve the operating efficiency, the carrier power transistor in the carrier power amplifier circuit operates in class AB. The capacitor C12 in the carrier output matching network is a dc blocking capacitor, and has the functions of blocking dc signals and allowing rf signals to pass through. The load impedances corresponding to the carrier power transistor at the back-off operating point and the saturation operating point are different. When the carrier power transistor works at a backspacing working point, the load impedance of the carrier power transistor can be matched to 50 ohms by adjusting the values of a microstrip line Z2 and a capacitor C13 in the carrier output matching network; when the carrier power transistor works at a saturated working point, the load impedance of the carrier power transistor can be matched to 150 ohms by adjusting the values of the microstrip line Z2 and the capacitor C13 in the carrier output matching network, so that the working efficiency of the carrier power transistor at different working points is improved on the premise of not influencing the saturated output power of the Doherty power amplifier.
Preferably, the carrier power amplifying circuit further comprises a pi-type phase compensation network connected between one output end of the power divider and the carrier input matching network; the pi-type phase compensation network comprises a second inductor L4, a fifth capacitor C8 and a sixth capacitor C9, wherein the fifth capacitor C8 and the sixth capacitor C9 are respectively connected to two ends of the second inductor L4; one end of the second inductor L4 is an input end of the pi-type phase compensation network, and the other end is an output end of the pi-type phase compensation network.
Specifically, the pi-type phase compensation network is formed by connecting an inductor and two grounded capacitors, wherein the two grounded capacitors have the same value. The pi-type phase compensation network in the carrier power amplification circuit is used for compensating the phase difference between the carrier power amplification circuit and the peak power amplification circuit, so that the whole amplifier circuit is more stable, and the gain of the whole circuit is improved.
Preferably, the peak power amplifying circuit further comprises a peak input matching network IMN 3; the peak input matching network comprises a second microstrip line Z3, a seventh capacitor C14 and an eighth capacitor C15, one end of the second microstrip line Z2 is simultaneously connected with one end of the seventh capacitor C14 and one end of the eighth capacitor C15, the other end of the seventh capacitor C14 is an input end of the peak input matching network, the other end of the eighth capacitor C15 is grounded, and the other end of the second microstrip line Z3 is an output end of the peak input matching network.
The peak output matching network OMN3 includes a third microstrip line Z4, a ninth capacitor C16, and a tenth capacitor C17, the third microstrip line Z4 is connected to one end of the ninth capacitor C16 and one end of the tenth capacitor C17, the other end of the ninth capacitor C16 is an input end of the peak output matching network, and the other end of the tenth capacitor C17 is grounded.
Specifically, to ensure operating efficiency, the peak power transistor is biased in class C. The capacitor C16 in the peak output matching network is a dc blocking capacitor, and has the function of blocking dc signals and allowing rf signals to pass through. When the drive power amplifying circuit inputs a high-power signal, the load impedance of the carrier power transistor can be matched to 150 ohms by adjusting the values of the microstrip line Z2 and the capacitor C13 in the carrier output matching network, the load impedance of the peak power transistor can be matched to 75 ohms by adjusting the values of the microstrip line Z4 and the capacitor C17 in the peak output matching network, so that the parallel load impedance of the carrier power amplifying circuit and the peak power amplifying circuit is 50 ohms and can be directly connected to a combined load, and the amplification of the input high-power signal is realized by the carrier power amplifying circuit and the peak power amplifying circuit together.
Preferably, the pi-type microstrip compensation line comprises a fourth microstrip line Z5 and an eleventh capacitor C18, and shares a tenth capacitor C17 with the peak output matching network; the tenth capacitor C17 and the eleventh capacitor C18 are respectively connected to two ends of the fourth microstrip line Z5, and two ends of the fourth microstrip line Z5 are respectively an input end and an output end of the pi-type microstrip compensation line.
Specifically, the output end of the peak output matching network is connected with the pi-type microstrip compensation line, so that the output power of the carrier power amplifying circuit is prevented from leaking when the peak power amplifier is not started, namely when the carrier power amplifier works at a backspacing point, the load impedance of the peak power transistor is in a high-impedance state. The pi-type microstrip compensation line is formed by combining a section of microstrip line and two grounding capacitors with the same capacitance value, and the grounding capacitor in the pi-type microstrip compensation line can be combined with the grounding capacitor in the matching network close to the peak output, i.e. the pi-type microstrip compensation line and the matching network share the capacitor C17 in the attached figure 2, thereby reducing the circuit size and saving the cost.
Preferably, the driving power amplifying circuit includes a driving input matching network IMN1, a driving power transistor, and a driving output matching network OMN 1. The driving input matching network comprises a first resistor R1, a third inductor L1, a twelfth capacitor C3, a thirteenth capacitor C1 and a fourteenth capacitor C2; the first resistor R1 is connected in parallel with the twelfth capacitor C3, one end of the parallel connection is an output end of the driving input matching network, the other end of the parallel connection is connected with one end of the third inductor, the other end of the third inductor is simultaneously connected with one end of the thirteenth capacitor C1 and one end of the fourteenth capacitor C2, the other end of the thirteenth capacitor C1 is an input end of the driving input matching network, and the other end of the fourteenth capacitor C2 is grounded.
The driving output matching network comprises a fifth microstrip line Z1, a fifteenth capacitor C4 and a sixteenth capacitor C5; one end of the fifth microstrip line Z1 is connected to one end of the fifteenth capacitor C4, the other end is an output end of the driving output matching network, the other end of the fifteenth capacitor C4 is an input end of the driving output matching network, and the sixteenth capacitor C5 is connected between the output end of the driving output matching network and the ground.
Specifically, to ensure the operation efficiency, the driving power transistor operates in class AB. The drive input matching network comprises an RC stable network, and the whole circuit can be kept stable without oscillation by adjusting the RC stable network, so that the stability of the whole circuit is improved.
Preferably, the device further comprises an input bias circuit connected to the gates of the carrier power transistor, the peak power transistor and the driving power transistor; the input bias network comprises a fourth inductor, a second resistor and a first direct-current voltage source; one end of the fourth inductor is an input end of the input bias network, the other end of the fourth inductor is connected with one end of the second resistor, the other end of the second resistor is connected with a positive polarity end of the direct current voltage source, and a negative polarity end of the direct current voltage source is grounded. Meanwhile, the input bias circuit further comprises three capacitors, and each capacitor is connected between the positive polarity end of the first direct-current voltage source and the ground in series.
Specifically, the input bias circuits connected to the carrier power transistor, the peak power transistor, and the gate of the driving power transistor have the same configuration except that the voltage VG of the first dc voltage source in the input bias circuit connected to the gate of the carrier power transistor is-4.8V, the voltage VG of the first dc voltage source in the input bias circuit connected to the gate of the carrier power transistor is-1.8V, and the voltage VG of the first dc voltage source in the input bias circuit connected to the gate of the driving power transistor is-1.7V.
By arranging the input bias circuit connected with the carrier power transistor, the peak power transistor and the grid electrode of the driving power transistor, stable direct-current voltage is provided for the grid electrode of the transistor, interference of a radio-frequency input signal to a direct-current power supply is prevented, and the stability of the whole circuit is improved.
Preferably, the power amplifier further comprises an output bias circuit connected to the drains of the carrier power transistor, the peak power transistor and the driving power transistor; the output bias network comprises a fifth inductor and a second direct current voltage source; one end of the fifth inductor is an input end of the output bias network, the other end of the fifth inductor is connected with a positive polarity end of the second direct-current voltage source, and a negative polarity end of the second direct-current voltage source is grounded. Meanwhile, the output bias network also comprises three capacitors, and each capacitor is connected between the positive polarity end of the second direct current voltage source and the ground in series.
Specifically, the output bias circuit connected to the drains of the carrier power transistor, the peak power transistor, and the driving power transistor has the same configuration, and the voltage VD of the second dc voltage source in the output bias circuit is 48V.
By arranging the output bias circuit connected with the drains of the carrier power transistor, the peak power transistor and the driving power transistor, stable direct-current voltage is provided for the drains of the transistors, interference of radio-frequency output signals to a direct-current power supply is prevented, and the stability of the whole circuit is improved.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. A compact Doherty power amplifier, comprising:
the driving power amplifying circuit is connected to the input end of the power divider;
the carrier power amplifying circuit is connected to one output end of the power divider and comprises a carrier output matching network;
and the peak power amplifying circuit is connected to the other output end of the power divider and comprises a peak output matching network and a pi-shaped microstrip compensation line.
2. The compact Doherty power amplifier of claim 1, wherein when a first power signal is input to a driving power amplifying circuit, the carrier output matching network matches a load impedance of a carrier power transistor to a combining point impedance, the pi-type microstrip compensation line matches a load impedance of a peak power transistor to infinity, and amplification of the first power signal is achieved by the carrier power amplifying circuit;
when a second power signal is input to the driving power amplification circuit, the carrier output matching network matches the load impedance of the carrier power transistor to 150 ohms, the peak output matching network matches the load impedance of the peak power transistor to 75 ohms, and the carrier power amplification circuit and the peak power amplification circuit jointly achieve amplification of the second power signal.
3. The compact Doherty power amplifier of claim 2 wherein the carrier power amplification circuit further comprises a carrier input matching network connected between one input of the power divider and a carrier power transistor;
the carrier input matching network comprises a first inductor, a first capacitor and a second capacitor; one end of the first inductor is connected with one end of the first capacitor and one end of the second capacitor at the same time, the other end of the first inductor is connected with a grid electrode of the carrier power transistor, the other end of the first capacitor is an input end of the carrier input matching network, and the other end of the second capacitor is grounded.
4. The compact Doherty power amplifier of claim 3 wherein the carrier output matching network is connected between the carrier power transistor and the combining point, and includes a first microstrip line, a third capacitor and a fourth capacitor, one end of the first microstrip line is connected to one end of the third capacitor, the other end of the first microstrip line is an output end of the carrier output matching network, the output end of the carrier output matching network is further connected to one end of the fourth capacitor, one end of the third capacitor is connected to the drain of the carrier power transistor, and the other end of the fourth capacitor is grounded.
5. The compact Doherty power amplifier of claim 4 wherein the carrier power amplification circuit further comprises a pi-type phase compensation network connected between one output of the power divider and the carrier input matching network;
the pi-type phase compensation network comprises a second inductor, a fifth capacitor and a sixth capacitor, and the fifth capacitor and the sixth capacitor are respectively connected to two ends of the second inductor; one end of the second inductor is an input end of the pi-type phase compensation network, and the other end of the second inductor is an output end of the pi-type phase compensation network.
6. The compact Doherty power amplifier of claim 1 wherein the peaking power amplifying circuit further comprises a peaking input matching network;
the peak value input matching network comprises a second microstrip line, a seventh capacitor and an eighth capacitor, one end of the second microstrip line is simultaneously connected with one end of the seventh capacitor and one end of the eighth capacitor, the other end of the seventh capacitor is an input end of the peak value input matching network, the other end of the eighth capacitor is grounded, and the other end of the second microstrip line is an output end of the peak value input matching network.
7. The compact Doherty power amplifier of claim 6 wherein the peak output matching network comprises a third microstrip line, a ninth capacitor and a tenth capacitor, the third microstrip line is connected to one end of the ninth capacitor and one end of the tenth capacitor, the other end of the ninth capacitor is an input end of the peak output matching network, and the other end of the tenth capacitor is grounded.
8. The compact Doherty power amplifier of claim 7 wherein the pi-type microstrip compensation line comprises a fourth microstrip line and an eleventh capacitor, and shares a tenth capacitor with the peak output matching network; the tenth capacitor and the eleventh capacitor are respectively connected to two ends of a fourth microstrip line, and the two ends of the fourth microstrip line are respectively an input end and an output end of the pi-shaped microstrip compensation line.
9. The compact Doherty power amplifier of claim 1 wherein the drive power amplification circuit comprises a drive input matching network, a drive power transistor and a drive output matching network;
the driving input matching network comprises a first resistor, a third inductor, a twelfth capacitor, a thirteenth capacitor and a fourteenth capacitor; the first resistor is connected with the twelfth capacitor in parallel, one end of the first resistor after the parallel connection is an output end of the driving input matching network, the other end of the first resistor after the parallel connection is connected with one end of the third inductor, the other end of the third inductor is simultaneously connected with one end of the thirteenth capacitor and one end of the fourteenth capacitor, the other end of the thirteenth capacitor is an input end of the driving input matching network, and the other end of the fourteenth capacitor is grounded;
the drive output matching network comprises a fifth microstrip line, a fifteenth capacitor and a sixteenth capacitor; one end of the fifth microstrip line is connected with one end of a fifteenth capacitor, the other end of the fifth microstrip line is an output end of the driving output matching network, the other end of the fifteenth capacitor is an input end of the driving output matching network, and the sixteenth capacitor is connected between the output end of the driving output matching network and the ground.
10. The compact Doherty power amplifier of claim 3 further comprising an input bias circuit connected at the gates of the carrier power transistor, the peak power transistor and the drive power transistor; the input bias network comprises a fourth inductor, a second resistor and a first direct-current voltage source; one end of the fourth inductor is an input end of the input bias network, the other end of the fourth inductor is connected with one end of the second resistor, the other end of the second resistor is connected with a positive polarity end of the direct current voltage source, and a negative polarity end of the direct current voltage source is grounded;
the output bias circuit is connected to the drains of the carrier power transistor, the peak power transistor and the driving power transistor; the output bias network comprises a fifth inductor and a second direct current voltage source; one end of the fifth inductor is an input end of the output bias network, the other end of the fifth inductor is connected with a positive polarity end of the second direct-current voltage source, and a negative polarity end of the second direct-current voltage source is grounded.
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| CN117294257A (en) * | 2023-08-18 | 2023-12-26 | 芯百特微电子(无锡)有限公司 | Doherty power amplifier |
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