CN114822387B - Pixel circuit and display panel - Google Patents

Abstract

The embodiment of the invention discloses a pixel circuit and a display panel. The pixel circuit includes: the data writing module is used for writing the data signals to the control end of the driving module; the data writing module comprises a first writing unit and a second writing unit, and the first writing unit and the second writing unit are connected in series in a data writing path; the connection point of the first writing unit and the second writing unit is a first node; the data clearing module is used for writing a reference voltage signal into the control end of the driving module and comprises a first clearing unit and a second clearing unit which are connected in series in a reference voltage signal writing channel; the connection point of the first clearing unit and the second clearing unit is a second node; and the first node and the second node are connected so that the potentials of the first node and the second node are equal. Compared with the prior art, the embodiment of the invention reduces the electric leakage of the pixel circuit and improves the performance of the pixel circuit.

Description

Pixel circuit and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit and a display panel.

Background

Along with the continuous development of display technology, the application range of the display panel is wider and wider, and the requirements of people on the display panel are also higher and higher. The pixel driving circuit in the display panel plays a very important role in driving the light emitting device to stably emit light. However, the performance of the existing pixel driving circuit is not ideal, and there is a problem of leakage, which can increase the power consumption of the display panel on one hand and cause poor display stability on the other hand.

Disclosure of Invention

The embodiment of the invention provides a pixel circuit and a display panel, which are used for reducing electric leakage and improving the performance of the pixel circuit.

In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:

a pixel circuit, comprising:

the driving module is used for responding to the data signal to generate driving current and driving the light emitting device to emit light;

the data writing module is used for writing data signals into the control end of the driving module; the data writing module comprises a first writing unit and a second writing unit, and the first writing unit and the second writing unit are connected in series in a signal path for writing the data signals; the connection point of the first writing unit and the second writing unit is a first node;

The data clearing module is used for writing a reference voltage signal into a control end of the driving module, and comprises a first clearing unit and a second clearing unit which are connected in series in a signal path in which the reference voltage signal is written; the connection point of the first clearing unit and the second clearing unit is a second node; and the first node and the second node are connected so that the potentials of the first node and the second node are equal.

Optionally, the first writing unit includes a control end, a first end and a second end; the second writing unit comprises a control end, a first end and a second end;

the control end of the first writing unit and the control end of the second writing unit are both connected with scanning signals, the first end of the first writing unit is connected with the data signals, the second end of the first writing unit is connected with the first end of the second writing unit, and the second end of the second writing unit is connected with the control end of the driving module;

the first cleaning unit comprises a control end, a first end and a second end; the second cleaning unit comprises a control end, a first end and a second end;

The control end of the first clearing unit and the control end of the second clearing unit are connected with clearing signals, the first end of the first clearing unit is connected with a reference voltage signal, the second end of the first clearing unit is connected with the first end of the second clearing unit, and the second end of the second clearing unit is connected with the control end of the driving module.

Optionally, the first writing unit includes a first transistor, and the second writing unit includes a second transistor; the grid electrode of the first transistor and the grid electrode of the second transistor are both connected with the scanning signal, the first electrode of the first transistor is connected with the data signal, the second electrode of the first transistor is connected with the first electrode of the second transistor, and the second electrode of the second transistor is connected with the control end of the driving module;

the first clearing unit comprises a third transistor, and the second clearing unit comprises a fourth transistor; the gate of the third transistor and the gate of the fourth transistor are both connected with the clearing signal, the first electrode of the third transistor is connected with the reference voltage signal, the second electrode of the third transistor is connected with the first electrode of the fourth transistor, and the second electrode of the fourth transistor is connected with the control end of the driving module.

Optionally, the driving module includes a driving transistor, and a gate of the driving transistor is used as a control end of the driving module; the grid electrode of the driving transistor is directly connected with the data output end of the data writing module;

the reference voltage signal and the data signal are opposite in level; channel types of the first transistor and the second transistor are opposite to channel types of the driving transistor; and channel types of the third transistor and the fourth transistor are the same as channel types of the driving transistor;

optionally, the driving transistor is a P-type transistor; the first transistor and the second transistor are both N-type transistors; the third transistor and the fourth transistor are P-type transistors;

or the driving transistor is an N-type transistor; the first transistor and the second transistor are both P-type transistors; the third transistor and the fourth transistor are both N-type transistors.

The driving module comprises a driving transistor, and a grid electrode of the driving transistor is used as a control end of the driving module; the grid electrode of the driving transistor is directly connected with the data output end of the data writing module;

The reference voltage signal and the data signal have the same level; channel types of the first transistor, the second transistor, the third transistor and the fourth transistor are opposite to channel types of the driving transistor;

optionally, the driving transistor is a P-type transistor; the first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors;

or the driving transistor is an N-type transistor; the first transistor, the second transistor, the third transistor and the fourth transistor are all P-type transistors.

Optionally, the driving module includes a driving transistor, and a gate of the driving transistor is used as a control end of the driving module; the grid electrode of the driving transistor is connected with the data output end of the data writing module through a latch;

the reference voltage signal and the data signal are opposite in level; the channel types of the first transistor and the second transistor are the same as the channel type of the driving transistor; and channel types of the third transistor and the fourth transistor are opposite to channel types of the driving transistor;

Optionally, the driving transistor is a P-type transistor; the first transistor and the second transistor are both P-type transistors; the third transistor and the fourth transistor are both N-type transistors;

or the driving transistor is an N-type transistor; the first transistor and the second transistor are both N-type transistors; the third transistor and the fourth transistor are P-type transistors.

Optionally, the driving module includes a driving transistor, and a gate of the driving transistor is used as a control end of the driving module; the channel types of the driving transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor are all the same.

Optionally, the pixel circuit further includes: a first memory module and a second memory module; the first storage module is connected with the control end of the driving module and is used for storing the potential of the control end of the driving module; the second storage module is connected with the first node and is used for storing the potential of the first node;

optionally, the first storage module includes a first capacitor, a first end of the first capacitor is connected to a first fixed potential, and a second end of the first capacitor is connected to a control end of the driving module;

Alternatively, the first memory module includes a latch connected in series between the data output terminal of the data writing module and the control terminal of the driving module;

optionally, the first storage module includes a first capacitor, and the first power signal or the second power signal is multiplexed to the first fixed potential; the first power supply signal and the second power supply signal are signals for generating a driving current;

optionally, the second storage module includes a second capacitor, a first end of the second capacitor is connected to a second fixed potential, and a second end of the second capacitor is connected to the first node;

optionally, the reference voltage signal, the first power supply signal or the second power supply signal is multiplexed to the second fixed potential; the first power supply signal and the second power supply signal are signals for generating a driving current.

Optionally, the pixel circuit is a digital driving pixel circuit, and the data signal is a digital data signal; the driving module is used for generating digital driving current in response to the digital data signal in a subframe and is used for being turned off in response to the reference voltage signal;

Or the pixel circuit is an analog driving pixel circuit, and the data signal is an analog data signal; the driving module is used for initializing in response to the reference voltage signal in one frame and is used for generating an analog driving current in response to the analog data signal.

Correspondingly, the invention also provides a display panel, which comprises: the pixel circuit according to any embodiment of the invention.

The pixel circuit setting data writing module provided by the embodiment of the invention comprises a first writing unit and a second writing unit, wherein the first writing unit and the second writing unit are connected in series in a signal path for writing data signals. And the data clearing module comprises a first clearing unit and a second clearing unit, wherein the first clearing unit and the second clearing unit are connected in series in a signal path for writing the reference voltage signal. The connection point of the first writing unit and the second writing unit is a first node, the connection point of the first clearing unit and the second clearing unit is a second node, and the first node and the second node are connected with equal potential. By the arrangement, when the first writing unit and the second writing unit are conducted, the electric potentials of the first node, the second node and the control end of the driving module are kept equal, and electric leakage of the electric potential of the control end of the driving module through the first clearing unit or the second clearing unit is prevented; and when the first clearing unit and the second clearing unit are conducted, the electric potentials of the first node, the second node and the control end of the driving module are kept equal, and electric leakage of the electric potential of the control end of the driving module through the first writing unit or the second writing unit is prevented, so that the power consumption of the pixel circuit is reduced, stable light emission of the light emitting device is facilitated, the performance of the pixel circuit is improved, and the low-frequency driving of the pixel circuit is facilitated.

Drawings

Fig. 1 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a timing diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 5 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 6 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 7 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 8 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 9 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 10 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention;

fig. 11 is a timing diagram of another pixel circuit according to an embodiment of the invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

The embodiment of the invention provides a pixel circuit. Fig. 1 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 1, the pixel circuit includes: the driving module 100, the data writing module 200 and the data erasing module 300.

The driving module 100 is configured to generate a driving current in response to the data signal Vdata, and drive the light emitting device LED to emit light. The data writing module 200 includes a data input terminal 201 and a data output terminal 202, the data input terminal 201 is connected to the data signal Vdata, the data output terminal 202 is connected to the control terminal 103 of the driving module 100, and a current path between the data input terminal 201 and the data output terminal 202 of the data writing module 200 forms a signal path L1 in which the data signal Vdata is written. The data writing module 200 includes a first writing unit 210 and a second writing unit 220, where the first writing unit 210 and the second writing unit 220 are connected in series in a signal path L1 where the data signal Vdata is written, that is, the first writing unit 210 and the second writing unit 220 are connected in series between the data input terminal 201 and the data output terminal 202. The connection point of the first writing unit 210 and the second writing unit 220 is the first node a.

The data clearing module 300 includes a clearing input 301 and a clearing output 302, the clearing input 301 is connected to a reference voltage signal (for example, a first reference voltage signal Vref 1), the clearing output 302 is connected to a control terminal of the driving module 100, and a current path between the clearing input 301 and the clearing output 302 of the data clearing module 300 forms a signal path L2 to which the reference voltage signal is written. The data erasing module 300 includes a first erasing unit 310 and a second erasing unit 320, where the first erasing unit 310 and the second erasing unit 320 are connected in series in a signal path L2 where the reference voltage signal is written, i.e., the first erasing unit 310 and the second erasing unit 320 are connected in series between the erasing input terminal 301 and the erasing output terminal 302. The connection point of the first clearing unit 310 and the second clearing unit 320 is the second node B; and the first node a and the second node B are connected so that the potentials of the first node a and the second node B are equal.

The data output terminal 202 (defined as a third node C) of the data writing module 200 is connected to the control terminal 103 of the driving module 100, and is configured to write a data signal Vdata into the third node C, where the data signal Vdata is used to drive the driving module 100 to generate a driving current; the clearing output end 302 of the data clearing module 300 is also connected to the third node C, and is configured to write the first reference voltage signal Vref1 into the third node C, where the first reference voltage signal Vref1 is used to clear the original signal of the third node C, so that the potential of the third node C meets the driving requirement of the next stage. The first reference voltage signal Vref1 and the data signal Vdata may have the same potential or opposite potentials, and may be set for a specific circuit.

Taking the driving module 100 as an example, the driving module 100 includes a driving transistor, which is generally operated in a saturation region when generating a driving current, the driving module 100 generates the driving current in response to the data signal VdataWherein W is the channel width, L is the channel length, mu _eff For electron mobility, C _ox Vth is the threshold voltage of the drive transistor, which is the channel capacitance per unit area.Vgs is the gate-source voltage difference of the driving transistor, e.g., the gate of the driving transistor is used as the control terminal 103 (i.e., the third node C) of the driving module 100, the source of the driving transistor is used as the first terminal 101 of the driving module 100, and the drain of the driving transistor is used as the second terminal 102 of the driving module 100. At this time, the gate of the driving transistor is the data signal Vdata, the source is the first power signal VDD, and the driving current +. >Since the first power supply signal VDD, the threshold voltage, the channel parameter, etc. can be regarded as constant values, the magnitude and/or duration of the signal written to the gate of the driving transistor determines the magnitude of the driving current and thus the light emitting brightness of the light emitting device LED; accordingly, the stability of the gate voltage of the driving transistor determines the stability of the light emission of the light emitting device LED.

However, during operation of the pixel circuit, there is leakage due to transistor leakage or the like, for example, a transistor connected to the gate (i.e., the third node C) of the driving transistor, on the one hand, so that the power consumption of the pixel circuit increases; on the other hand, the grid voltage of the driving transistor fluctuates, so that the light emitting device LED emits light unstably, and particularly, the requirement on long-time stable light emission of the light emitting device LED is higher when the light emitting device LED is driven at low frequency.

The embodiment of the invention comprises a data writing module 200 connected with a third node C, wherein the data writing module comprises two writing units (a first writing unit 210 and a second writing unit 220 respectively) connected in series; and the data clearing module 300 connected with the third node C includes two clearing units (the first clearing unit 310 and the second clearing unit 320 respectively) connected in series, so that the electric leakage of the third node C can be reduced, thereby being beneficial to reducing the power consumption of the pixel circuit, being beneficial to stable light emission of the light emitting device LED, and improving the performance of the pixel circuit. The following is a specific description:

Fig. 2 is a timing diagram of a pixel circuit according to an embodiment of the invention. Referring to fig. 1 and 2, the first reference voltage signal Vref1 and the data signal Vdata are used to clear the data signal Vdata of the third node C, so that the driving module 100 is switched to an operating state in which no driving current is generated. The conduction states of the first writing unit 210 and the second writing unit 220 are controlled by the Scan signal Scan, and when the Scan signal Scan is at a high level, the first writing unit 210 and the second writing unit 220 are turned on; when the Scan signal Scan is at a low level, the first and second writing units 210 and 220 are turned off; the on state of the first and second Clear units 310 and 320 is controlled by the Clear signal Clear, and when the Clear signal Clear is low, the first and second Clear units 310 and 320 are turned on; when the Clear signal Clear is at a high level, the first Clear unit 310 and the second Clear unit 320 are turned off.

The driving timing of the pixel circuit includes a stage T1, a stage T2, and a stage T3. In the stage T1, the Clear signal Clear is high, and the first Clear unit 310 and the second Clear unit 320 are turned off; the Scan signal Scan is at a high level, the first writing unit 210 and the second writing unit 220 are turned on, the data signal Vdata is transmitted to the third node C, and the driving module 100 generates a driving current in response to the data signal Vdata to drive the light emitting device LED to emit light. At this time, the potential of the third node C may leak through the second and first clearing units 320 and 310, however, the embodiment of the present invention cuts off the leakage path. Specifically, since the second writing unit 220 is in the on state, the potentials of the first node a and the third node C are equal to each other, which is equal to the potential of the data signal Vdata; since the first node a and the second node B are connected and have equal potentials, the second node B and the third node C have equal potentials, which is equivalent to the equal potentials at both ends of the second clearing unit 320, the second clearing unit 320 cannot be turned on, the flowing current is 0, and the potential of the third node C cannot leak through the second clearing unit 320. And, since the first and second clearing units 310 and 320 are connected in series, the current of the first clearing unit 310 is limited by the second clearing unit 320, and the potential of the third node C does not leak through the first clearing unit 310.

In the stage T3, the Scan signal Scan is low, and the first and second write units 210 and 220 are turned off; the Clear signal Clear is at a low level, the first Clear unit 310 and the second Clear unit 320 are turned on, the first reference voltage signal Vref1 is transmitted to the third node C, and the driving module 100 is turned off in response to the first reference voltage signal Vref1 to stop generating the driving current. At this time, the potential of the third node C may leak through the second writing unit 220 and the first writing unit 210. As such, the embodiment of the present invention can cut off the leakage path, specifically, since the second clearing unit 320 is in the on state, the potential of the second node B and the third node C are equal, which is equal to the potential of the first reference voltage signal Vref 1; since the first node a and the second node B are connected to each other and have the same potential, the potentials of the first node a and the third node C are also equal, which corresponds to the equal potential at both ends of the second writing unit 220, the second writing unit 220 cannot be turned on, the current flowing through the second writing unit 220 is 0, and the potential of the third node C cannot leak through the second writing unit 220. And, since the first writing unit 210 and the second writing unit 220 are connected in series, the current of the first writing unit 210 is limited by the second writing unit 220, and the potential of the third node C does not leak through the first writing unit 210.

From the above analysis, the embodiment of the present invention can effectively reduce the leakage of the third node C, thereby being beneficial to reducing the power consumption of the pixel circuit, being beneficial to stable light emission of the light emitting device LED, improving the performance of the pixel circuit, and being beneficial to low frequency driving of the pixel circuit.

With continued reference to fig. 1, on the basis of the above embodiments, optionally, the connection relationship between the first writing unit 210 and the second writing unit 220 is as follows: the first writing unit 210 includes a control terminal 213, a first terminal 211, and a second terminal 212; the second writing unit 220 includes a control terminal 223, a first terminal 221, and a second terminal 222. The control end 213 of the first writing unit 210 and the control end 223 of the second writing unit 220 are both connected to the Scan signal Scan, the first end 211 of the first writing unit 210 is connected to the data signal Vdata, the second end 212 of the first writing unit 210 is connected to the first end 221 of the second writing unit 220, and the second end 222 of the second writing unit 220 is connected to the control end 103 of the driving module 100. In this way, the first writing unit 210 and the second writing unit 220 form a series connection relationship, and the first writing unit 210 and the second writing unit 220 are connected between the data input terminal 201 and the data output terminal 202.

With continued reference to fig. 1, the first purge unit 310 may optionally include a control end 313, a first end 311, and a second end 312, as per the various embodiments described above; the second purge unit 320 includes a control end 323, a first end 321, and a second end 322. The control end 313 of the first clearing unit 310 and the control end 323 of the second clearing unit 320 are both connected to a clearing signal Clear, the first end 311 of the first clearing unit 310 is connected to a first reference voltage signal Vref1, the second end 312 of the first clearing unit 310 is connected to the first end 321 of the second clearing unit 320, and the second end of the second clearing unit 320 is connected to the control end of the driving module 100. Thus, the first and second clear units 310 and 320 are in a series connection, and the first and second clear units 310 and 320 are connected between the clear input 301 and the clear output 302.

With continued reference to fig. 1, the drive module 100 optionally includes a control end 103, a first end 101, and a second end 102, as per the various embodiments described above. The control end 103 of the driving module 100 is connected to the third node C, the first end 101 of the driving module 100 is connected to the first power signal VDD, the second end 102 of the driving module 100 is connected to the anode of the light emitting device LED, and the cathode of the light emitting device LED is connected to the second power signal VSS. The first power signal VDD and the second power signal VSS are signals for generating a driving current, that is, the driving current generated by the driving module 100 flows between the first power signal VDD and the second power signal VSS.

With continued reference to fig. 1, the pixel circuit optionally further includes a first memory module 400, as per the embodiments described above. The first storage module 400 is connected to the control end 103 of the driving module 100, and is used for storing the potential of the control end 103 of the driving module 100 to maintain the potential stability of the control end 103 of the driving module 100, so as to facilitate the stable light emission of the light emitting device LED. Referring to fig. 1 and 2, illustratively, in phase T2, the Scan signal Scan is low, and the first and second write units 210 and 220 are turned off; the Clear signal Clear is high and the first Clear unit 310 and the second Clear unit 320 are turned off. Since the first memory module 400 stores the data signal Vdata written into the control terminal 103 of the driving module 100 in the stage T1, the potential of the control terminal 103 of the driving module 100 is maintained in the stage T2, so that the driving module 100 generates a stable driving current in response to the data signal Vdata.

With continued reference to fig. 1, optionally, the first memory module 400 includes a first terminal 401 and a second terminal 402, and the first terminal 401 of the first memory module 400 is connected to a first fixed potential, which is, for example, the first power supply signal VDD. The second end 402 of the memory module is connected to the control end 103 of the drive module 100. The first memory module 400 can maintain the potential of the second terminal 402 stable according to the first fixed potential of the first terminal 401. In other embodiments, the first fixed potential may also be set as the second power supply signal VSS, which may specifically be determined according to the setting manner of the driving module 100, or according to the connection relationship between the driving module 100 and the light emitting device LED.

On the basis of the above embodiments, the pixel circuit provided by the embodiments of the present invention may be a digital driving pixel circuit or an analog driving pixel circuit. If the pixel circuit can be a digital driving pixel circuit, the data signal Vdata is a digital data signal; the driving module 100 is used for generating a digital driving current in response to the digital data signal Vdata within a subframe, and is used for being turned off in response to the first reference voltage signal Vref 1. In general, the digital data signal has a constant voltage, and the digital driving display gray scale is essentially a process of varying the duration of the digital data signal and the duration of the first reference voltage signal Vref1, i.e. a process of varying the duration of the light emitting device LED. The frame comprises a plurality of subframes, the bright state time of the LEDs in the subframes is combined to form total light-emitting time, and the longer the bright state time is, the shorter the dark state time is, and the higher the light-emitting brightness of the LEDs is; conversely, the shorter the bright state time, the longer the dark state time, and the lower the light emission luminance of the light emitting device LED. Alternatively, in other embodiments, the voltage level of the digital data signal may be set to vary in different subframes or different frames, so as to increase the flexibility of driving.

In one subframe, when the digital data signal is written into the third node C, the moment when the light emitting device LED starts to emit light is indicated; when the first reference voltage signal Vref1 is written to the third node C, it indicates the timing at which the light emitting device LED stops emitting light. Referring to fig. 2, in the digital driving pixel circuit, the driving timing is the driving timing within one subframe, and the start time of the phase T1 is the time when the light emitting device LED starts to emit light; the start time of the stage T3 is the time when the light emitting device LED stops emitting light. The stage T1 and the stage T2 are the time for which the light emitting device LED continuously emits light, wherein the first memory module 400 maintains the light emitting device LED to stably emit light in the stage T2; stage T3 is the off time of the light emitting device LED. Thus, the Scan signal Scan and the Clear signal Clear realize the combination of the light emission time of a plurality of subframes, thereby realizing different light emission luminance.

Alternatively, for a digitally driven pixel circuit, the light emission time of the light emitting device LED may be controlled by the action time of the Scan signal Scan and the Clear signal Clear. The Scan signal Scan and the Clear signal Clear may be driven by an array substrate row driving circuit (Gate Driver on Array, GOA), for example, a shift register. Therefore, the embodiment of the invention is beneficial to realizing the digital driving setting mode by the GOA.

If the pixel circuit is an analog driving pixel circuit, the data signal Vdata is an analog data signal, and the driving module 100 is configured to initialize in response to the first reference voltage signal Vref1 within one frame and generate an analog driving current in response to the analog data signal Vdata. Unlike a digital driving pixel circuit, an analog driving pixel circuit controls the light emission luminance of a light emitting device LED by the magnitude of a driving current, and thus, in general, the analog driving pixel circuit does not need to divide one frame into a plurality of subframes. Referring to fig. 2, in the analog driving pixel circuit, the driving timing is one frame driving timing, and in the stage T1, the data signal Vdata is written into the third node C, and the light emitting device LED emits light; in the stage T2, the data signal Vdata is not written into the third node C any more, and the first memory module 400 stores the data signal Vdata written into the third node C in the stage T1 and maintains the data signal Vdata, so that the driving module 100 generates a stable driving current in response to the data signal Vdata; in the stage T3, the Clear signal Clear is written into the third node C, and the third node C is reset, so as to prepare for driving the light emitting device LED to emit light for the next frame.

Note that fig. 2 shows only one driving timing of the analog driving pixel circuit, and is not a limitation of the present invention. In other embodiments, the step of setting the stage T3 may be performed before the stage T1, that is, before the data signal Vdata is written into the third node C, and in actual applications, the stage T3 may be set as required.

Fig. 3 is a schematic circuit diagram of another pixel circuit according to an embodiment of the invention. Referring to fig. 3, the pixel circuit may further include a second memory module 500, as an option, based on the above embodiments. The second memory module 500 is connected to the first node a for storing the potential of the first node a. Wherein, since the first node A and the second node B are connected, storing the potential of the first node A is equivalent to storing the potentials of the first node A and the second node B. Thus, when the first writing unit 210, the second writing unit 220, the first erasing unit 310 and the second erasing unit 320 are all turned off (e.g., stage T2 in fig. 2), the potential of the third node C is maintained unchanged under the action of the first memory module 400, and the potentials of the first node a and the second node B are maintained unchanged under the action of the second memory module 500, so that the potentials of the first node a, the second node B and the third node C can be maintained equal, not only the leakage of the second writing unit 220, but also the leakage of the second erasing unit 320 can be prevented. Therefore, the second memory module 500 is provided in the embodiment of the invention, so that the anti-leakage performance of the pixel circuit is further improved.

With continued reference to FIG. 3, optionally, the second memory module 500 includes a first end 501 and a second end 502. The first terminal 501 of the second memory module 500 is connected to a second fixed potential, which is, for example, a second reference voltage signal Vref2. The second end 502 of the second memory module 500 is connected to the first node a. The second memory module 500 is capable of maintaining the potential of the second terminal 502 stable according to the second fixed potential of the first terminal 501. For example, when the second terminal 502 of the second memory module 500 writes a high potential, the second memory module 500 can store the high potential and keep the voltage difference between the first terminal 501 and the second terminal 502 of the second memory module 500 unchanged. When the first node a has no other signal written, the potential of the first node a is also kept unchanged under the action of the second memory module 500, because the potential of the second reference voltage signal Vref2 is kept unchanged.

Alternatively, the first reference voltage signal Vref1, the first power supply signal VDD or the second power supply signal VSS is multiplexed to the second fixed potential. This arrangement is advantageous in reducing the number of signal lines. Those skilled in the art will appreciate that the multiplexing of signals can reduce the number of signal lines, and the operation modes that can be implemented can also be reduced, and can be set according to the needs in practical applications.

Fig. 4 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention. Referring to fig. 4, the first writing unit 210 may optionally include a first transistor M1, and the second writing unit 220 may include a second transistor M2, on the basis of the above embodiments; the gate of the first transistor M1 and the gate of the second transistor M2 are both connected to the Scan signal Scan, the first pole of the first transistor M1 is connected to the data signal Vdata, the second pole of the first transistor M1 is connected to the first pole of the second transistor M2, and the second pole of the second transistor M2 is connected to the control end of the driving module 100. So arranged, corresponds to the first transistor M1 and the second transistor M2 being connected in series to realize the function of data writing; and the circuit structure is simple and easy to realize. Wherein the connection point of the second pole of the first transistor M1 and the first pole of the second transistor M2 is the first node a.

With continued reference to fig. 4, on the basis of the above embodiments, optionally, the first erasing unit 310 includes a third transistor M3, and the second erasing unit 320 includes a fourth transistor M4; the gate of the third transistor M3 and the gate of the fourth transistor M4 are both connected to the Clear signal Clear, the first pole of the third transistor M3 is connected to the first reference voltage signal Vref1, the second pole of the third transistor M3 is connected to the first pole of the fourth transistor M4, and the second pole of the fourth transistor M4 is connected to the control terminal of the driving module 100. The arrangement corresponds to the series connection of the third transistor M3 and the fourth transistor M4 so as to realize the writing function of the first reference voltage signal Vref1, and the arrangement has simple circuit structure and is easy to realize. Wherein the connection point of the second pole of the third transistor M3 and the first pole of the fourth transistor M4 is the second node B. The first node A and the second node B are connected, and when the first transistor M1 and the second transistor M2 are conducted, the first node A, the second node B and the third node C can be equipotential, so that the fourth transistor M4 is prevented from leaking; when the third transistor M3 and the fourth transistor M4 are turned on, the first node a, the second node B, and the third node C are made to be equipotential, thereby preventing the second transistor M2 from leaking.

With continued reference to fig. 4, in the foregoing embodiments, optionally, the first memory module 400 includes a first capacitor C1, a first end of the first capacitor C1 is connected to a first fixed potential (e.g., the first power signal VDD), and a second end of the first capacitor C1 is connected to the third node C.

With continued reference to fig. 4, the second memory module 500 may optionally include a second capacitor C2, where a first end of the second capacitor C2 is connected to a second fixed potential (e.g., the second reference voltage signal Vref 2), and a second end of the second capacitor C2 is connected to the first node a.

With continued reference to fig. 4, the driving module 100 may optionally include a driving transistor M5, where, illustratively, a gate of the driving transistor M5 is connected to the third node C, a first pole of the driving transistor M5 is connected to the first power signal VDD, a second pole of the driving transistor M5 is connected to an anode of the light emitting device LED, and a cathode of the light emitting device LED is connected to the second power signal VSS.

On the basis of the above embodiments, the types of the transistors are further limited in the embodiments of the present invention, and the following description is made in detail.

With continued reference to fig. 4, the driving transistor M5, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may be formed of the same channel type, for example, P-type transistors, based on the above embodiments. The arrangement is beneficial to forming all transistors in the same process, thereby being beneficial to simplifying the process flow and reducing the manufacturing cost.

Fig. 5 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention. Referring to fig. 5, the gate of the driving transistor M5 is directly connected to the data output terminal of the data writing module 200, i.e., the gate of the driving transistor M5 and the third node C are the same node, the data signal Vdata is directly used as the control signal of the driving transistor M5, and the first reference voltage signal Vref1 is directly used as the control signal of the driving transistor M5, and the level of the first reference voltage signal Vref1 is opposite to that of the data signal Vdata. The channel types of the first transistor M1 and the second transistor M2 are opposite to the channel type of the driving transistor M5; and channel types of the third transistor M3 and the fourth transistor M4 are the same as those of the driving transistor M5. The arrangement is beneficial to writing the data signal Vdata and the first reference voltage signal Vref1 into the grid electrode of the driving transistor M5, so that the stability of the pixel circuit is improved; on the other hand, the logic power consumption is reduced.

Specifically, with continued reference to fig. 5, the driving transistor M5 is a P-type transistor; the first transistor M1 and the second transistor M2 are both N-type transistors; the third transistor M3 and the fourth transistor M4 are P-type transistors. Since the driving transistor M5 is of a P-channel type, the data signal Vdata is low, and the first reference voltage signal Vref1 is high. In the embodiment of the invention, the first transistor M1 and the second transistor M2 are set to be N-channel, which is beneficial for the first transistor M1 and the second transistor M2 to transmit the data signal Vdata. Specifically, when the first transistor M1 and the second transistor M2 need to be controlled to be turned on, the Scan signal Scan is at a high level, the high level of the gates of the first transistor M1 and the second transistor M2 and the low level of the data signal Vdata form a voltage difference larger than a threshold value, the first transistor M1 and the second transistor M2 are controlled to be turned on, and the high level of the Scan signal Scan does not need to be set higher, so that the logic power consumption of the pixel circuit is reduced, and meanwhile, the data signal Vdata can be written into the gate of the driving transistor M5 better. In contrast, if the first transistor M1 and the second transistor M2 are P-channel, when the first transistor M1 and the second transistor M2 need to be controlled to be turned on, the Scan signal Scan is at a low level, and the low level needs to be lower than the low level of the data signal Vdata, and the power consumption of the pixel circuit is high due to the low level voltage of the Scan signal Scan. Similarly, setting the third transistor M3 and the fourth transistor M4 to P-channel type is advantageous for transmitting the first reference voltage signal Vref1 and reducing logic power consumption.

Fig. 6 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention. Referring to fig. 6, unlike in fig. 5, the driving transistor M5 is an N-type transistor, and accordingly, the first transistor M1 and the second transistor M2 are P-type transistors, and the third transistor M3 and the fourth transistor M4 are N-type transistors. The arrangement is beneficial to transmitting the data signal Vdata and the first reference voltage signal Vref1 and reducing the logic power consumption of the pixel circuit, and the specific principle is similar to that of the above embodiment and will not be repeated.

In one embodiment of the present invention, the first reference voltage signal Vref1 is optionally the same level as the data signal Vdata. The channel types of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are opposite to those of the driving transistor M5. The arrangement is beneficial to writing the data signal Vdata and the first reference voltage signal Vref1 into the grid electrode of the driving transistor M5, so that the stability of the pixel circuit is improved; on the other hand, the logic power consumption is reduced, and the specific principle is similar to that of the above embodiment and will not be repeated.

It should be noted that, for the digitally driven pixel circuit, there are various arrangements of the first memory module 400, and fig. 1, 3-6 exemplarily show one arrangement of the first memory module 400. In other embodiments, the first memory module 400 may be configured in other forms. For example, fig. 7 is a schematic circuit diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 7, the first memory module 400 may optionally include latches connected in series between the data output terminal 202 (third node C) of the data writing module 200 and the control terminal (fourth node D) of the driving module 100. The latch has a similar storage function to the capacitor, and can maintain the constant potential of the control terminal of the driving module 100. Unlike the capacitance, the first and second ends of the latch are opposite in potential, i.e., the third and fourth nodes C and D are opposite in potential. Thus, when the data signal Vdata is low, the potential transmitted to the third node C is still low, but the potential transmitted to the fourth node D becomes high; in contrast, when the data signal Vdata is at a high level, the potential transmitted to the third node C is still at a high level, but the potential transmitted to the fourth node D becomes at a low level. Likewise, when the first reference voltage signal Vref1 is at a high level, the potential transmitted to the third node C is still at a high level, but the potential transmitted to the fourth node D becomes at a low level; on the contrary, when the first reference voltage signal Vref1 is low, the potential transmitted to the third node C is still low, but the potential transmitted to the fourth node D is high.

Fig. 8 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention. Referring to fig. 8, in one embodiment of the present invention, optionally, for the digital pixel driving circuit, the first reference voltage signal Vref1 is opposite to the level of the data signal Vdata. Meanwhile, for a digital pixel driving circuit employing a latch as the first memory module 400, channel types of the first transistor M1 and the second transistor M2 are the same as those of the driving transistor M5; and the channel types of the third transistor M3 and the fourth transistor M4 are opposite to those of the driving transistor M5. The arrangement is beneficial to writing the data signal Vdata and the first reference voltage signal Vref1 into the grid electrode of the driving transistor M5, so that the stability of the pixel circuit is improved; on the other hand, the logic power consumption is reduced.

Specifically, with continued reference to fig. 8, the driving transistor M5 is a P-type transistor; the first transistor M1 and the second transistor M2 are P-type transistors; the third transistor M3 and the fourth transistor M4 are both N-type transistors. Since the driving transistor M5 is of a P-channel type, the data signal Vdata is high, and the first reference voltage signal Vref1 is low. In the embodiment of the invention, the first transistor M1 and the second transistor M2 are P-channel, which is beneficial for the first transistor M1 and the second transistor M2 to transmit the data signal Vdata. Specifically, when the first transistor M1 and the second transistor M2 need to be controlled to be turned on, the Scan signal Scan is at a low level, the low level of the gates of the first transistor M1 and the second transistor M2 and the high level of the data signal Vdata form a voltage difference larger than a threshold value, the first transistor M1 and the second transistor M2 are controlled to be turned on, and the low level of the Scan signal Scan is not required to be set lower, so that the logic power consumption of the pixel circuit is reduced, and the data signal Vdata can be written into the gate of the driving transistor M5 better. In contrast, if the first transistor M1 and the second transistor M2 are set to be N-channel, when the first transistor M1 and the second transistor M2 need to be controlled to be turned on, the Scan signal Scan is at a high level, and the high level needs to be higher than the high level of the data signal Vdata, and the power consumption of the pixel circuit is higher due to the excessively high voltage of the high level of the Scan signal Scan. Similarly, setting the third transistor M3 and the fourth transistor M4 to N-channel type is advantageous for transmitting the first reference voltage signal Vref1 and reducing logic power consumption.

Fig. 9 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention. Referring to fig. 9, unlike in fig. 8, the driving transistor M5 is an N-type transistor, and accordingly, the first transistor M1 and the second transistor M2 are both N-type transistors, and the third transistor M3 and the fourth transistor M4 are both P-type transistors. The arrangement is beneficial to transmitting the data signal Vdata and the first reference voltage signal Vref1 and reducing the logic power consumption of the pixel circuit, and the specific principle is similar to that of the above embodiment and will not be repeated.

With continued reference to fig. 8 and 9, the latch may optionally include a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, based on the above embodiments; the first pole of the sixth transistor M6 and the first pole of the seventh transistor M7 are shorted and then serve as the first power supply terminal 403 of the memory module, the gate of the sixth transistor M6, the second pole of the seventh transistor M7, the gate of the eighth transistor M8 and the first pole of the ninth transistor M9 are shorted and then serve as the first terminal 401 of the memory module, the gate of the sixth transistor M6, the gate of the seventh transistor M7, the first pole of the eighth transistor M8 and the gate of the ninth transistor M9 are shorted and then serve as the second terminal 402 of the memory module, and the second pole of the eighth transistor M8 and the second pole of the ninth transistor M9 are shorted and then serve as the second power supply terminal 404 of the memory module.

Among them, the channel types of the sixth transistor M6 and the eighth transistor M8 are different, and the channel types of the seventh transistor M7 and the ninth transistor M9 are different. The sixth transistor M6 and the eighth transistor M8 constitute the first inverter 410, and similarly, the seventh transistor M7 and the ninth transistor M9 constitute the second inverter 420. The first inverter 410 and the second inverter 420 form an anti-parallel connection relationship, so as to form a memory module, and the first end 401 and the second end 402 of the memory module have opposite potentials.

In the above embodiments, the pixel circuits shown in fig. 4 to 6, 8 and 9 do not have the threshold voltage compensation function of the driving transistor M5, and are not limited to the present invention. In other embodiments, the pixel circuit may be further configured to have a threshold voltage compensation function. For example, fig. 10 is a schematic circuit diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 10, in an embodiment, the data writing module 200 optionally includes a first transistor M1, a second transistor M2, and a tenth transistor M10, the gate of the tenth transistor M10, the gates of the first transistor M1, and the gate of the second transistor M2 are connected to the Scan signal Scan, the first transistor M1 and the second transistor M2 are connected in series between the second pole and the gate of the driving transistor M5, the first pole of the tenth transistor M10 is connected to the data signal Vdata, and the second pole of the tenth transistor M10 is connected to the first pole of the driving transistor M5. The pixel circuit further includes a light emission control module 600, the light emission control module 600 including an eleventh transistor M11 and a twelfth transistor M12, the gate of the eleventh transistor M11 and the gate of the twelfth transistor M12 being connected in series between the first power supply signal VDD and the first pole of the driving transistor M5, the twelfth transistor M12 being connected in series between the second terminal of the driving transistor M5 and the anode of the light emitting device LED. The connection relationship between other modules is the same as that of the above embodiments, and will not be described here again.

Fig. 11 is a timing diagram of another pixel circuit according to an embodiment of the invention. Referring to fig. 10 and 11, illustratively, each transistor in fig. 10 is a P-type transistor, and the data writing module 200 is turned on when the Scan signal Scan is at a low level; when Clear signal Clear is low, data Clear module 300 turns on. The data signal Vdata and the first reference voltage signal Vref1 are both low. The driving timing of the pixel circuit includes a stage T4, a stage T5, and a stage T6.

In the stage T4, also called an initialization stage, the Clear signal Clear is low, and the Scan signal Scan and the emission control signal EM are high. The Clear signal Clear controls the third transistor M3 and the fourth transistor M4 to be turned on, transmits the first reference voltage signal Vref1 to the third node C, initializes the gate of the driving transistor M5, and ensures that the driving transistor M5 is turned on at the initial time of the stage T5. Wherein, since the fourth transistor M4 is in an on state, the potential of the second node B and the third node C are equal to each other, which is equal to the potential of the first reference voltage signal Vref 1; since the first node a and the second node B are connected and have equal potential, the first node a and the third node C have equal potential, which is equivalent to the equal potential at both ends of the second transistor M2, the second transistor M2 cannot be turned on, the current flowing is 0, and the potential of the third node C cannot leak through the second transistor M2.

In the stage T5, also called a compensation stage, the Clear signal Clear and the emission control signal EM are at high level, and the Scan signal Scan is at low level. The Scan signal Scan controls the tenth transistor M10, the first transistor M1, and the second transistor M2 to be turned on, and transmits the data signal Vdata to the third node C via the first and second poles of the driving transistor M5. Since the data signal Vdata passes through the turned-on driving transistor M5, the potential vc=vdata+vth of the gate electrode of the driving transistor M5 is written, and the threshold voltage compensation of the driving transistor M5 is completed. Wherein, the second transistor M2 is in a conducting state, so that the potential of the first node A and the potential of the third node C are equal; since the first node a and the second node B are connected to each other and have the same potential, the second node B and the third node C have the same potential, which is equivalent to the potential at both ends of the fourth transistor M4, the fourth transistor M4 cannot be turned on, the current flowing through the fourth transistor M4 is 0, and the potential of the third node C cannot leak through the fourth transistor M4. Meanwhile, the second capacitor C2 stores the potentials of the first node a and the second node B, and the first capacitor C1 stores the potential of the third node C.

The stage T6, also called a light emitting stage, is a high level for the Scan signal Scan and the Clear signal Clear, and a low level for the light emission control signal EM. The light emission control signal EM controls the eleventh transistor M11 and the twelfth transistor M12 to be turned on, the first electrode of the driving transistor M5 is turned on the first power signal VDD, the second electrode is turned on the light emitting device LED, and then the second power signal VSS is turned on, and the driving transistor M5 generates the driving current Id in response to the data signal Vdata, specifically:

Therefore, the driving current Id generated by the pixel circuit provided by the embodiment of the invention is irrelevant to the threshold voltage of the driving transistor M5, and is only relevant to the magnitudes of the data signal Vdata and the first power supply signal VDD, so that the compensation of the threshold voltage is realized, the influence of the threshold voltage on the analog driving current Id is avoided, the display uniformity of the display panel is improved, the display image quality is improved, and the performance of the pixel circuit is further improved.

The Scan signal Scan controls the tenth transistor M10, the first transistor M1, and the second transistor M2 to be turned off, and the Clear signal Clear controls the third transistor M3 and the fourth transistor M4 to be turned off. The first node a and the second node B still maintain the potential of the phase T5 due to the storage effect of the second capacitor C2, and the third node C still maintains the potential of the phase T5 due to the storage effect of the first capacitor C1. Therefore, the potentials of the first node a, the second node B and the third node C are still equal, which is equivalent to the equal potential at both ends of the fourth transistor M4, the fourth transistor M4 cannot be turned on, the potential at both ends of the first transistor M1 is equal, the first transistor M1 cannot be turned on, and the third node C cannot leak current through the first transistor M1 and the fourth transistor M4.

In summary, the data writing module 200 according to the embodiment of the invention includes the first writing unit 210 and the second writing unit 220, and the first writing unit 210 and the second writing unit 220 are connected in series in the data writing path. And, the data erasing module 300 according to the embodiment of the present invention includes a first erasing unit 310 and a second erasing unit 320, and the first erasing unit 310 and the second erasing unit 320 are connected in series in the reference voltage signal writing path. The connection point of the first writing unit 210 and the second writing unit 220 is a first node a, the connection point of the first erasing unit 310 and the second erasing unit 320 is a second node B, and the first node a and the second node B are connected with equal potential. By doing so, it is possible to maintain the electric potentials of the first node a, the second node B, and the control terminal of the driving module 100 equal when the first writing unit 210 and the second writing unit 220 are turned on, preventing the electric potential of the control terminal of the driving module 100 from leaking through the first erasing unit 310 or the second erasing unit 320; and when the first clearing unit 310 and the second clearing unit 320 are turned on, the electric potentials of the first node a, the second node B and the control end of the driving module 100 are maintained to be equal, so that the electric potential of the control end of the driving module 100 is prevented from leaking through the first writing unit 210 or the second writing unit 220, thereby being beneficial to reducing the power consumption of the pixel circuit, being beneficial to the stable light emission of the light emitting device LED, improving the performance of the pixel circuit and being beneficial to the low-frequency driving of the pixel circuit.

It should be noted that, the pixel circuit provided in the embodiment of the present invention is not limited to the case shown in the drawings, and the embodiment of the present invention is applicable to other types of pixel circuits.

The embodiment of the invention also provides a display panel which can be an Organic Light-Emitting Diode (OLED), a Micro Light-Emitting Diode (Micro Light Emitting Diode) display panel or a Light-Emitting Diode (Light Emitting Diode) display panel. The display panel comprises the pixel circuit provided by any embodiment of the invention, and the technical principle and the generated effect are similar and are not repeated.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (13)

1. A pixel circuit, comprising:

the driving module is used for responding to the data signal to generate driving current and driving the light emitting device to emit light;

the data writing module is used for writing data signals into the control end of the driving module; the data writing module comprises a first writing unit and a second writing unit, and the first writing unit and the second writing unit are connected in series in a signal path for writing the data signals; the connection point of the first writing unit and the second writing unit is a first node;

the data clearing module is used for writing a reference voltage signal into a control end of the driving module, and comprises a first clearing unit and a second clearing unit which are connected in series in a signal path in which the reference voltage signal is written; the connection point of the first clearing unit and the second clearing unit is a second node; the first node and the second node are connected so that the potentials of the first node and the second node are equal;

the pixel circuit further comprises a second storage module, wherein the second storage module is connected with the first node and is used for storing the potential of the first node;

The second storage module is a second capacitor, a first end of the second capacitor is connected to a second fixed potential, and a second end of the second capacitor is connected with the first node.

2. The pixel circuit of claim 1, wherein the first write unit comprises a control terminal, a first terminal, and a second terminal; the second writing unit comprises a control end, a first end and a second end;

the control end of the first writing unit and the control end of the second writing unit are both connected with scanning signals, the first end of the first writing unit is connected with the data signals, the second end of the first writing unit is connected with the first end of the second writing unit, and the second end of the second writing unit is connected with the control end of the driving module;

the first cleaning unit comprises a control end, a first end and a second end; the second cleaning unit comprises a control end, a first end and a second end;

the control end of the first clearing unit and the control end of the second clearing unit are connected with clearing signals, the first end of the first clearing unit is connected with a reference voltage signal, the second end of the first clearing unit is connected with the first end of the second clearing unit, and the second end of the second clearing unit is connected with the control end of the driving module.

3. The pixel circuit according to claim 2, wherein the first writing unit includes a first transistor, and the second writing unit includes a second transistor; the grid electrode of the first transistor and the grid electrode of the second transistor are both connected with the scanning signal, the first electrode of the first transistor is connected with the data signal, the second electrode of the first transistor is connected with the first electrode of the second transistor, and the second electrode of the second transistor is connected with the control end of the driving module;

the first clearing unit comprises a third transistor, and the second clearing unit comprises a fourth transistor; the gate of the third transistor and the gate of the fourth transistor are both connected with the clearing signal, the first electrode of the third transistor is connected with the reference voltage signal, the second electrode of the third transistor is connected with the first electrode of the fourth transistor, and the second electrode of the fourth transistor is connected with the control end of the driving module.

4. A pixel circuit according to claim 3, wherein the drive module comprises a drive transistor, the gate of the drive transistor being the control terminal of the drive module; the grid electrode of the driving transistor is directly connected with the data output end of the data writing module;

The reference voltage signal and the data signal are opposite in level; channel types of the first transistor and the second transistor are opposite to channel types of the driving transistor; and channel types of the third transistor and the fourth transistor are the same as channel types of the driving transistor;

alternatively, the reference voltage signal and the data signal have the same level; channel types of the first transistor, the second transistor, the third transistor, and the fourth transistor are opposite to channel types of the driving transistor.

5. A pixel circuit according to claim 3, wherein the drive module comprises a drive transistor, the gate of the drive transistor being the control terminal of the drive module; the grid electrode of the driving transistor is connected with the data output end of the data writing module through a latch;

the reference voltage signal and the data signal are opposite in level; the channel types of the first transistor and the second transistor are the same as the channel type of the driving transistor; and the channel types of the third transistor and the fourth transistor are opposite to the channel type of the driving transistor.

6. A pixel circuit according to claim 3, wherein the drive module comprises a drive transistor, the gate of the drive transistor being the control terminal of the drive module; the channel types of the driving transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor are all the same.

7. The pixel circuit of claim 1, further comprising: a first storage module; the first storage module is connected with the control end of the driving module and is used for storing the electric potential of the control end of the driving module.

8. The pixel circuit according to claim 7, wherein the first storage module comprises a first capacitor, a first end of the first capacitor is connected to a first fixed potential, and a second end of the first capacitor is connected to a control end of the driving module;

alternatively, the first memory module includes latches connected in series between the data output terminal of the data writing module and the control terminal of the driving module.

9. The pixel circuit of claim 7, wherein the first memory module comprises a first capacitor, the first power signal or the second power signal being multiplexed to a first fixed potential; the first power supply signal and the second power supply signal are signals for generating a driving current.

10. The pixel circuit of claim 7, wherein the second storage module comprises a second capacitor, a first end of the second capacitor is connected to a second fixed potential, and a second end of the second capacitor is connected to the first node.

11. The pixel circuit according to claim 10, wherein the reference voltage signal, the first power supply signal, or the second power supply signal is multiplexed to the second fixed potential; the first power supply signal and the second power supply signal are signals for generating a driving current.

12. The pixel circuit of claim 1, wherein the pixel circuit is a digital drive pixel circuit and the data signal is a digital data signal; the driving module is used for generating digital driving current in response to the digital data signal in a subframe and is used for being turned off in response to the reference voltage signal;

or the pixel circuit is an analog driving pixel circuit, and the data signal is an analog data signal; the driving module is used for initializing in response to the reference voltage signal in one frame and is used for generating an analog driving current in response to the analog data signal.

13. A display panel, comprising: a pixel circuit as claimed in any one of claims 1 to 12.