CN114822352A - Grid driving circuit, display panel and display device - Google Patents

Abstract

The application provides a grid driving circuit, a display panel and a display device, and relates to the technical field of display; the gate driving circuit comprises a plurality of cascade-connected gate driving units, and each stage of gate driving unit comprises: the control module is electrically connected to the first node and is used for controlling the potential of the first node; the pull-up module is electrically connected to the first node and the current-stage scanning signal output end and is used for pulling up the potential of the current-stage scanning signal output end under the control of the potential of the first node; and the pull-down module is electrically connected to the first node and the current-level scanning signal output end and is used for pulling down the potential of the current-level scanning signal output end under the control of the potential of the first node. The charge and discharge of the first node in the grid drive unit can be combined into one, the number of components in the grid drive unit is reduced, and the requirements of high screen occupation ratio and narrow frame are favorably met.

Description

Grid driving circuit, display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a gate driving circuit, a display panel and a display device.

Background

In the prior art, a display panel in a display device generally adopts an Amorphous Silicon Gate (ASG) driving circuit, and with the development of the society, users increasingly pursue high screen occupation ratio and narrow frame for the display device, and the compression of the ASG on a layout space is a subject which exists all the time; the existing ASG adopts a relatively complex architecture, such as an 11T1C architecture, having 11 transistors; such a number of transistors can still meet customer needs in the recent past, but with the screen becoming more competitive hotter, the ASG of this architecture will also become a toggle that hinders narrow borders; therefore, it is desirable to invent an ASG with a relatively small number of transistors to meet the requirements of high screen ratio and narrow frame.

Disclosure of Invention

In view of the above, the present invention provides a gate driving circuit, a display panel and a display device, so as to meet the requirements of high screen ratio and narrow frame.

In a first aspect, the present application provides a gate driving circuit, including a plurality of gate driving units arranged in a cascade, where each of the gate driving units includes:

the control module is electrically connected to a first node and is used for controlling the potential of the first node;

the pull-up module is electrically connected to the first node and the current-stage scanning signal output end, and is used for pulling up the potential of the current-stage scanning signal output end under the control of the potential of the first node;

and the pull-down module is electrically connected to the first node and the current-stage scanning signal output end, and is used for pulling down the potential of the current-stage scanning signal output end under the control of the potential of the first node.

In a second aspect, the present application provides a display panel, which includes the gate driving circuit.

In a third aspect, the present application provides a display device, comprising the display panel.

Compared with the prior art, the gate driving circuit, the display panel and the display device provided by the invention at least realize the following beneficial effects:

the application provides a grid drive circuit, a display panel and a display device, wherein each level of grid drive unit in the grid drive circuit comprises a control module, a pull-up module and a pull-down module, so that the control module is used for charging or discharging a first node, and the first node is in a high potential or a low potential; the pull-up module is used for pulling up the potential of the output end of the scanning signal of the current stage in the grid driving unit under the control of the potential of the first node; the pull-down module is used for pulling down the potential of the output end of the scanning signal of the current stage in the grid driving unit under the control of the potential of the first node; so set up, realized that the charge-discharge of first node can unite into one in the gate drive unit to can reduce the quantity that sets up of components and parts in the gate drive unit, thereby be favorable to adapting to the demand that the high screen accounts for the ratio and narrow frame ization.

Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;

fig. 2 is a circuit diagram of a gate driving unit according to an embodiment of the present disclosure;

fig. 3 is a circuit diagram of another gate driving unit according to an embodiment of the present disclosure;

fig. 4 is a circuit diagram of another gate driving unit according to an embodiment of the present disclosure;

fig. 5 is a circuit diagram of another gate driving unit according to an embodiment of the present disclosure;

fig. 6 is a circuit diagram of another gate driving unit according to an embodiment of the present disclosure;

fig. 7 is a circuit diagram of another gate driving unit according to an embodiment of the present disclosure;

fig. 8 is another schematic diagram of a gate driving circuit according to an embodiment of the disclosure;

fig. 9 is another schematic diagram of a gate driving circuit according to an embodiment of the disclosure;

fig. 10 is a driving waveform diagram of a gate driving circuit corresponding to fig. 1 or fig. 9 according to an embodiment of the present disclosure;

fig. 11 is a driving waveform diagram of the gate driving circuit of fig. 8 according to an embodiment of the present disclosure;

fig. 12 is a schematic view of a display panel according to an embodiment of the present disclosure;

fig. 13 is a schematic view of a display device according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be discussed further in subsequent figures.

In the prior art, a display panel in a display device generally adopts an Amorphous Silicon Gate (ASG) driving circuit, and with the development of the society, users increasingly pursue high screen occupation ratio and narrow frame for the display device, and the compression of the ASG on a layout space is a subject which exists all the time; the existing ASG adopts a relatively complex architecture, such as an 11T1C architecture, having 11 transistors; such a number of transistors can still meet customer needs in the recent past, but with the screen becoming more competitive hotter, the ASG of this architecture will also become a toggle that hinders narrow borders; therefore, it is desirable to invent an ASG with a relatively small number of transistors to meet the requirements of high screen ratio and narrow frame.

In view of the above, the present invention provides a gate driving circuit, a display panel and a display device, so as to meet the requirements of high screen ratio and narrow frame.

Fig. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention, fig. 2 is a circuit diagram of a gate driving unit according to an embodiment of the present invention, and referring to fig. 1 and fig. 2, the present invention provides a gate driving circuit 100 including a plurality of gate driving units 101 arranged in a cascade, each stage of the gate driving unit 101 includes:

the control module 10, the control module 10 is electrically connected to the first node P, and the control module 10 is configured to control a potential of the first node P;

the pull-up module 20, the pull-up module 20 is electrically connected to the first node P and the present-level scanning signal output terminal GOUT, the pull-up module 20 is configured to pull up the potential of the present-level scanning signal output terminal GOUT under the control of the potential of the first node P;

the pull-down module 30, the pull-down module 30 is electrically connected to the first node P and the present-stage scan signal output terminal GOUT, and the pull-down module 30 is configured to pull down the potential of the present-stage scan signal output terminal GOUT under the control of the potential of the first node P.

Specifically, with continuing reference to fig. 1 and fig. 2, the present application provides a gate driving circuit 100, where the gate driving circuit 100 includes a plurality of gate driving units 101 connected in cascade, and each gate driving unit 101 includes at least three modules, specifically, a control module 10, a pull-up module 20, and a lower module 30. The control module 10 is electrically connected to the first node P, and the control module 10 adjusts the potential of the first node P, for example, the control module 10 can adjust the first node P to be at a high potential or a low potential. On this basis, this application sets up pull-up module 20 also with first node P electric connection, and connects this level scanning signal output GOUT simultaneously, and pull-up module 20 is used for receiving the electric potential of first node P, under the control of first node P electric potential, realizes pulling up the electric potential of the signal of telecommunication that this level scanning signal output GOUT outputs to make this level scanning signal output GOUT can output high level electric potential. On this basis, this application sets up pull-down module 30 also with first node P electric connection, and connects this level scanning signal output GOUT simultaneously, and pull-down module 30 is used for receiving the electric potential of first node P, under the control of first node P electric potential, realizes pulling down the electric potential of the signal of telecommunication that this level scanning signal output GOUT outputs to make this level scanning signal output GOUT can output low level electric potential.

That is, in the gate driving unit 101 provided in the present application, through the control of the control module 10 on the potential condition of the first node P, different potentials of the first node P are respectively used for controlling the pull-up module 20 to output a high level potential to the current-stage scanning signal output terminal GOUT, and controlling the pull-down module 30 to output a level potential to the current-stage scanning signal output terminal GOUT, so that the control of different potentials transmitted by the current-stage scanning signal output terminal GOUT through different magnitudes of the potential of the first node P can be achieved. More specifically, in the gate driving unit 101 provided in the present application, charging and discharging of the first node P can be integrated, and all can be realized by one control module 10, and it is not necessary to set two or more control modules for controlling the potential of the first node P, so as to be beneficial to reducing the number of components in the gate driving unit 101, and further beneficial to meeting the design requirements of high screen occupation ratio and narrow frame.

Fig. 3 is another circuit diagram of the gate driving unit according to the embodiment of the present application, referring to fig. 1 to 3, optionally, the control module 10 includes a first transistor T1 and a bootstrap capacitor C, a gate of the first transistor T1 is electrically connected to the first clock signal terminal CK, one of a source and a drain of the first transistor T1 is electrically connected to the previous stage scan signal input terminal GN-1, and the other of the source and the drain of the first transistor T1 is electrically connected to the first node P;

one end of the bootstrap capacitor C is electrically connected to the first node P, and the other end of the bootstrap capacitor C is electrically connected to the current-stage scanning signal output terminal GOUT.

Specifically, the gate driving unit 101 provided in the present application includes a control module 10, and the control module 10 may include a first transistor T1 and a bootstrap capacitor C; specifically, the gate of the first transistor T1 is electrically connected to the first clock signal terminal CK, one of the source or the drain is electrically connected to the previous-stage scanning signal input terminal GN-1, and the other of the source or the drain is electrically connected to the first node P; the turn-on or turn-off of the first transistor T1 is controlled by an electrical signal transmitted from the first clock signal terminal CK to the gate of the first transistor T1, so that it can be controlled whether the previous stage scan signal input terminal GN-1 can transmit an electrical signal to the first node P through the first transistor T1.

That is, the control module 10 in the gate driving unit 101 of the present application is configured to control the first transistor T1 to be turned off or on through the first clock signal terminal CK, so as to control whether the first node P can receive the electrical signal transmitted from the previous stage scanning signal input terminal GN-1, thereby implementing charging or discharging of the first node P by the control module 10. Obviously, in the present application, charging or discharging of the first node P can be realized by setting one control module 10, and it is not necessary to set two or more control modules for controlling the potential of the first node P, so that the number of components in the gate driving unit 101 is reduced, and the design requirements of current high screen occupation ratio and narrow frame are adapted.

It should be added that, when the gate driving unit 101 is the 1 st stage gate driving unit 101 in the gate driving circuit 100, the previous stage scanning signal input terminal GN-1 receives a start signal for triggering the 1 st stage gate driving unit 101 to output a scanning driving signal, and at the same time, the 1 st stage gate driving unit 101 can start to transmit an electrical signal to the next stage gate driving unit 101, so as to realize the step-by-step transmission of the scanning driving signal.

Referring to fig. 1 to fig. 3, optionally, the pull-up module 20 includes a second transistor T2, a gate of the second transistor T2 is electrically connected to the first node P, one of a source and a drain of the second transistor T2 is electrically connected to the second clock signal terminal CKB, and the other of the source and the drain of the second transistor T2 is electrically connected to the present-stage scan signal output terminal GOUT.

Specifically, the gate driving unit 101 provided by the present application includes a pull-up module 20, the pull-up module 20 may include a second transistor T2, a gate of the second transistor T2 is electrically connected to the first node P, and the second transistor T2 is controlled to be in an on state or an off state according to whether the first node P is in a charged state or a discharged state; one of the source or the drain of the second transistor T2 is electrically connected to the second clock signal terminal CKB, and the other of the source or the drain is electrically connected to the present-stage scanning signal output terminal GOUT; when the potential of the first node P controls the second transistor T2 to be in the on state, the transmission of the electrical signal received by the second clock signal terminal CKB to the current-stage scanning signal output terminal GOUT can be realized, and the electrical signal transmitted by the second clock signal terminal CKB through the second transistor T2 can be used for realizing the potential pull-up of the electrical signal output by the current-stage scanning signal output terminal GOUT.

That is, in the present application, the control module 10 transmits the potential to the first node P, so that the second transistor T2 is in an on state under the control of the potential of the first node P, and the electrical signal received by the second clock signal terminal CKB is transmitted to the current scanning signal output terminal GOUT.

With continued reference to fig. 1-3, optionally, the pull-down module 30 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a second node Q;

a gate of the third transistor T3 is electrically connected to the first node P, one of a source and a drain of the third transistor T3 is electrically connected to the second node Q, and the other of the source and the drain of the third transistor T3 is electrically connected to the first level signal terminal VGL;

a gate of the fourth transistor T4 is electrically connected to the second level signal terminal VGH, one of a source and a drain of the fourth transistor T4 is electrically connected to the second level signal terminal VGH, and the other of the source and the drain of the fourth transistor T4 is electrically connected to the second node Q;

a gate of the fifth transistor T5 is electrically connected to the second node Q, one of a source and a drain of the fifth transistor T5 is electrically connected to the first level signal terminal VGL, and the other of the source and the drain of the fifth transistor T5 is electrically connected to the present-stage scan signal output terminal GOUT;

the gate of the sixth transistor T6 is electrically connected to the second node Q, one of the source and the drain of the sixth transistor T6 is electrically connected to the first node P, and the other of the source and the drain of the sixth transistor T6 is electrically connected to the first level signal terminal VGL.

Specifically, the gate driving unit 101 provided by the present application further includes a pull-down module 30, and an optional setting manner is provided in the present application, where the pull-down module 30 at least includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a second node Q.

A gate of the third transistor T3 is electrically connected to the first node P for receiving a potential of the first node P, so as to control the third transistor T3 to be in an on state or an off state, one of a source or a drain of the third transistor T3 is electrically connected to the second node Q, and the other of the source or the drain is electrically connected to the first level signal terminal VGL; one of the gate and the source or the drain of the fourth transistor T4 is electrically connected to the second level signal terminal VGH, the type of the electrical signal of the second level signal terminal VGH can be used to control the fourth transistor T4 to be in an on state or an off state, and the other of the source or the drain of the fourth transistor T4 is electrically connected to the second node Q, and when the fourth transistor T4 is in the on state, the other can be used to transmit the electrical signal received by the second level signal terminal VGH to the second node Q; the gate of the fifth transistor T5 is electrically connected to the second node Q, the potential of the second node Q may be used to control the fifth transistor T5 to be in an on state or an off state, one of the source or the drain of the fifth transistor T5 is electrically connected to the first level signal terminal VGL, the other is electrically connected to the present-level scan signal output terminal GOUT, when the fifth transistor T5 is in the on state, the fifth transistor T5 may be used to transmit the electrical signal of the first level signal terminal VGL to the present-level scan signal output terminal GOUT, and the scan driving signal transmitted by the gate driving unit 101 is the electrical signal received by the first level signal terminal VGL; the gate of the sixth transistor T6 is electrically connected to the second node Q, and is configured to control the sixth transistor T6 to be in an on state or an off state according to the potential of the second node Q, one of the source and the drain of the sixth transistor T6 is electrically connected to the first node P, and the other is electrically connected to the first level signal terminal VGL.

That is, the control module 10 transmits a potential to the first node P, so that the third transistor T3 can be driven to be in a turned-off state under the control of the potential of the first node P, and the second node Q can receive an electrical signal transmitted by the second level signal terminal VGH, where the electrical signal can be used to drive the fifth transistor T5 and the sixth transistor T6 to be in a turned-on state. When the fifth transistor T5 is in an on state, the electrical signal received by the first level signal terminal VGL can be transmitted to the present-stage scanning signal output terminal GOUT through the fifth transistor T5, so as to pull down the potential of the present-stage scanning signal output terminal GOUT; the sixth transistor T6 is turned on to pull down the potential of the first node P through the electrical signal received by the first level signal terminal VGL, so as to maintain the low potential state of the first node P.

Therefore, the present application realizes that, by setting a control module 10 to control the potential of the first node P, according to the different types of the potential of the first node P, the transmission of the electrical signal of the second clock signal terminal CKB to the local scanning signal output terminal GOUT can be achieved, and the transmission of the electrical signal of the first level signal terminal VGL to the local scanning signal output terminal GOUT can also be achieved; meanwhile, the transistors required to be arranged in the control module 10 provided by the present application include only one first transistor T1; obviously, in the present application, charging or discharging of the first node P can be realized by setting one control module 10, two or more control modules 10 do not need to be set for controlling the potential of the first node P, and only one transistor is needed in the control module 10, which is beneficial to reducing the number of components in the gate driving unit 101, and is further beneficial to meeting the design requirements of high screen occupation ratio and narrow frame.

It should be further noted that, in this embodiment, each gate driving unit 101 only needs to be provided with 6 transistors and one bootstrap capacitor C, so as to meet the working requirements of each level of the gate driving unit 101, and compared with the prior art, the gate driving unit 101 provided in the present application greatly reduces the number of components that need to be provided, can greatly compress the required area of the whole gate driving circuit 100 that needs to be provided in one display device, breaks through the obstruction of the gate driving circuit 100 to the narrow frame of the display device, and is favorable for adapting to the requirements of the current user for a high screen ratio and a narrow frame display device.

It should be added that the types of the electrical signals received by the first clock signal terminal CK and the second clock signal terminal CKB in the gate driving unit 101 are inverted clock signals.

The driving timing of the gate driving circuit 100 provided by the present application includes a charging phase, an outputting phase, a pulling-down phase and a maintaining phase. Wherein, in the charging phase, the first transistor T1 is turned on, charging the first node P1; in the output stage, the local scanning signal output end GOUT outputs the local scanning signal to the scanning line electrically connected with the local scanning signal output end GOUT; in the pull-down stage, the potential of the first node P1 and the potential of the output terminal GOUT of the scan signal of the current stage are pulled down; in the hold phase, the voltage level of the first node P1 and the voltage level of the output terminal GOUT of the current stage of scan signal are maintained.

The specific operation process of the gate driving unit 101 is as follows: first, the first clock signal terminal CK and the previous scan signal input terminal GN-1 are controlled to be simultaneously raised from a low potential to a high potential, and the high potential of the first clock signal terminal CK drives the first transistor T1 to be turned on, so that the high potential of the previous scan signal input terminal GN-1 can be transmitted to the first node P through the first transistor T1, and the first node P is charged, so that the first node P reaches the high potential. Since the first node P is at a high potential, the gates of the second transistor T2 and the third transistor T3 are both electrically connected to the first node P, so that the high potential of the first node P can drive the second transistor T2 and the third transistor T3 to be turned on; when the third transistor T3 is turned on, since the second level signal terminal VGH transmits a high voltage to the second node Q, the first level signal terminal VGL transmits a low voltage to the second node Q via the third transistor T3, so that the second node Q is discharged and the voltage at the second node Q drops; since the gates of the fifth and sixth transistors T5 and T6 are electrically connected to the second node Q, the drop of the potential of the second node Q may cause the fifth and sixth transistors T5 and T6 to be in an off state.

Then, the first clock signal terminal CK and the previous stage scanning signal input terminal GN-1 are controlled to be lowered from a high potential to a low potential at the same time, and the second clock signal terminal CKB is controlled to be raised from a low potential to a high potential, due to the function of the bootstrap capacitor C, the first node P still maintains a high potential state, at this time, the second transistor T2 is still in an open state, and the raised high potential of the second clock signal terminal CKB can be transmitted to the present stage scanning signal output terminal GOUT through the second transistor T2.

Then, the second clock signal terminal CKB is controlled to be lowered from a high potential to a low potential, the first clock signal terminal CK is controlled to be raised from the low potential to the high potential, the previous scanning signal input terminal GN-1 maintains the low potential, at this time, the first transistor T1 is turned on, the high potential of the first node P is discharged through the first transistor T1, and the first node P reaches the low potential; therefore, the second transistor T2 and the third transistor T3 electrically connected to the first node P are in an off state, and at this time, the second node Q receives a high voltage transmitted through the fourth transistor T4 to charge the second node Q, so that the voltage of the second node Q is raised, and thus the fifth transistor T5 and the sixth transistor T6 electrically connected to the second node Q are in an on state; the fifth transistor T5 and the sixth transistor T6 maintain the low potential of the first node P, and allow the first level signal terminal VGL to transmit the low potential to the present stage scan signal output terminal GOUT through the fifth transistor T.

Fig. 4 is another circuit diagram of the gate driving unit according to the embodiment of the present application, referring to fig. 2 and fig. 4, optionally, the pull-down module 30 further includes a seventh transistor T7;

the gate of the seventh transistor T7 is electrically connected to the next-stage scan signal input terminal GN +1, one of the source and the drain of the seventh transistor T7 is electrically connected to the second level signal terminal VGH, and the other of the source and the drain of the seventh transistor T7 is electrically connected to the second node Q.

Specifically, on the basis that the pull-down module 30 includes the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, the present application also provides an alternative embodiment that the pull-down module 30 may further include a seventh transistor T7, where a gate of the seventh transistor T7 may be connected to the next-stage scan signal input terminal GN +1, an electrical signal transmitted by the next-stage scan signal input terminal GN +1 may be used to control the seventh transistor T7 to be in an on state or an off state, one of a source or a drain of the seventh transistor T7 is electrically connected to the second level signal terminal VGH, and the other is electrically connected to the second node Q; when the seventh transistor T7 is in an on state, the electrical signal received by the second level signal terminal VGH can be directly transmitted to the second node Q through the seventh transistor T7.

It should be added that, when the pull-down module 30 does not include the seventh transistor T7, after the previous-stage scan signal input terminal GN-1 is required to pull down the potential of the first node P through the first transistor T1, the first node P does not suppress the potential of the second node Q, and the second level signal terminal VGH can only pass through the fourth transistor T4 to raise the potential of the second node Q; when the seventh transistor T7 is disposed in the pull-down module 30, and the seventh transistor T7 is controlled to be in an on state by the next-stage scan signal input terminal GN +1, the second level signal terminal VGH may be directly charged to the second node Q through the seventh transistor T7. The second node Q receives the electrical signal transmitted by the second level signal terminal VGH, so that the second node Q is maintained at a high potential, the gates of the fifth transistor T5 and the sixth transistor T6 both receive the high potential electrical signal from the second node Q, and the fifth transistor T5 and the sixth transistor T6 are maintained in a stable on state, so that the electrical signal received by the first level signal terminal VGL can be used for pulling down the potential of the first node P through the sixth transistor T6, and the low potential state of the first node P is maintained; that is, the provision of the seventh transistor T7 enables the second node Q to be maintained at a high potential, thereby accelerating the pull-down of the potential at the first node P.

Fig. 5 is another circuit diagram of the gate driving unit according to the embodiment of the present application, referring to fig. 2 and fig. 5, optionally, the pull-down module 30 further includes a seventh transistor T7;

the gate of the seventh transistor T7 is electrically connected to the next-stage scan signal input terminal GN +1, one of the source and the drain of the seventh transistor T7 is electrically connected to the next-stage scan signal input terminal GN +1, and the other of the source and the drain of the seventh transistor T7 is electrically connected to the second node Q.

Specifically, on the basis that the pull-down module 30 includes the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, the present application also provides an alternative embodiment that the pull-down module 30 may further include a seventh transistor T7, where a gate of the seventh transistor T7 may be connected to the next-stage scan signal input terminal GN +1, an electrical signal transmitted by the next-stage scan signal input terminal GN +1 may be used to control the seventh transistor T7 to be in an on state or an off state, one of a source and a drain of the seventh transistor T7 is also electrically connected to the next-stage scan signal input terminal GN +1, and the other is electrically connected to the second node Q; when the seventh transistor T7 is turned on, the electrical signal received by the next-stage scan signal input terminal GN +1 can be directly transmitted to the second node Q via the seventh transistor T7.

It should be added that, when the pull-down module 30 does not include the seventh transistor T7, after the previous-stage scan signal input terminal GN-1 is required to pull down the potential of the first node P through the first transistor T1, the first node P does not suppress the potential of the second node Q, and the second level signal terminal VGH can only pass through the fourth transistor T4 to raise the potential of the second node Q; when the seventh transistor T7 is disposed in the pull-down block 30, and the seventh transistor T7 is controlled to be in an on state by the next-stage scan signal input terminal GN +1, a high potential received by the next-stage scan signal input terminal GN +1 can be directly charged to the second node Q through the seventh transistor T7.

Fig. 6 is another circuit diagram of the gate driving unit according to the embodiment of the present application, please refer to fig. 1, fig. 2 and fig. 6, wherein optionally, each stage of the gate driving unit 101 further includes an eighth transistor T8;

the gate of the eighth transistor T8 is electrically connected to the switch control signal terminal goff; one of a source and a drain of the eighth transistor T8 is electrically connected to the current-stage scan signal output terminal GOUT, and the other of the source and the drain of the eighth transistor T8 is electrically connected to the first level signal terminal VGL.

Specifically, in the technology of the gate driving unit 101 including the control module 10, the pull-up module 20 and the pull-down module 30, it is further added that each stage of the gate driving unit 101 further includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the switch control signal terminal goff for controlling the eighth transistor T8 to be in an on state or an off state according to a type of an electrical signal received by the switch control signal terminal goff, one of a source or a drain of the eighth transistor T8 is electrically connected to the present-stage scanning signal output terminal GOUT, and the other is electrically connected to the first level signal terminal VGL.

It should be added that when the gate of the eighth transistor T8 is set to be electrically connected to the switch control signal terminal goff, the switch control signal terminal goff may be set to be raised only before the start of each frame or during the touch; before the start of each frame, the switch controls the signal terminal goff to be turned on, which can be used to release the static electricity existing in the scanning line electrically connected to the scanning signal output terminal GOUT of the current stage to the first level signal terminal VGL through the eighth transistor T8, thereby avoiding the static electricity existing in the scanning line; the switch control signal terminal goff is opened during swiping touch, so that the scanning line electrically connected with the scanning signal output terminal GOUT at the current level can be electrically connected with the first level signal terminal VGL of the effective potential through the eighth transistor T8, the scanning line is prevented from being in a suspended state during swiping touch, and the stability of the scanning line is ensured.

Fig. 7 is another circuit diagram of the gate driving unit according to the embodiment of the present application, and fig. 8 is another schematic diagram of the gate driving unit according to the embodiment of the present application, please refer to fig. 2, fig. 7 and fig. 8, optionally, each stage of the gate driving unit 101 further includes an eighth transistor T8;

a gate of the eighth transistor T8 is electrically connected to the first clock signal terminal CK; one of a source and a drain of the eighth transistor T8 is electrically connected to the current-stage scan signal output terminal GOUT, and the other of the source and the drain of the eighth transistor T8 is electrically connected to the first level signal terminal VGL.

Specifically, in the technology of the gate driving unit 101 including the control module 10, the pull-up module 20 and the pull-down module 30, it is further added that each stage of the gate driving unit 101 further includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the first clock signal terminal CK for controlling the eighth transistor T8 to be in an on state or an off state according to a type of an electrical signal received by the first clock signal terminal CK, one of a source and a drain of the eighth transistor T8 is electrically connected to the present-stage scanning signal output terminal GOUT, and the other is electrically connected to the first level signal terminal VGL.

It should be added that the gate of the eighth transistor T8 is electrically connected to the first clock signal terminal CK, and the first clock signal terminal CK is turned on for a plurality of times in each frame of picture, so that the scan lines electrically connected to the gate driving unit 101 at each stage can be discharged for a plurality of times within one frame of picture, and the stability of the scan lines can be further ensured.

It should be further added that, although the seventh transistor T7 and the next-stage scan signal input terminal GN +1 shown in fig. 4 and 5 are not included in the pull-down module 30 in the gate driving unit 101 shown in fig. 6 and 7, the present application is not limited thereto, and the seventh transistor T7 and the next-stage scan signal input terminal GN +1 shown in fig. 4 and 5 may also be added to the pull-down module 30 in the gate driving unit 101 shown in fig. 6 and 7.

Referring to fig. 1, optionally, the first clock signal line CK-L and the start signal line STV-L are included;

the first clock signal line CK-L is electrically connected to the first clock signal terminal CK of each stage of the gate driving unit 101;

the start signal line STV-L is electrically connected to the upper stage scanning signal input terminal GN-1 of the first stage gate driving unit 101;

the present-stage scanning signal output terminal GOUT of each stage of the Gate driving unit 101 is electrically connected to a scanning line (e.g., Gate1, Gate2, Gate3) and the previous-stage scanning signal input terminal GN-1 of the next-stage Gate driving unit 101, respectively.

Specifically, the gate driving circuit 100 includes, in addition to the gate driving units 101 with the various setting manners, a first clock signal line CK-L and a start signal line STV-L, wherein the first clock signal line CK-L is electrically connected to the first clock signal terminal CK of each stage of the gate driving unit 101, the start signal line STV-L is electrically connected to the previous scanning signal terminal CK of the 1 st stage of the gate driving unit 101 in the gate driving circuit 100, and meanwhile, the current scanning signal output terminal GOUT is electrically connected to the scanning line and the previous scanning signal input terminal GN-1 of the next stage of the gate driving unit 101, respectively.

With such a configuration, the start signal line STV-L is electrically connected to the previous scanning signal of the 1 st-level gate driving unit 101, and can be used to drive the current scanning signal output terminal GOUT of the 1 st-level gate driving unit 101 to have a scanning driving signal output, so as to implement the electrical signal transmission to the scanning line electrically connected to the gate driving unit 101 in the display device; and the scanning signal output terminal GOUT of the gate driving unit 101 and the scanning signal input terminal GN-1 of the previous stage of the gate driving unit 101 are also used for realizing the transmission of the electric signals among the cascaded gate driving units 101, so that each gate driving unit 101 can transmit the electric signals to the scanning lines respectively electrically connected with the gate driving unit step by step, and the scanning driving of the whole display panel is realized.

Fig. 9 is another schematic diagram of a gate driving circuit according to an embodiment of the present disclosure, please refer to fig. 9 in combination with fig. 4 and 5, and optionally includes a first clock signal line CK-L and a start signal line STV-L;

the first clock signal line CK-L is electrically connected to the first clock signal terminal CK of each stage of the gate driving unit 101;

the start signal line STV-L is electrically connected to the upper stage scanning signal input terminal GN-1 of the first stage gate driving unit 101;

the scanning signal output end GOUT of the current stage of the gate driving unit 101 of each stage is electrically connected with the scanning line and the previous stage scanning signal input end GN-1 of the next stage of the gate driving unit 101 respectively;

the next-stage scanning signal input terminal GN +1 of each stage of gate driving unit 101 is electrically connected to the present-stage scanning signal output terminal GOUT of the next-stage gate driving unit 101.

Specifically, when the gate driving unit 101 is further provided with a seventh transistor T7, a gate of the seventh transistor T7 is electrically connected to a next-stage scanning signal input terminal GN +1, and at this time, the present application provides an alternative embodiment that the gate driving circuit 100 further includes, in addition to the gate driving unit 101, a first clock signal line CK-L and a start signal line STV-L, wherein the first clock signal line CK-L is electrically connected to a first clock signal terminal CK of each stage of the gate driving unit 101, the start signal line STV-L is electrically connected to a previous-stage scanning signal of the 1 st-stage gate driving unit 101 in the gate driving circuit 100, and meanwhile, the current-stage scanning signal output terminal GOUT is electrically connected to the scanning line and the previous-stage scanning signal input terminal GN-1 of the next-stage gate driving unit 101, respectively; in addition to the 1 st stage gate driving unit 101, the present stage scanning signal output terminal GOUT of each stage of the gate driving unit 101 needs to be electrically connected to the next stage scanning signal input terminal GN +1 in the previous stage gate driving unit 101, so as to reset the next stage scanning signal input terminal GN +1 in the previous stage gate driving unit 101 by the scanning driving signal.

With such a configuration, the start signal line STV-L is electrically connected to the previous scanning signal of the 1 st-level gate driving unit 101, and can be used to drive the current scanning signal output terminal GOUT of the 1 st-level gate driving unit 101 to have a scanning driving signal output, so as to implement the electrical signal transmission to the scanning line electrically connected to the gate driving unit 101 in the display device; the present-stage scanning signal output end GOUT of the gate driving unit 101 and the previous-stage scanning signal input end GN-1 of the next-stage gate driving unit 101 are also used for realizing the electric signal transmission among the cascaded gate driving units 101, so that each gate driving unit 101 can transmit electric signals to the scanning lines respectively electrically connected with the gate driving unit step by step, and the scanning driving of the whole display panel is realized; each stage of the gate driving units 101 except for the 1 st stage of the gate driving unit 101 may also perform reset for the next stage of the scan signal input terminal GN +1 in the previous stage of the gate driving unit 101 by using the outputted scan driving signal.

Fig. 10 is a driving waveform diagram of the gate driving circuit corresponding to fig. 1 or fig. 9 according to an embodiment of the present disclosure, and fig. 11 is a driving waveform diagram of the gate driving circuit corresponding to fig. 8 according to an embodiment of the present disclosure, please refer to fig. 1 and fig. 8-fig. 11, alternatively, when the first clock signal line CK-L is used for transmitting a first clock signal to the first stage gate driving unit 101, the start signal line STV-L is used for transmitting a start signal to the first stage gate driving unit 101;

the pulse width of the start signal is less than or equal to the pulse width of the first clock signal, and the pulse signal of the start signal is within the pulse signal time range of the first clock signal.

Specifically, when the gate driving circuit 100 of the present application is in operation, the pulse width of the first clock signal line CK-L for transmitting the first clock signal to the first stage gate driving unit 101 is set to be equal to the pulse width of the start signal line STV-L for transmitting the start signal to the first stage gate driving unit 101 (as shown in fig. 10 and 11), or the pulse width of the start signal is set to be smaller than the pulse width of the first clock signal (not shown); on the basis of this, it is also necessary to set the pulse signal of the start signal to fall within the time range of the pulse signal of the first clock signal. With this arrangement, when the control module 10 (the first transistor T1) in the gate driving unit 101 is in the on state, the start signal line STV-L can transmit an electrical signal to the first node P through the previous scanning signal input terminal GN-1 in the gate driving unit 101, so as to achieve the effect of controlling different potentials of the first node P.

That is, if the start signal line STV-L does not start transmitting the start signal when the first clock signal drives the first transistor T1 to be turned on, the start signal cannot be transmitted to the first node P through the previous stage scan signal input terminal GN-1 and the first transistor T1, and the control module 10 cannot control different potentials of the first node P; through the arrangement, the charging or discharging of the first node P can be realized only by arranging one control module 10 in the gate driving unit 101, and the control module 10 only comprises one first transistor T1, and two or more control modules 10 are not required to be arranged for controlling the potential of the first node P, so that the arrangement number of components in the gate driving unit 101 is reduced, and the design requirements of current high screen ratio and narrow frame are met.

Fig. 12 is a schematic diagram of a display panel according to an embodiment of the present application, please refer to fig. 12 in conjunction with fig. 1 to 9, and based on the same inventive concept, the present application further provides a display panel 200, where the display panel 200 includes a gate driving circuit 100, and the gate driving circuit 100 is any one of the gate driving circuits 100 provided in the present application.

Fig. 13 is a schematic diagram of a display device according to an embodiment of the present application, please refer to fig. 13 in combination with fig. 1 to 9 and fig. 12, and based on the same inventive concept, the present application further provides a display device 300, where the display device 300 includes a display panel 200, and the display panel 200 is any one of the display panels 200 provided in the present application.

It should be noted that, for the embodiments of the display device 300 provided in the embodiments of the present application, reference may be made to the embodiments of the display panel 200, and repeated descriptions are omitted. The display device 300 provided by the present application may be: the touch control system comprises any products and components with a touch control function, such as a mobile phone, a tablet computer, a television, a touch controller, a notebook computer, a navigator and the like.

As can be seen from the above embodiments, the gate driving circuit, the display panel and the display device provided in the present invention at least achieve the following advantages:

the application provides a grid drive circuit, a display panel and a display device, wherein each level of grid drive unit in the grid drive circuit comprises a control module, a pull-up module and a pull-down module, so that the first node is charged or discharged through the control module and is in a high potential or a low potential; the pull-up module is used for pulling up the potential of the output end of the scanning signal of the current stage in the grid driving unit under the control of the potential of the first node; the pull-down module is used for pulling down the potential of the output end of the scanning signal of the current stage in the grid driving unit under the control of the potential of the first node; so set up, realized that the charge-discharge of first node can unite into one in the gate drive unit to can reduce the quantity that sets up of components and parts in the gate drive unit, thereby be favorable to adapting to the demand that the high screen accounts for the ratio and narrow frame ization.

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (13)

1. A gate drive circuit comprising a plurality of gate drive units arranged in cascade, each of said gate drive units comprising:

the control module is electrically connected to a first node and is used for controlling the potential of the first node;

the pull-up module is electrically connected to the first node and the current-stage scanning signal output end, and is used for pulling up the potential of the current-stage scanning signal output end under the control of the potential of the first node;

and the pull-down module is electrically connected to the first node and the current-stage scanning signal output end, and is used for pulling down the potential of the current-stage scanning signal output end under the control of the potential of the first node.

2. The gate driving circuit according to claim 1, wherein the control module comprises a first transistor and a bootstrap capacitor, a gate of the first transistor is electrically connected to a first clock signal terminal, one of a source or a drain of the first transistor is electrically connected to a previous stage scan signal input terminal, and the other of the source or the drain of the first transistor is electrically connected to the first node;

one end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current-stage scanning signal output end.

3. The gate driving circuit of claim 1, wherein the pull-up module comprises a second transistor, a gate of the second transistor is electrically connected to the first node, one of a source or a drain of the second transistor is electrically connected to a second clock signal terminal, and the other of the source or the drain of the second transistor is electrically connected to the present-stage scan signal output terminal.

4. The gate driving circuit of claim 1, wherein the pull-down module comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a second node;

a gate of the third transistor is electrically connected to the first node, one of a source or a drain of the third transistor is electrically connected to the second node, and the other of the source or the drain of the third transistor is electrically connected to a first level signal terminal;

a gate of the fourth transistor is electrically connected to a second level signal terminal, one of a source or a drain of the fourth transistor is electrically connected to the second level signal terminal, and the other of the source or the drain of the fourth transistor is electrically connected to the second node;

a gate of the fifth transistor is electrically connected to the second node, one of a source or a drain of the fifth transistor is electrically connected to the first level signal terminal, and the other of the source or the drain of the fifth transistor is electrically connected to the present-stage scanning signal output terminal;

the gate of the sixth transistor is electrically connected to the second node, one of the source or the drain of the sixth transistor is electrically connected to the first node, and the other of the source or the drain of the sixth transistor is electrically connected to the first level signal terminal.

5. The gate driving circuit of claim 4, wherein the pull-down module further comprises a seventh transistor;

the gate of the seventh transistor is electrically connected to the next-stage scanning signal input terminal, one of the source or the drain of the seventh transistor is electrically connected to the second level signal terminal, and the other of the source or the drain of the seventh transistor is electrically connected to the second node.

6. A gate drive circuit as claimed in claim 4, wherein the pull-down module further comprises a seventh transistor;

a gate of the seventh transistor is electrically connected to the next-stage scan signal input terminal, one of a source or a drain of the seventh transistor is electrically connected to the next-stage scan signal input terminal, and the other of the source or the drain of the seventh transistor is electrically connected to the second node.

7. A gate drive circuit as claimed in claim 1, wherein the gate drive unit of each stage further comprises an eighth transistor;

the grid electrode of the eighth transistor is electrically connected to the switch control signal end; one of the source or the drain of the eighth transistor is electrically connected to the current-stage scanning signal output terminal, and the other of the source or the drain of the eighth transistor is electrically connected to the first level signal terminal.

8. A gate drive circuit as claimed in claim 1, wherein the gate drive unit of each stage further comprises an eighth transistor;

a gate of the eighth transistor is electrically connected to the first clock signal terminal; one of the source or the drain of the eighth transistor is electrically connected to the current-stage scanning signal output terminal, and the other of the source or the drain of the eighth transistor is electrically connected to the first level signal terminal.

9. The gate driving circuit according to claim 1, comprising a first clock signal line and a start signal line;

the first clock signal line is electrically connected with the first clock signal end of each stage of the grid driving unit;

the starting signal line is electrically connected with the last scanning signal input end of the first-stage grid driving unit;

the scanning signal output end of the grid driving unit at each stage is electrically connected with the scanning line and the scanning signal input end of the grid driving unit at the previous stage.

10. The gate driving circuit according to claim 1, comprising a first clock signal line and a start signal line;

the first clock signal line is electrically connected with the first clock signal end of each stage of the grid driving unit;

the starting signal line is electrically connected with the last scanning signal input end of the first-stage grid driving unit;

the scanning signal output end of the grid driving unit at each stage is respectively and electrically connected with a scanning line and the scanning signal input end of the previous stage of the grid driving unit at the next stage;

and the next-stage scanning signal input end of the grid driving unit at each stage is electrically connected with the current-stage scanning signal output end of the grid driving unit at the next stage.

11. A gate drive circuit as claimed in claim 9 or 10,

the first clock signal line is used for transmitting a first clock signal to the gate driving unit of the first stage, and the starting signal line is used for transmitting a starting signal to the gate driving unit of the first stage;

the pulse width of the start signal is less than or equal to the pulse width of the first clock signal, and the pulse signal of the start signal is within the pulse signal time range of the first clock signal.

12. A display panel comprising the gate driver circuit according to any one of claims 1 to 11.

13. A display device characterized by comprising the display panel according to claim 12.

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