CN114817113B - Method, system, equipment and storage medium for judging SDA data direction - Google Patents

Method, system, equipment and storage medium for judging SDA data direction Download PDF

Info

Publication number
CN114817113B
CN114817113B CN202210476585.9A CN202210476585A CN114817113B CN 114817113 B CN114817113 B CN 114817113B CN 202210476585 A CN202210476585 A CN 202210476585A CN 114817113 B CN114817113 B CN 114817113B
Authority
CN
China
Prior art keywords
value
register
sda
gpio
determining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210476585.9A
Other languages
Chinese (zh)
Other versions
CN114817113A (en
Inventor
张叶梅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Inspur Intelligent Technology Co Ltd
Original Assignee
Suzhou Inspur Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Inspur Intelligent Technology Co Ltd filed Critical Suzhou Inspur Intelligent Technology Co Ltd
Priority to CN202210476585.9A priority Critical patent/CN114817113B/en
Publication of CN114817113A publication Critical patent/CN114817113A/en
Application granted granted Critical
Publication of CN114817113B publication Critical patent/CN114817113B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The invention provides a method, a system, equipment and a storage medium for judging the SDA data direction, wherein the method comprises the following steps: determining a first register value of a next clock signal according to values in a first SDA direction register, a first SDA decoding value register and a first SDA GPIO data reading register in the CPLD of the transmitting terminal; determining a first GPIO value of the CPLD at the transmitting end according to the first register value; determining a second register value of the next clock signal according to values in a second SDA direction register, a second SDA decoding value register and a second SDA GPIO data reading register in the CPLD of the receiving end; determining a second GPIO value of the CPLD according to the second register value; and determining SDA data directions of the transmitting end and the receiving end according to the first GPIO value and the second GPIO value respectively. The invention realizes the judgment of the SDA direction under the condition of saving logic resources and realizes the data transparent transmission.

Description

Method, system, equipment and storage medium for judging SDA data direction
Technical Field
The present invention relates to the field of data transmission, and more particularly, to a method, system, device, and storage medium for determining SDA data direction.
Background
In the application environment of long-distance transmission, SCL and SDA of the I2C bus and other signal lines are transmitted, because the limited communication data transmission distance is limited, and the actual transmission requirement cannot be met, optical fiber transmission is needed, the TX CPLD encodes SCL and SDA and other signals into serial signals to transmit through tx_so, the RX CPLD analyzes the data of rx_si, and simultaneously encodes SDA and other signals into serial signals to transmit to the TX CPLD through rx_so, and the TX CPLD analyzes the data of tx_si to obtain signals such as SDA, and the relationship diagram is shown in fig. 1. Unidirectional signal decoding is simple, but the SDA data is bidirectional, requiring a clear direction to resolve correctly. The general idea is to analyze according to the protocol format of the I2C to determine the data direction of the SDA, but due to the limitation of the CPLD model resource applied, stable transmission is difficult under limited resources.
Disclosure of Invention
In view of the above, an object of the embodiments of the present invention is to provide a method, a system, a computer device, and a computer readable storage medium for determining an SDA data direction, where the method of data transparent transmission is not used to analyze an I2C protocol, so that when the SDA and the SCL of the I2C are transmitted, the TX CPLD can stably send an SDA signal to the RX CPLD and a received SDA signal sent by the RX CPLD, and at the same time, the RX CPLD can stably receive the SDA signal sent by the TX CPLD and send the SDA signal to the TX CPLD, thereby implementing the determination of the SDA direction under the condition of saving logic resources.
Based on the above objects, an aspect of the embodiments of the present invention provides a method for determining an SDA data direction, including the steps of: determining a first register value of a next clock signal according to values in a first SDA direction register, a first SDA decoding value register and a first SDA GPIO data reading register in the CPLD of the transmitting terminal; determining a first GPIO value of the CPLD at the transmitting end according to the first register value; determining a second register value of the next clock signal according to values in a second SDA direction register, a second SDA decoding value register and a second SDA GPIO data reading register in the CPLD of the receiving end; determining a second GPIO value of the CPLD according to the second register value; and determining SDA data directions of the transmitting end and the receiving end according to the first GPIO value and the second GPIO value respectively.
In some embodiments, the determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoded value register, and the first SDA GPIO data read register in the sender CPLD includes: and formulating a relation table of the register value and the first register value of the next clock signal, and determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoding value register and the first SDA GPIO data reading register in the relation table.
In some embodiments, the determining the first GPIO value of the sender CPLD from the first register value includes: assigning a high impedance to the first GPIO value in response to the first register value being a first value; and assigning the first GPIO value as the value of the first SDA-decoded value register in response to the first register value being a second value.
In some implementations, the determining the second GPIO value of the receiving CPLD from the second register value includes: assigning the second GPIO value to a value of a second SDA decoded value register in response to the second register value being the first value; and assigning the second GPIO value as a high resistance in response to the second register value being a second value.
In another aspect of the embodiments of the present invention, there is provided a system for determining an SDA data direction, including: the transmitting module is configured to determine a first register value of a next clock signal according to values in a first SDA direction register, a first SDA decoding value register and a first SDA GPIO data reading register in the transmitting terminal CPLD; the first confirming module is configured to confirm a first GPIO value of the CPLD according to the first register value; the receiving module is configured to determine a second register value of the next clock signal according to values in a second SDA direction register, a second SDA decoding value register and a second SDA GPIO data reading register in the receiving terminal CPLD; a second determining module configured to determine a second GPIO value of the receiving terminal CPLD according to the second register value; and a direction module configured to determine SDA data directions of the transmitting end and the receiving end according to the first GPIO value and the second GPIO value, respectively.
In some embodiments, the transmitting module is configured to: and formulating a relation table of the register value and the first register value of the next clock signal, and determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoding value register and the first SDA GPIO data reading register in the relation table.
In some embodiments, the first acknowledgement module is configured to: assigning a high impedance to the first GPIO value in response to the first register value being a first value; and assigning the first GPIO value as the value of the first SDA-decoded value register in response to the first register value being a second value.
In some embodiments, the second determination module is configured to: assigning the second GPIO value to a value of a second SDA decoded value register in response to the second register value being the first value; and assigning the second GPIO value as a high resistance in response to the second register value being a second value.
In yet another aspect of the embodiment of the present invention, there is also provided a computer apparatus, including: at least one processor; and a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method as above.
In yet another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method steps as described above.
The invention has the following beneficial technical effects: the method has the advantages that the SDA signal of the I2C and the SDA signal sent by the received RX CPLD can be stably sent to the RX CPLD by the TX CPLD through the data transmission method without analyzing the I2C protocol, and meanwhile, the SDA signal sent by the TX CPLD and the SDA signal sent to the TX CPLD can be stably received by the RX CPLD, so that the judgment of the SDA direction is realized under the condition of saving logic resources.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a relationship between a transmitting end CPLD and a receiving end CPLD in the prior art;
fig. 2 is a schematic diagram of an embodiment of a method for determining SDA data direction according to the present invention;
fig. 3 is a schematic diagram of an embodiment of a system for determining SDA data direction according to the present invention;
fig. 4 is a schematic hardware structure diagram of an embodiment of a computer device for determining an SDA data direction according to the present invention;
fig. 5 is a schematic diagram of an embodiment of a computer storage medium for determining SDA data direction according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
In a first aspect of the embodiment of the present invention, an embodiment of a method for determining an SDA data direction is provided. Fig. 2 is a schematic diagram of an embodiment of a method for determining SDA data direction according to the present invention. As shown in fig. 2, the embodiment of the present invention includes the following steps:
s1, determining a first register value of a next clock signal according to values in a first SDA direction register, a first SDA decoding value register and a first SDA GPIO data reading register in a CPLD of a transmitting end;
s2, determining a first GPIO value of the CPLD at the transmitting end according to the first register value;
s3, determining a second register value of the next clock signal according to values in a second SDA direction register, a second SDA decoding value register and a second SDA GPIO data reading register in the CPLD of the receiving end;
s4, determining a second GPIO value of the CPLD of the receiving end according to the second register value; and
s5, determining SDA data directions of the sending end and the receiving end according to the first GPIO value and the second GPIO value respectively.
And determining a first register value of the next clock signal according to values in a first SDA direction register, a first SDA decoding value register and a first SDA GPIO data reading register in the CPLD of the transmitting terminal.
In some embodiments, the determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoded value register, and the first SDA GPIO data read register in the sender CPLD includes: and formulating a relation table of the register value and the first register value of the next clock signal, and determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoding value register and the first SDA GPIO data reading register in the relation table.
The SDA direction register of the CPLD (TX CPLD) at the transmitting end is r_tx_sdadir, the SDA decoding value register of the CPLD (RX CPLD) at the receiving end is r_tx_rxsda, and the SDA GPIO data reading register at the TX CPLD end is r_tx_iosda. The register data is judged according to table 1, and the r_tx_sdadir register value of the next clk is obtained by the values of the r_tx_sdadir, r_tx_iosda and r_tx_rxsda registers of the current clk. Where r_tx_sdadir 0 denotes SDA is from TX CPLD to RX CPLD direction, 1 denotes SDA is from RX CPLD to TX CPLD direction, the values 1 of r_tx_iosda and r_tx_rxsda registers denote high level, and 0 denotes low level.
TABLE 1 SDA Direction determination Table for TX CPLD
Figure BDA0003625860400000051
Figure BDA0003625860400000061
And determining a first GPIO value of the CPLD at the transmitting end according to the first register value.
In some embodiments, the determining the first GPIO value of the sender CPLD from the first register value includes: assigning a high impedance to the first GPIO value in response to the first register value being a first value; and assigning the first GPIO value as the value of the first SDA-decoded value register in response to the first register value being a second value.
The first GPIO value tx_gpio_sda (SDA GPIO) on the TX CPLD side is assigned, if r_tx_sdadir is 0, the tx_gpio_sda is assigned with high resistance z, and if r_tx_sdadir is 1, the tx_sgpio_sda is assigned with r_tx_rxsda.
And determining a second register value of the next clock signal according to values in a second SDA direction register, a second SDA decoding value register and a second SDA GPIO data reading register in the receiving end CPLD.
The SDA direction register of the RX CPLD is r_rx_sdadir, the SDA decoding value register of the TX CPLD is r_rx_txsda, and the SDA IO data reading register of the RX CPLD terminal is r_rx_iosda. The register data is judged according to table 2, and the r_rx_sdadir register value of the next clk is obtained from the values of the r_rx_sdadir, r_rx_iosda and r_rx_txsda registers of the current clk. Where r_rx_sdadir 0 denotes SDA is from TX CPLD to RX CPLD direction, 1 denotes SDA is from RX CPLD to TX CPLD direction, the values 1 of r_rx_iosda and r_rx_txsda registers denote high level, and 0 denotes low level.
TABLE 2 SDA Direction determination Table for RX CPLD
Figure BDA0003625860400000062
Figure BDA0003625860400000071
And determining a second GPIO value of the CPLD according to the second register value.
In some implementations, the determining the second GPIO value of the receiving CPLD from the second register value includes: assigning the second GPIO value to a value of a second SDA decoded value register in response to the second register value being the first value; and assigning the second GPIO value as a high resistance in response to the second register value being a second value.
And assigning a second GPIO value RX_GPIO_SDA (SDA GPIO) on the RX CPLD side, assigning r_tx_rxsda to RX_GPIO_SDA if r_rx_sdadir is 0, and assigning high resistance z to SDA GPIO if r_rx_sdadir is 1.
And determining SDA data directions of a transmitting end and a receiving end according to the first GPIO value and the second GPIO value respectively.
It should be noted that, in the foregoing embodiments of the method for determining the SDA data direction, the steps may be intersected, replaced, added and deleted, so that the method for determining the SDA data direction by these reasonable permutation and combination changes should also belong to the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.
Based on the above object, in a second aspect of the embodiment of the present invention, a system for determining an SDA data direction is provided. As shown in fig. 3, the system 200 includes the following modules: the transmitting module is configured to determine a first register value of a next clock signal according to values in a first SDA direction register, a first SDA decoding value register and a first SDA GPIO data reading register in the transmitting terminal CPLD; the first confirming module is configured to confirm a first GPIO value of the CPLD according to the first register value; the receiving module is configured to determine a second register value of the next clock signal according to values in a second SDA direction register, a second SDA decoding value register and a second SDA GPIO data reading register in the receiving terminal CPLD; a second determining module configured to determine a second GPIO value of the receiving terminal CPLD according to the second register value; and a direction module configured to determine SDA data directions of the transmitting end and the receiving end according to the first GPIO value and the second GPIO value, respectively.
In some embodiments, the transmitting module is configured to: and formulating a relation table of the register value and the first register value of the next clock signal, and determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoding value register and the first SDA GPIO data reading register in the relation table.
In some embodiments, the first acknowledgement module is configured to: assigning a high impedance to the first GPIO value in response to the first register value being a first value; and assigning the first GPIO value as the value of the first SDA-decoded value register in response to the first register value being a second value.
In some embodiments, the second determination module is configured to: assigning the second GPIO value to a value of a second SDA decoded value register in response to the second register value being the first value; and assigning the second GPIO value as a high resistance in response to the second register value being a second value.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, determining a first register value of a next clock signal according to values in a first SDA direction register, a first SDA decoding value register and a first SDA GPIO data reading register in a CPLD of a transmitting end; s2, determining a first GPIO value of the CPLD at the transmitting end according to the first register value; s3, determining a second register value of the next clock signal according to values in a second SDA direction register, a second SDA decoding value register and a second SDA GPIO data reading register in the CPLD of the receiving end; s4, determining a second GPIO value of the CPLD of the receiving end according to the second register value; and S5, determining SDA data directions of the sending end and the receiving end according to the first GPIO value and the second GPIO value respectively.
In some embodiments, the determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoded value register, and the first SDA GPIO data read register in the sender CPLD includes: and formulating a relation table of the register value and the first register value of the next clock signal, and determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoding value register and the first SDA GPIO data reading register in the relation table.
In some embodiments, the determining the first GPIO value of the sender CPLD from the first register value includes: assigning a high impedance to the first GPIO value in response to the first register value being a first value; and assigning the first GPIO value as the value of the first SDA-decoded value register in response to the first register value being a second value.
In some implementations, the determining the second GPIO value of the receiving CPLD from the second register value includes: assigning the second GPIO value to a value of a second SDA decoded value register in response to the second register value being the first value; and assigning the second GPIO value as a high resistance in response to the second register value being a second value.
As shown in fig. 4, a hardware structure diagram of an embodiment of the computer device for determining an SDA data direction according to the present invention is provided.
Taking the example of the apparatus shown in fig. 4, a processor 301 and a memory 302 are included in the apparatus.
The processor 301 and the memory 302 may be connected by a bus or otherwise, for example in fig. 4.
The memory 302 is used as a non-volatile computer readable storage medium, and may be used to store a non-volatile software program, a non-volatile computer executable program, and a module, such as program instructions/modules corresponding to a method for determining an SDA data direction in the embodiments of the present application. The processor 301 executes various functional applications of the server and data processing, i.e., implements a method for determining the SDA data direction, by running non-volatile software programs, instructions, and modules stored in the memory 302.
Memory 302 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the data storage area may store data created according to the use of the method for judging the SDA data direction, etc. In addition, memory 302 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 302 may optionally include memory located remotely from processor 301, which may be connected to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more computer instructions 303 corresponding to a method for determining an SDA data direction are stored in the memory 302, which when executed by the processor 301, perform the method for determining an SDA data direction in any of the method embodiments described above.
Any one of the embodiments of the computer device that performs the method for determining the direction of SDA data described above may achieve the same or similar effects as any of the embodiments of the method described above that correspond thereto.
The present invention also provides a computer readable storage medium storing a computer program which when executed by a processor performs a method for determining SDA data direction.
Fig. 5 is a schematic diagram of an embodiment of the above-mentioned computer storage medium for determining SDA data direction according to the present invention. Taking a computer storage medium as shown in fig. 5 as an example, the computer readable storage medium 401 stores a computer program 402 that when executed by a processor performs the above method.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the embodiments described above may be implemented by a computer program to instruct related hardware, and the program for determining the SDA data direction may be stored in a computer readable storage medium, where the program when executed may include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.

Claims (8)

1. A method for determining SDA data direction, comprising the steps of:
determining a first register value of a next clock signal according to values in a first SDA direction register, a first SDA decoding value register and a first SDA GPIO data reading register in the CPLD of the transmitting terminal;
determining a first GPIO value of the CPLD at the transmitting end according to the first register value;
determining a second register value of the next clock signal according to values in a second SDA direction register, a second SDA decoding value register and a second SDA GPIO data reading register in the CPLD of the receiving end;
determining a second GPIO value of the CPLD according to the second register value; and
determining SDA data directions of a transmitting end and a receiving end according to the first GPIO value and the second GPIO value respectively,
the determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoding value register, and the first SDA GPIO data reading register in the transmitting terminal CPLD includes:
and formulating a relation table of the register value and the first register value of the next clock signal, and determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoding value register and the first SDA GPIO data reading register in the relation table.
2. The method according to claim 1, wherein said determining a first GPIO value of the sender CPLD from the first register value comprises:
assigning a high impedance to the first GPIO value in response to the first register value being a first value; and
and assigning the first GPIO value as the value of the first SDA decoded value register in response to the first register value being a second value.
3. The method according to claim 1, wherein said determining a second GPIO value of the receiving CPLD from the second register value comprises:
assigning the second GPIO value to the value of a second SDA decoded value register in response to the second register value being the first value,
and assigning the second GPIO value as a high resistance in response to the second register value being a second value.
4. A system for determining SDA data direction, comprising:
the transmitting module is configured to determine a first register value of a next clock signal according to values in a first SDA direction register, a first SDA decoding value register and a first SDA GPIO data reading register in the transmitting terminal CPLD;
the first confirming module is configured to confirm a first GPIO value of the CPLD according to the first register value;
the receiving module is configured to determine a second register value of the next clock signal according to values in a second SDA direction register, a second SDA decoding value register and a second SDA GPIO data reading register in the receiving terminal CPLD;
a second determining module configured to determine a second GPIO value of the receiving terminal CPLD according to the second register value; and
a direction module configured to determine SDA data directions of the transmitting end and the receiving end according to the first GPIO value and the second GPIO value, respectively,
the sending module is configured to:
and formulating a relation table of the register value and the first register value of the next clock signal, and determining the first register value of the next clock signal according to the values in the first SDA direction register, the first SDA decoding value register and the first SDA GPIO data reading register in the relation table.
5. The system of claim 4, wherein the first acknowledgement module is configured to:
assigning a high impedance to the first GPIO value in response to the first register value being a first value; and
and assigning the first GPIO value as the value of the first SDA decoded value register in response to the first register value being a second value.
6. The system of claim 4, wherein the second determination module is configured to:
assigning the second GPIO value to a value of a second SDA decoded value register in response to the second register value being the first value;
and assigning the second GPIO value as a high resistance in response to the second register value being a second value.
7. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, which instructions when executed by the processor implement the steps of the method of any one of claims 1-3.
8. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of any of claims 1-3.
CN202210476585.9A 2022-04-30 2022-04-30 Method, system, equipment and storage medium for judging SDA data direction Active CN114817113B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210476585.9A CN114817113B (en) 2022-04-30 2022-04-30 Method, system, equipment and storage medium for judging SDA data direction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210476585.9A CN114817113B (en) 2022-04-30 2022-04-30 Method, system, equipment and storage medium for judging SDA data direction

Publications (2)

Publication Number Publication Date
CN114817113A CN114817113A (en) 2022-07-29
CN114817113B true CN114817113B (en) 2023-07-14

Family

ID=82511836

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210476585.9A Active CN114817113B (en) 2022-04-30 2022-04-30 Method, system, equipment and storage medium for judging SDA data direction

Country Status (1)

Country Link
CN (1) CN114817113B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101763331A (en) * 2010-01-18 2010-06-30 中兴通讯股份有限公司 System and method for realizing I2C bus control
CN106649180A (en) * 2016-09-09 2017-05-10 锐捷网络股份有限公司 Method and device for relieving I2C bus deadlock
CN109460378A (en) * 2018-10-30 2019-03-12 新华三信息安全技术有限公司 A kind of interface circuit, signal processing method, device and medium

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070240011A1 (en) * 2006-04-05 2007-10-11 Texas Instruments Incorporated FIFO memory data pipelining system and method for increasing I²C bus speed

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101763331A (en) * 2010-01-18 2010-06-30 中兴通讯股份有限公司 System and method for realizing I2C bus control
CN106649180A (en) * 2016-09-09 2017-05-10 锐捷网络股份有限公司 Method and device for relieving I2C bus deadlock
CN109460378A (en) * 2018-10-30 2019-03-12 新华三信息安全技术有限公司 A kind of interface circuit, signal processing method, device and medium

Also Published As

Publication number Publication date
CN114817113A (en) 2022-07-29

Similar Documents

Publication Publication Date Title
CN104468363A (en) Page redirection method, page redirection system, router equipment and terminal equipment
CN112218339B (en) Relay transmission scheduling method, device, storage medium and electronic equipment
CN114826542B (en) Data transmission method, device, equipment and medium based on asynchronous serial communication
CN114039703A (en) Data transmission method, device, equipment and medium
CN114817113B (en) Method, system, equipment and storage medium for judging SDA data direction
CN113726592A (en) Transmission delay testing method and system of edge server and related components
CN112422485B (en) Communication method and device of transmission control protocol
CN115150795A (en) Information filtering method, bluetooth antenna and Internet of things data platform
CN109639555B (en) Link layer message generation method, link layer message generation device and terminal equipment
CN114443537B (en) PCIE signal transmitting end parameter configuration method, device, equipment and medium
CN111541958A (en) Optical interface rate self-adaption method, equipment, device and readable storage medium
CN113490154B (en) Broadcast data transmission method, device, terminal equipment and storage medium
CN114337942B (en) Message retransmission method and device and electronic equipment
US20230246730A1 (en) Data transmission method and apparatus, circuit board, storage medium and electronic apparatus
CN102545953B (en) UART (Universal Asynchronous Receiver/Transmitter) function extension circuit and control method thereof
CN113411102A (en) Data transmission method, device and system
CN211956465U (en) TTL and RS232 support double-level serial port extension circuit
CN114138063B (en) CPLD-based transmission method and device for reducing connector signals
CN112165465B (en) Data processing method and device for outgoing third-party platform and electronic device
CN116226027B (en) Data transmission system, method, device, communication equipment and storage medium
CN209949149U (en) Distribution network signal transmission device
CN114513523B (en) Data synchronization method, device, equipment and storage medium
CN112834964B (en) Detection method, device and equipment for wiring line sequence of self-adaptive combiner
CN112838972B (en) Enabling control method, device and equipment based on RS-485 transceiver and storage medium
CN103605622B (en) A kind of method and apparatus transmitting data

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant