CN114817070A - Server power software parameter debugging method, system, terminal and storage medium - Google Patents
Server power software parameter debugging method, system, terminal and storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of servers, in particular to a method, a system, a terminal and a storage medium for debugging parameters of server power software, wherein the method comprises the following steps: acquiring test data from server power supply test equipment; analyzing the test data to obtain abnormal data items; and debugging the software parameter item corresponding to the abnormal data item in a stepping mode according to the standard software parameter file until the abnormal data item is in an abnormal state. According to the invention, the software parameters do not need to be debugged manually, the whole process does not need manual participation, and the debugging efficiency of the software parameters is greatly improved through a scientific parameter adjusting range and a scientific parameter adjusting mode.
Description
Technical Field
The invention belongs to the technical field of servers, and particularly relates to a server power software parameter debugging method, a system, a terminal and a storage medium.
Background
In the development stage of the server mainboard, a targeted test needs to be performed on core power supply modules VCCIN, VCCSA, VCCIO and the like related to CPU power supply. The method comprises the following steps: dynamic response test, DVID test, jitter, Bott diagram test, etc. In the development process, VR CODE debugging (that is, VR CODE is a software parameter which can be solidified inside a VR chip) is required aiming at the condition of the occurring test fail so as to reach the design standard and leave a certain margin, and the performance of a feedback loop can be improved by adjusting the register parameter of the feedback loop.
At present, VR CODE is debugged mainly by means of experience accumulation of power supply engineers and referential documents given by manufacturers, and parameter collocation meeting spec is obtained through continuous manual trial and error. The debugging method needs too much time and energy, the manual trial and error efficiency is too low, and a scientific and efficient system debugging method is lacked. And the referential documents given by manufacturers are too strong in referential property and too low in practicality, and often cannot be used as standards, and hardware engineers are still required to spend a lot of time for trial and error depending on experience. In addition, mechanical retest of fixed test items is required after each parameter adjustment, and a great space for improving the test efficiency exists.
Disclosure of Invention
Aiming at the problem of low debugging efficiency caused by manual debugging in the prior art, the invention provides a server power supply software parameter debugging method, a system, a terminal and a storage medium, so as to solve the technical problem.
In a first aspect, the present invention provides a method for debugging parameters of server power software, including:
acquiring test data from server power supply test equipment;
analyzing the test data to obtain abnormal data items;
and debugging the software parameter item corresponding to the abnormal data item in a stepping mode according to the standard software parameter file until the abnormal data item is in an abnormal state.
Further, acquiring test data from the server power supply test device includes:
the control oscilloscope and the frequency response analyzer are connected through a universal interface bus;
test data is collected in real time from the control oscilloscope and frequency response analysis during the test tool performing the test.
Further, collecting test data in real time from the control oscilloscope and the frequency response analysis during the test tool performing the test includes:
reading DROOP and OVERSHOOT values of voltage when large-span current is drawn from an oscilloscope, calculating active parameters and passive parameters with manually filled END and START values, and evaluating the active parameters and the passive parameters by using a standard performance evaluation file;
reading the minimum voltage value of 4us-25us on an oscilloscope, comparing the minimum voltage value with corresponding standard data of a standard performance evaluation file, and judging whether the test is passed or not and the size of the margin;
capturing the waveform of the vibration test on an oscilloscope, calculating a vibration test value by automatically measuring the waveform jitter width, and comparing the vibration test value with corresponding standard data of a standard performance evaluation file to judge whether the test is passed;
and (3) capturing waveforms of 10%, 50% and 100% of the tensile load of the frequency response analyzer, reading corresponding stage values and edge values, comparing the corresponding stage values and edge values with corresponding standard data of a standard performance evaluation file, and judging whether the test is passed or not.
Further, analyzing the test data to obtain an abnormal data item, including:
comparing the test data with a pre-stored standard performance evaluation file, and judging whether the test data completely meets the requirements of the standard performance evaluation file:
if yes, judging that all tests pass;
if not, outputting the test data item which does not meet the requirements of the standard performance evaluation file as an abnormal data item.
Further, debugging the software parameter item corresponding to the abnormal data item in a stepping manner according to the standard software parameter file until the abnormal data item is in an abnormal state, including:
presetting software parameter items corresponding to the test data items in a standard software parameter file, and respectively setting a standard array for each software parameter item, wherein the standard array comprises a series of standard parameters arranged according to the numerical value;
screening software parameter items corresponding to the abnormal data items, taking the corresponding software parameter items as target parameter items and outputting standard arrays of the target parameter items as object arrays;
sorting the standard parameters in the object array according to the absolute value of the difference value between the standard parameters and the actual parameters of the target parameter item;
writing the standard parameters in the object array into the target parameter items in sequence according to the sequence;
and after the parameter value of the target parameter item is changed each time, acquiring the test data again and analyzing whether an abnormal data item exists:
if so, continuously replacing the parameter value of the target parameter item;
if not, taking the current parameter value of the target parameter item as the optimal parameter value, and stopping replacing the parameter value of the target parameter item.
In a second aspect, the present invention provides a server power software parameter debugging system, including:
the data acquisition unit is used for acquiring test data from the server power supply test equipment;
the test analysis unit is used for analyzing the test data to obtain abnormal data items;
and the parameter adjusting unit is used for debugging the software parameter item corresponding to the abnormal data item in a stepping mode according to the standard software parameter file until the abnormal data item is in an abnormal state.
Further, the data acquisition unit includes:
the equipment connection module is used for connecting the control oscilloscope and the frequency response analyzer through the universal interface bus;
and the data acquisition module is used for acquiring test data in real time from the control oscilloscope and the frequency response analysis during the test tool executing test.
Further, the test analysis unit includes:
the test judgment module is used for comparing the test data with a pre-stored standard performance evaluation file and judging whether the test data completely meets the requirement of the standard performance evaluation file;
the pass judgment module is used for judging that all tests pass if all the test data meet the requirements of the standard performance evaluation file;
and the abnormal output module is used for outputting the test data item which does not meet the requirement of the standard performance evaluation file as an abnormal data item if the test data does not meet the requirement of the standard performance evaluation file.
Further, the parameter adjusting unit is further configured to:
presetting software parameter items corresponding to the test data items in a standard software parameter file, and respectively setting a standard array for each software parameter item, wherein the standard array comprises a series of standard parameters arranged according to the numerical value;
screening software parameter items corresponding to the abnormal data items, taking the corresponding software parameter items as target parameter items and outputting standard arrays of the target parameter items as object arrays;
sorting the standard parameters in the object array according to the absolute value of the difference value between the standard parameters and the actual parameters of the target parameter item;
writing the standard parameters in the object array into the target parameter items in sequence according to the sequence;
and after the parameter value of the target parameter item is changed each time, acquiring the test data again and analyzing whether an abnormal data item exists:
if so, continuously replacing the parameter value of the target parameter item;
if not, taking the current parameter value of the target parameter item as the optimal parameter value, and stopping replacing the parameter value of the target parameter item.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The method, the system, the terminal and the storage medium for debugging the power supply software parameters of the server have the advantages that the test data are directly obtained by butting the test equipment, the test data are subjected to abnormity analysis, and the software parameter items corresponding to the abnormal data items are debugged in a stepping mode according to the analysis result and based on the preset standard software parameter file. According to the invention, the software parameters do not need to be debugged manually, the whole process does not need manual participation, and the debugging efficiency of the software parameters is greatly improved through a scientific parameter adjusting range and a scientific parameter adjusting mode.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
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In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution subject in fig. 1 may be a server power software parameter debugging system.
As shown in fig. 1, the method includes:
In order to facilitate understanding of the present invention, the server power software parameter debugging method provided by the present invention is further described below with reference to the principle of the server power software parameter debugging method of the present invention and the process of debugging the server power software parameters in the embodiments.
Specifically, the server power software parameter debugging method includes:
and S1, acquiring the test data from the server power supply test equipment.
The control oscilloscope and the frequency response analyzer are connected through a universal interface bus; test data is collected in real time from the control oscilloscope and frequency response analysis during the test tool performing the test. Wherein the test data comprises: transient test data, bode plot, and jitter test data.
In order to improve VR CODE debugging efficiency and accuracy in the power research and development stage, an upper computer system is adopted for control in the embodiment, and a Python script is used for realizing an automatic debugging process.
The upper computer controls the power-on sequence of the VRTT fixture and the mainboard to be tested through the control single chip microcomputer and the relay, the VRTT fixture is powered on at first, and then the mainboard is powered on, so that damage to the fixture caused by errors of the power-on sequence is avoided.
GUI and mainboard connection, the host computer passes through Python script control VRTT tool and draws and carry. Meanwhile, a GPIB wire is used for connecting the control oscilloscope and the frequency response analyzer to test the Transient, the DVID, the baud chart and the jitter. And (5) capturing test data from the oscilloscope. Specifically, after condition parameters are set in a Python script, a single chip microcomputer and a relay are controlled to be powered on, a Tool is controlled to carry out pulling load, each graph on an oscilloscope is accumulated for 100 times and then the numerical value is read, and a frequency response analyzer is set according to the convention.
And S2, analyzing the test data to obtain abnormal data items.
Comparing the test data with a pre-stored standard performance evaluation file, and judging whether the test data completely meets the requirements of the standard performance evaluation file: if yes, judging that all tests pass; if not, outputting the test data item which does not meet the requirements of the standard performance evaluation file as an abnormal data item.
Specifically, the test results are compared to SPEC (standard performance evaluation document, available from the manufacturer). And when the result does not meet the spec requirement, calling a GUI tool and corresponding debugging software to adjust and optimize. For example: the DROOP (descending value) and OVERSHOOT (exceeding value) of the voltage when the large-span current is pulled can be read from an oscilloscope, Positive parameters and Negative parameters are calculated with the END (ending value) and START (starting value) which are filled manually, and the comparison with spec is carried out to judge whether pass exists and the allowance. On an oscilloscope, the voltage minimum (minimum) of 4us-25us can be read, compared with spec to judge whether pass exists or not and the size of the margin. The waveform of the jitter (vibration test) is captured on an oscilloscope, the jitter width of the waveform is automatically measured to calculate the test value of the jitter, and the test value is compared with the spec to judge whether pass exists. And (3) capturing the waveform when the frequency response analyzer is loaded by 10%, 50% and 100%, reading the corresponding Phase (Phase value) and Margin (edge value), comparing the Phase (Phase value) and Margin (edge value) with spec, and judging whether pass exists or not. And finally, summarizing the data tested under different codes into a table, and leading in a scheme with pass and reasonable margin left by a tester.
And S3, debugging the software parameter item corresponding to the abnormal data item in a stepping mode according to the standard software parameter file until the abnormal data item is in an abnormal state.
Presetting software parameter items corresponding to the test data items in a standard software parameter file, and respectively setting a standard array for each software parameter item, wherein the standard array comprises a series of standard parameters arranged according to the numerical value; screening software parameter items corresponding to the abnormal data items, taking the corresponding software parameter items as target parameter items and outputting standard arrays of the target parameter items as object arrays; sorting the standard parameters in the object array according to the absolute value of the difference value between the standard parameters and the actual parameters of the target parameter item; writing the standard parameters in the object array into the target parameter items in sequence according to the sequence; and after the parameter value of the target parameter item is changed each time, acquiring the test data again and analyzing whether an abnormal data item exists: if so, continuously replacing the parameter value of the target parameter item; if not, taking the current parameter value of the target parameter item as the optimal parameter value, and stopping replacing the parameter value of the target parameter item.
Specifically, software parameter items corresponding to the test data items are preset in a standard software parameter file, and standard arrays are respectively set for the software parameter items. For example: and j iterfail automatically adjusts the Ramp compensation value of the register, and the drop is too small or the overthot is too large. And adjusting the values of the register ramp and the integration gain when the ACLL is adjusted at a high frequency, the DCLL is adjusted at a low frequency, and the phase margin of the baud chart is insufficient. Taking the Ramp compensation value as an example, a standard array is set according to the summary of the multiple times of historical test data in advance, the standard array comprises multiple standard Ramp compensation values [ k1, k2, k3], and the jitter test is pass when the standard Ramp compensation values are written.
And comparing all the test items after the test with the spec, generating final test data if the test items meet the requirements, finishing debugging, calling corresponding chip debugging software to adjust the SVID parameters if the test items do not meet the spec requirements, and capturing all the test item data again after the adjustment to finally obtain the SVID parameters and the test data which are successfully debugged. Taking the jitter test item as an example, assuming that the jitter test fails, the current Ramp compensation value is k0, and the absolute value of the difference between k0 and k1 is the minimum, therefore, k1 is written into the Ramp compensation value register first, the jitter test data is obtained again, whether the jitter test fails or not is judged, if the test succeeds, the Ramp compensation value register is not modified, and if the test fails, k2 is written into the Ramp compensation value register. And in analogy, debugging corresponding to other test items is also performed. In addition, after one test, the condition that a plurality of test items are abnormal may exist, and corresponding software parameter items are debugged by the same method, a plurality of software parameter items can be simultaneously modified by one debugging, the target value of the modified software parameter item can be written into a debugging scheme firstly, and then parameter value adjustment is carried out on the target software parameter item according to the debugging scheme.
As shown in fig. 2, the system 200 includes:
a data acquisition unit 210 for acquiring test data from the server power supply test device;
a test analysis unit 220, configured to analyze the test data to obtain an abnormal data item;
and the parameter adjusting unit 230 is configured to debug the software parameter item corresponding to the abnormal data item in a stepping manner according to the standard software parameter file until the abnormal data item is in an abnormal state.
Optionally, as an embodiment of the present invention, the data obtaining unit includes:
the equipment connection module is used for connecting the control oscilloscope and the frequency response analyzer through the universal interface bus;
and the data acquisition module is used for acquiring test data in real time from the control oscilloscope and the frequency response analysis during the test tool executing test.
Optionally, as an embodiment of the present invention, the test analysis unit includes:
the test judgment module is used for comparing the test data with a pre-stored standard performance evaluation file and judging whether the test data completely meets the requirement of the standard performance evaluation file;
the pass judgment module is used for judging that all tests pass if all the test data meet the requirements of the standard performance evaluation file;
and the abnormal output module is used for outputting the test data item which does not meet the requirement of the standard performance evaluation file as an abnormal data item if the test data does not meet the requirement of the standard performance evaluation file.
Optionally, as an embodiment of the present invention, the parameter adjusting unit is further configured to:
presetting software parameter items corresponding to the test data items in a standard software parameter file, and respectively setting a standard array for each software parameter item, wherein the standard array comprises a series of standard parameters arranged according to the numerical value;
screening software parameter items corresponding to the abnormal data items, taking the corresponding software parameter items as target parameter items and outputting standard arrays of the target parameter items as object arrays;
sorting the standard parameters in the object array according to the absolute value of the difference value between the standard parameters and the actual parameters of the target parameter item;
writing the standard parameters in the object array into the target parameter items in sequence according to the sequence;
and after the parameter value of the target parameter item is changed each time, acquiring the test data again and analyzing whether an abnormal data item exists:
if so, continuously replacing the parameter value of the target parameter item;
if not, taking the current parameter value of the target parameter item as the optimal parameter value, and stopping replacing the parameter value of the target parameter item.
Fig. 3 is a schematic structural diagram of a terminal 300 according to an embodiment of the present invention, where the terminal 300 may be used to execute a server power software parameter debugging method according to the embodiment of the present invention.
Among them, the terminal 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the invention directly obtains the test data by butting the test equipment, performs exception analysis on the test data, and debugs the software parameter item corresponding to the exception data item in a stepping mode according to the analysis result and based on the preset standard software parameter file. According to the method, the software parameters do not need to be debugged manually, manual participation is not needed in the whole process, the debugging efficiency of the software parameters is greatly improved through a scientific parameter adjusting range and a scientific parameter adjusting mode, the technical effect achieved by the embodiment can be seen in the description above, and the details are not repeated here.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail in connection with the preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for debugging parameters of server power software is characterized by comprising the following steps:
acquiring test data from server power supply test equipment;
analyzing the test data to obtain abnormal data items;
and debugging the software parameter item corresponding to the abnormal data item in a stepping mode according to the standard software parameter file until the abnormal data item is in an abnormal state.
2. The method of claim 1, wherein obtaining test data from a server power supply test device comprises:
the control oscilloscope and the frequency response analyzer are connected through a universal interface bus;
test data is collected in real time from the control oscilloscope and frequency response analysis during the test tool performing the test.
3. The method of claim 2, wherein collecting test data in real time from the control oscilloscope and the frequency response analysis during the test tool performing the test comprises:
reading a voltage drop value and an overtake value when the large-span current is drawn from an oscilloscope, calculating an active parameter and a passive parameter with a manually filled finish value and a start value, and evaluating the active parameter and the passive parameter by using a standard performance evaluation file;
reading the minimum voltage value of 4us-25us on an oscilloscope, comparing the minimum voltage value with corresponding standard data of a standard performance evaluation file, and judging whether the test is passed or not and the size of the margin;
capturing the waveform of the vibration test on an oscilloscope, calculating a vibration test value by automatically measuring the waveform jitter width, and comparing the vibration test value with corresponding standard data of a standard performance evaluation file to judge whether the test is passed;
and (3) capturing waveforms of 10%, 50% and 100% of the tensile load of the frequency response analyzer, reading corresponding stage values and edge values, comparing the corresponding stage values and edge values with corresponding standard data of a standard performance evaluation file, and judging whether the test is passed or not.
4. The method of claim 1, wherein analyzing the test data for anomalous data items comprises:
comparing the test data with a pre-stored standard performance evaluation file, and judging whether the test data completely meets the requirements of the standard performance evaluation file:
if yes, judging that all tests pass;
if not, outputting the test data item which does not meet the requirements of the standard performance evaluation file as an abnormal data item.
5. The method of claim 1, wherein debugging the software parameter item corresponding to the abnormal data item in a stepping manner according to a standard software parameter file until the abnormal data item is in an abnormal state, comprises:
presetting software parameter items corresponding to the test data items in a standard software parameter file, and respectively setting a standard array for each software parameter item, wherein the standard array comprises a series of standard parameters arranged according to the numerical value;
screening software parameter items corresponding to the abnormal data items, taking the corresponding software parameter items as target parameter items and outputting standard arrays of the target parameter items as object arrays;
sorting the standard parameters in the object array according to the absolute value of the difference value between the standard parameters and the actual parameters of the target parameter item;
writing the standard parameters in the object array into the target parameter items in sequence according to the sequence;
and after the parameter value of the target parameter item is changed each time, acquiring the test data again and analyzing whether an abnormal data item exists:
if so, continuously replacing the parameter value of the target parameter item;
if not, taking the current parameter value of the target parameter item as the optimal parameter value, and stopping replacing the parameter value of the target parameter item.
6. A server power software parameter debugging system, comprising:
the data acquisition unit is used for acquiring test data from the server power supply test equipment;
the test analysis unit is used for analyzing the test data to obtain abnormal data items;
and the parameter adjusting unit is used for debugging the software parameter item corresponding to the abnormal data item in a stepping mode according to the standard software parameter file until the abnormal data item is in an abnormal state.
7. The system of claim 6, wherein the data acquisition unit comprises:
the equipment connection module is used for connecting the control oscilloscope and the frequency response analyzer through a universal interface bus;
and the data acquisition module is used for acquiring test data in real time from the control oscilloscope and the frequency response analysis during the test tool executing test.
8. The system of claim 6, wherein the test analysis unit comprises:
the test judgment module is used for comparing the test data with a pre-stored standard performance evaluation file and judging whether the test data completely meets the requirement of the standard performance evaluation file;
the pass judgment module is used for judging that all tests pass if all the test data meet the requirements of the standard performance evaluation file;
and the abnormal output module is used for outputting the test data item which does not meet the requirement of the standard performance evaluation file as an abnormal data item if the test data does not meet the requirement of the standard performance evaluation file.
9. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any one of claims 1-5.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-5.
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| CN117171054A (en) * | 2023-11-01 | 2023-12-05 | 深圳市好盈科技股份有限公司 | Processing method and device based on communication between upper computer and lower computer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117171054A (en) * | 2023-11-01 | 2023-12-05 | 深圳市好盈科技股份有限公司 | Processing method and device based on communication between upper computer and lower computer |
| CN117171054B (en) * | 2023-11-01 | 2024-03-08 | 深圳市好盈科技股份有限公司 | Processing method and device based on communication between upper computer and lower computer |
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