CN114816566B - Instruction moving method, system, equipment and medium - Google Patents
Instruction moving method, system, equipment and medium Download PDFInfo
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
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Abstract
The invention discloses an instruction moving method, which comprises the following steps: responding to a received request issued by a host to an IO, and updating first pointer information in a corresponding task according to address parameters of instructions carried in the request; detecting whether the first pointer information in each task reaches a preset value or not; setting a first mark and a second mark of a corresponding task in response to detecting that the first pointer information reaches a preset value; responding to the detection that a first mark is set and a second mark of other tasks is not set currently, and moving corresponding continuous instructions according to the first pointer information; and restoring the set first mark and the set second mark in response to the continuous instruction movement completion. The invention also discloses a system, computer equipment and a readable storage medium. Compared with the traditional single instruction moving, the scheme provided by the invention has higher bus efficiency, and the performance is obviously improved in the program with good space locality.
Description
Technical Field
The present invention relates to the field of data processing, and in particular, to a method, a system, an apparatus, and a storage medium for moving instructions.
Background
With the popularization of cloud computing and big data, computing and storage are becoming more and more critical paths restricting the development of computing technology. For computing systems, the CPU becomes an intermediate node because both data computation and movement are handled by the CPU. With the increase of the application data volume of the system, the load of the CPU is higher and higher. In order to solve the problem, the data calculation is moved from the CPU to a special processing unit, so that the load of the CPU is greatly reduced, and the efficiency is greatly improved. The AEM (acceleration engine management) is a device that relays operations such as data calculation, and returns to a processing unit of a host computer after completion of calculation processing.
As shown in fig. 1, conventional processing is scheduled by firmware. The firmware needs to acquire the instruction issued by the host, analyze the instruction, and then transmit the instruction to the corresponding computing processing unit for processing, and the hardware processing completion notification firmware returns the replied data to the host.
This way of processing consumes excessive CPU processing time, taking up the CPU load. In order to relieve the load of the CPU, a part of data processing tasks of the CPU can be transferred to the accelerator card for processing by using a hardware accelerator card, so that the pressure of the CPU is greatly relieved. A processing manner using AEM (acceleration engine management) is shown in fig. 2. The AEM (acceleration engine management) needs to move the instruction issued by the host to the local for processing. The AEM sequentially moves down the instructions created by the host and then processes the instructions. The processing mode can only move one instruction at a time, the bus access times are more, and the efficiency is lower.
The single instruction moving mode is simple and easy to realize, but has limited efficiency and low bus utilization rate. The host maintains a buffer and a set doorbell of registers. The Doorbell register is used to identify the pointer location of the buffer and to inform the host of the execution status of the instruction. The register set mainly consists of 3 registers: 1. tail pointer: the method comprises the steps of issuing an instruction; 2. head pointer: for indicating the completion of the instruction. 3. Processing pointers: for indicating the processing of the hardware instructions. The specific execution flow is as follows:
1. The host side issues instructions, places the instructions in the host side memory space, and configures doorbell registers to notify the AEM that instructions are issued. If doorbell registers are configured as 10, this means that there are 10 instructions on the host side to execute.
AEM requests PCIE DMA (Direct Memory Access ). Since a single instruction moving mode is adopted, 10 operations are required for moving 10 instructions, and 10 bus operations are initiated. The hardware maintains a processing pointer, which is updated every time a bus operation is initiated.
3. Waiting for the host side instructions to move into the local memory space. The corresponding head pointer is updated after the bus responds and moves the instruction issued by the corresponding host side into the local. The final head-to-tail pointer coincidence indicates that the instructions issued by the host have all been moved by the AEM.
Therefore, when 10 instructions issued by the host require 10 DMA operations, the number of bus accesses is 10, and the bus utilization is low.
Disclosure of Invention
In view of this, in order to overcome at least one aspect of the above-mentioned problems, an embodiment of the present invention provides an instruction moving method, including the following steps:
Responding to a received request issued by a host to an IO, and updating first pointer information in a corresponding task according to address parameters of instructions carried in the request;
detecting whether the first pointer information in each task reaches a preset value or not;
setting a first mark and a second mark of a corresponding task in response to detecting that the first pointer information reaches a preset value;
Responding to the detection that a first mark is set and a second mark of other tasks is not set currently, and moving corresponding continuous instructions according to the first pointer information;
and restoring the set first mark and the set second mark in response to the continuous instruction movement completion.
In some embodiments, in response to receiving an IO request issued by a host, updating first pointer information in a corresponding task according to an address parameter of an instruction carried in the request, further including:
Judging whether the first pointer information of the corresponding task is empty or not;
and in response to being empty, recording the IO request issuing time and timing.
In some embodiments, the method further comprises:
judging whether a overtime task exists or not according to the fact that the first pointer information in each task does not reach a preset value;
setting a first flag and a second flag of a timeout task in response to the task having the timeout;
Responding to the detection that the first mark is set and the second mark of other tasks is not set currently, and moving corresponding continuous instructions according to the current first pointer information of the overtime task;
and restoring the set first mark and the set second mark of the timeout task in response to the completion of the continuous instruction movement.
In some embodiments, moving the corresponding consecutive instructions according to the first pointer information further comprises:
updating the second pointer information according to the moved instruction;
and determining that the corresponding continuous instruction movement is completed in response to the second pointer information being the same as the first pointer information.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides an instruction moving system, including:
The first updating module is configured to respond to receiving an IO request issued by a host, and update first pointer information in a corresponding task according to address parameters of instructions carried in the request;
The detection module is configured to detect whether the first pointer information in each task reaches a preset value or not;
the setting module is configured to set a first mark and a second mark of a corresponding task in response to detecting that the first pointer information reaches a preset value;
The moving module is configured to respond to the detection that the first mark is set and the second mark of other tasks is not set currently, and move corresponding continuous instructions according to the first pointer information;
And the recovery module is configured to recover the set first mark and the set second mark in response to the completion of the continuous instruction movement.
In some embodiments, the first update module is further configured to:
Judging whether the first pointer information of the corresponding task is empty or not;
and in response to being empty, recording the IO request issuing time and timing.
In some embodiments, the method further comprises a judging module configured to:
judging whether a overtime task exists or not according to the fact that the first pointer information in each task does not reach a preset value;
setting a first flag and a second flag of a timeout task in response to the task having the timeout;
Responding to the detection that the first mark is set and the second mark of other tasks is not set currently, and moving corresponding continuous instructions according to the current first pointer information of the overtime task;
and restoring the set first mark and the set second mark of the timeout task in response to the completion of the continuous instruction movement.
In some embodiments, the movement module is further configured to:
updating the second pointer information according to the moved instruction;
and determining that the corresponding continuous instruction movement is completed in response to the second pointer information being the same as the first pointer information.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
A memory storing a computer program executable on the processor, wherein the processor executes steps of any one of the instruction moving methods described above when the processor executes the program.
Based on the same inventive concept, according to another aspect of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of any one of the instruction moving methods described above.
The invention has one of the following beneficial technical effects: compared with the traditional single instruction moving, the scheme provided by the invention has higher bus efficiency, and the performance is obviously improved in the program with good space locality.
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In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram of a conventional data acceleration process;
FIG. 2 is a schematic diagram of a process using an acceleration engine;
FIG. 3 is a flow chart of an instruction moving method according to an embodiment of the present invention;
FIG. 4 is a block diagram of AEM hardware provided by an embodiment of the invention;
FIG. 5 is a schematic diagram of a bus decoding module according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a task creation module according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a timeout processing module according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of an indexing module according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of an instruction cache module according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of an instruction moving system according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a computer device according to an embodiment of the present invention;
Fig. 12 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
According to one aspect of the present invention, an embodiment of the present invention proposes an instruction moving method, as shown in fig. 3, which may include the steps of:
S1, in response to receiving an IO request issued by a host, updating first pointer information in a corresponding task according to address parameters of an instruction carried in the request;
s2, detecting whether the first pointer information in each task reaches a preset value or not;
s3, setting a first mark and a second mark of a corresponding task in response to the fact that the first pointer information reaches a preset value;
S4, in response to detecting that the first mark is set and that a second mark of other tasks is not set currently, moving corresponding continuous instructions according to the first pointer information;
S5, responding to the continuous instruction moving completion, and recovering the set first mark and second mark.
Compared with the traditional single instruction moving, the scheme provided by the invention has higher bus efficiency, and the performance is obviously improved in the program with good space locality.
In some embodiments, as shown in fig. 4, the AEM (accel-tion ENGINE MANAGER, acceleration engine management) may include a bus decoder (bus decoder), a task creation module (task generation), an instruction fetch module (instruction fetcher), an instruction cache module (instruction buffer), and a timeout processing module (timeout ctrl). In contrast to single instruction move modes, the move size of multiple instructions requires certain conditions to execute. Because of the randomness of the tasks issued by the host, the movement of multiple instructions requires the addition of a timeout handling mechanism to prevent tasks issued by the host from late failing to meet the conditions and not having an opportunity to execute.
In some embodiments, as shown in fig. 5, the function of the bus decode module is to parse the tail pointer of the configuration and some configuration values needed for hardware processing from the bus protocol according to the task issued by the host. And updating the value of the processing pointer and the head pointer of the AEM to the register. The processing progress of the host instructions is notified. The block diagram of this module is shown in fig. 5: the configuration information required by the AEM is acquired from the bus interface, different configuration information corresponds to different addresses, and the decoding logic is used for acquiring the configuration information. Configuration information such as: class 3 pointer information, configuration information for queues, and some other configuration information, etc. The mode selection signal configures the read-write operation of the bus according to the source of the information and the time.
In some embodiments, step S1, in response to receiving a request issued by a host to an IO, updates first pointer information in a corresponding task according to an address parameter of an instruction carried in the request, and specifically, as shown in fig. 6, the task creation module is configured to create task movement information according to configuration information issued by the host, so as to write the movement information into the instruction fetching module, and wait for the instruction fetching module to process the movement operation of the instruction. The module can support multitasking, each row of information represents an instruction to be moved issued by the host, the instruction must be continuous at the host side, and a discontinuous instruction needs to be split into a plurality of continuous instructions for processing, and the operation is completed at the host side. Wherein, the task request mark indicates that the task to be moved waits for execution, and there are two ways to set the task request mark: 1. updating the tail pointer to a preset value; 2 has a task timeout. The tail pointer and the processing pointer identify the processing progress of the AEM. The processing flag identifies that the move operation for the task has not been completed, and a new processing request needs to be initiated after the task is completed.
It should be noted that, the IO request issued by the host may be sent to a corresponding task in the task creation module through a different channel in the bus decoding module, and update the tail pointer information (the first pointer information) in the corresponding task. Each IO represents an independent instruction, and continuous instructions can be accumulated by updating the tail pointer parameters, so that after the threshold value is reached, the addresses of the continuous instructions are determined according to the parameters corresponding to the tail pointer, and the continuous instructions are moved.
The benefit of one-time moving of a plurality of instructions is that for spatially continuous instructions, the operation can be completed by only initiating one bus operation, and the program efficiency with good spatial locality is obviously improved. Meanwhile, as the queue for caching the instructions is composed of the RAM, a part of hardware area can be well saved relative to the realization mode of the register.
In some embodiments, in response to receiving an IO request issued by a host, updating first pointer information in a corresponding task according to an address parameter of an instruction carried in the request, further including:
Judging whether the first pointer information of the corresponding task is empty or not;
and in response to being empty, recording the IO request issuing time and timing.
Specifically, when the first pointer information in the task is empty, in order to prevent the task issued by the host from failing to meet the condition at a later time without opportunity to be executed, a timestamp is stamped according to the first received request, timing is started, and a timeout judgment flow is entered.
In some embodiments, the method further comprises:
judging whether a overtime task exists or not according to the fact that the first pointer information in each task does not reach a preset value;
setting a first flag and a second flag of a timeout task in response to the task having the timeout;
Responding to the detection that the first mark is set and the second mark of other tasks is not set currently, and moving corresponding continuous instructions according to the current first pointer information of the overtime task;
and restoring the set first mark and the set second mark of the timeout task in response to the completion of the continuous instruction movement.
Specifically, as shown in fig. 7, the timeout processing module is configured to process a timeout request for dispatching an instruction, since the multi-instruction move operation is dispatched by the host, and the instruction dispatched by the host is random. According to a specific scene, when a scene with good space locality is encountered, the moving of the instruction always meets the moving condition, and the moving can be normally performed. When a scene with poor spatial locality is encountered, tasks dispatched by a host may be discontinuous, resulting in a sporadic move operation of only one or two instructions per process. In this case, if the host is not always able to issue a new instruction satisfying the move condition, then sporadic tasks are not processed. In this scenario, a timeout mechanism is required to ensure that instructions to meet the move condition can be moved.
The timeout processing module consists of a timer, a comparator and a time stamp buffer. And the counter starts working after being electrified, and when the module receives a task request issued by the host, the time stamp of the issuing time is cached. Judging whether the time delay of each task is overtime or not through a comparator, and if the time delay is overtime, sending the overtime task request to a task creation module for processing. And normally processing the completed task and exiting the overtime processing flow.
Judging whether a task to be processed exists or not according to the request mark (first mark), and if the current process has an unfinished task, calculating the position and the size to be moved according to the configuration information. Judging whether the moving meets the minimum threshold value of the moving, if so, writing moving information into the finger taking module to wait for the moving and placing the processing mark when the second mark (the processing mark) of the other task is in a set state, namely, no other task is being processed. If not, no operation is performed until a new moving task is issued or the task is overtime. For overtime tasks, a request mark is set, and whether the shifting threshold value is met or not is not needed to be judged, so that all instructions are directly shifted at one time. And after the normal execution of the task is completed, the task with the completed normal processing is withdrawn from the overtime processing flow.
In some embodiments, S4, in response to detecting that the first flag is set and that the second flag of the other task is not set, moving the corresponding continuous instruction according to the first pointer information, specifically, as shown in fig. 8, the instruction fetching module receives the task created by the task creating module, stores moving information, such as a moving base address and a moving length, and requests a bus, sends the information to the bus, and performs an instruction moving operation. The module consists of a RAM and a state machine, wherein the RAM is used for storing moving information, the state machine is used for controlling and generating bus data packets with specified formats, and the data packets mainly comprise source addresses, destination addresses, moving lengths, other control information and the like. When a bus request is issued, state machine control logic updates the processing pointer, processes the tag, and deletes the timestamp information in the timeout processing module (this operation is completed normally, without a timeout). And the external control module performs DMA (direct memory access) moving operation according to the data packet analysis information.
In some embodiments, moving the corresponding consecutive instructions according to the first pointer information further comprises:
updating the second pointer information according to the moved instruction;
and determining that the corresponding continuous instruction movement is completed in response to the second pointer information being the same as the first pointer information.
Specifically, as shown in fig. 9, the instruction cache module mainly completes the cache of the instruction and the update operation of the head pointer (second pointer). The control state machine updates the head pointer according to the number of the received instructions and is used for identifying the instruction processing state of the AEM. Meanwhile, the module also packages the received instructions and sends some control information to a subsequent processing engine for processing.
The invention provides a continuous multi-instruction moving mode aiming at the problem of low single-instruction moving efficiency. By utilizing the locality of the program, a section of continuous instructions can be moved to the local place, split processing is carried out on the local place, and the continuous instructions become single instructions to operate. The purpose of this is to reduce the configuration frequency of the bus, and the transmission which needs to be configured for many times is changed into the transmission which needs to be completed only once, so as to achieve the purposes of reducing the access frequency of the bus and improving the utilization rate of the bus.
Based on the same inventive concept, according to another aspect of the present invention, there is further provided an instruction moving system 400, as shown in fig. 10, including:
the first updating module 401 is configured to update the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request in response to receiving the request issued by the host to the IO;
a detection module 402 configured to detect whether the first pointer information in each task reaches a preset value;
the setting module 403 is configured to set a first mark and a second mark of a corresponding task in response to detecting that the first pointer information reaches a preset value;
A moving module 404, configured to move the corresponding continuous instruction according to the first pointer information in response to detecting that the first flag is set and that the second flag of the other task is not currently set;
A restoration module 405 configured to restore the set first flag and second flag in response to the completion of the consecutive instruction movement.
In some embodiments, the first update module 401 is further configured to:
Judging whether the first pointer information of the corresponding task is empty or not;
and in response to being empty, recording the IO request issuing time and timing.
In some embodiments, the method further comprises a judging module configured to:
judging whether a overtime task exists or not according to the fact that the first pointer information in each task does not reach a preset value;
setting a first flag and a second flag of a timeout task in response to the task having the timeout;
Responding to the detection that the first mark is set and the second mark of other tasks is not set currently, and moving corresponding continuous instructions according to the current first pointer information of the overtime task;
and restoring the set first mark and the set second mark of the timeout task in response to the completion of the continuous instruction movement.
In some embodiments, the movement module 404 is further configured to:
updating the second pointer information according to the moved instruction;
and determining that the corresponding continuous instruction movement is completed in response to the second pointer information being the same as the first pointer information.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 11, an embodiment of the present invention further provides a computer apparatus 501, including:
at least one processor 520; and
The memory 510, the memory 510 stores a computer program 511 executable on a processor, and the processor 520 executes the steps of any one of the instruction moving methods described above when executing the program.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 12, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610 when executed by a processor perform the steps of any of the instruction moving methods as above.
Finally, it should be noted that, as will be appreciated by those skilled in the art, all or part of the procedures in implementing the methods of the embodiments described above may be implemented by a computer program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, and the program may include the procedures of the embodiments of the methods described above when executed.
Further, it should be appreciated that the computer-readable storage medium (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (10)
1. A method of instruction movement comprising the steps of:
Responding to a request issued by a host to an IO, and updating first pointer information in a corresponding instruction moving task according to address parameters of instructions carried in the request, wherein the first pointer information is tail instruction information of continuous instructions in the corresponding instruction moving task;
Detecting whether first pointer information in each instruction moving task reaches a preset value or not;
Setting a first mark and a second mark of a corresponding instruction moving task in response to the fact that the first pointer information reaches a preset value, wherein the setting state of the first mark indicates that the corresponding instruction moving task needs to be processed, the non-setting state indicates that the corresponding instruction moving task does not need to be processed, and the setting state of the second mark indicates that the corresponding instruction moving task is being processed, and the non-setting state indicates that the corresponding instruction moving task is not being processed;
Responding to the detection that a first mark is set and a second mark of other instruction moving tasks is not set currently, and moving corresponding continuous instructions according to the first pointer information;
and restoring the set first mark and the set second mark in response to the continuous instruction movement completion.
2. The method of claim 1, wherein in response to receiving a host issued to IO request, updating first pointer information in a corresponding instruction move task according to address parameters of an instruction carried in the request, further comprising:
judging whether first pointer information corresponding to the instruction moving task is empty or not;
and in response to being empty, recording the IO request issuing time and timing.
3. The method of claim 2, wherein the method further comprises:
Judging whether an overtime instruction moving task exists or not according to the fact that the first pointer information in each instruction moving task does not reach a preset value;
Setting a first mark and a second mark of the overtime instruction moving task in response to the overtime instruction moving task;
responding to the detection that the first mark is set and the second mark of the other instruction moving task is not set currently, and moving the corresponding continuous instruction according to the current first pointer information of the overtime instruction moving task;
And restoring the first mark and the second mark which are set by the overtime instruction moving task in response to the completion of continuous instruction moving.
4. The method of claim 1, wherein moving the corresponding successive instructions according to the first pointer information further comprises:
Updating second pointer information according to the moved instruction, wherein the second pointer information is information of the moved pointer;
and determining that the corresponding continuous instruction movement is completed in response to the second pointer information being the same as the first pointer information.
5. An instruction moving system, comprising:
The first updating module is configured to respond to receiving an IO request issued by a host, and update first pointer information in a corresponding instruction moving task according to address parameters of instructions carried in the request, wherein the first pointer information is tail instruction information of continuous instructions in the corresponding instruction moving task;
The detection module is configured to detect whether the first pointer information in each instruction moving task reaches a preset value or not;
The setting module is configured to set a first mark and a second mark of a corresponding instruction moving task in response to detecting that the first pointer information reaches a preset value;
The moving module is configured to move corresponding continuous instructions according to the first pointer information in response to detecting that a first mark is set and a second mark of other instruction moving tasks is not set currently, wherein the set state of the first mark indicates that the corresponding instruction moving task needs to be processed, the non-set state indicates that the corresponding instruction moving task does not need to be processed, the set state of the second mark indicates that the corresponding instruction moving task is being processed, and the non-set state indicates that the corresponding instruction moving task is not being processed;
And the recovery module is configured to recover the set first mark and the set second mark in response to the completion of the continuous instruction movement.
6. The system of claim 5, wherein the first update module is further configured to:
judging whether first pointer information corresponding to the instruction moving task is empty or not;
and in response to being empty, recording the IO request issuing time and timing.
7. The system of claim 6, further comprising a determination module configured to:
Judging whether an overtime instruction moving task exists or not according to the fact that the first pointer information in each instruction moving task does not reach a preset value;
Setting a first mark and a second mark of the overtime instruction moving task in response to the overtime instruction moving task;
responding to the detection that the first mark is set and the second mark of the other instruction moving task is not set currently, and moving the corresponding continuous instruction according to the current first pointer information of the overtime instruction moving task;
And restoring the first mark and the second mark which are set by the overtime instruction moving task in response to the completion of continuous instruction moving.
8. The system of claim 5, wherein the movement module is further configured to:
Updating second pointer information according to the moved instruction, wherein the second pointer information is information of the moved pointer;
and determining that the corresponding continuous instruction movement is completed in response to the second pointer information being the same as the first pointer information.
9. A computer device, comprising:
at least one processor; and
A memory storing a computer program executable on the processor, wherein the processor performs the steps of the method of any of claims 1-4 when the program is executed.
10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor performs the steps of the method according to any of claims 1-4.
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