CN114814336B - Load current sampling circuit - Google Patents
Load current sampling circuit Download PDFInfo
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- CN114814336B CN114814336B CN202210489606.0A CN202210489606A CN114814336B CN 114814336 B CN114814336 B CN 114814336B CN 202210489606 A CN202210489606 A CN 202210489606A CN 114814336 B CN114814336 B CN 114814336B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a load current sampling circuit. Aiming at the problems that the traditional load current detection circuit needs an off-chip complex sampling circuit and needs an extra pin, the invention provides an on-chip load current sampling circuit, which samples the current when a high-side power tube is started in the chip, and then the sampling value at the moment of half the starting time is extracted by using a sampling hold circuit, wherein the sampling value is equal to the sampling value of the load current.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a load current sampling circuit.
Background
The load current sampling circuit is crucial for switching power supplies (such as for fast charging applications, LEDs, current-mode COT applications) requiring constant current output or requiring feedback of inductor current information, directly affecting the reliability and performance index of such switching power supplies. For the application requiring constant current output, a small resistor is usually added between the load and the ground, and the load current is sampled through the voltage drop generated by the load current flowing through the resistor, so that the method inevitably requires an extra pin to introduce the voltage information of the resistor into the chip, and a load current sampling signal is obtained after the voltage information is processed by a sampling circuit and is used as the information of loop regulation, thereby realizing constant current output; for applications requiring feedback of inductor current information, it is often necessary to introduce the signals at both ends of the inductor back into the chip, and thus additional pins and more complex sampling circuits are also inevitably required. Therefore, the conventional load current sampling circuit not only needs an extra pin, but also needs a more complex sampling circuit. The conventional sampling method is not suitable for low power consumption and miniaturized applications.
Disclosure of Invention
Aiming at the problems that the traditional load current detection circuit needs an off-chip complex sampling circuit and needs an extra pin, the invention provides an on-chip load current sampling circuit.
The technical scheme of the invention is as follows:
a load current sampling circuit comprises a first switch NMOS tube, a second switch NMOS tube, a third switch NMOS tube, a fourth switch NMOS tube, a fifth switch NMOS tube, a sixth switch NMOS tube, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first current source, a second current source, a third current source, a fourth current source, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate, a first comparator, a second comparator, a first AND gate, a second AND gate, a first operational amplifier and a second operational amplifier; the drain electrode of the first switch NMOS tube is connected to a power supply through a first current source, the source electrode of the first switch NMOS tube is connected to the ground through a first capacitor, the source electrode of the first switch NMOS tube is connected with the source electrode of the fifth switch NMOS tube and the drain electrode of the second switch NMOS tube, the grid electrode of the first switch NMOS tube is a first control signal, and the first signal is a signal with pulse width being the opening time of the upper tube and the period being twice the switching period; the grid electrode of the fifth switch NMOS tube is connected with a global enabling signal, and the drain electrode of the fifth switch NMOS tube is connected with a reference voltage; the grid electrode of the second switch NMOS tube is connected with a second control signal, the source electrode of the second switch NMOS tube is grounded through a second current source, and the second control signal is a signal with the pulse width of 180 DEG different from the first control signal and the upper tube opening time and the period of two times of the switch period; the drain electrode of the third switch NMOS tube is connected to voltage through a third current source, the source electrode of the third switch NMOS tube is connected to ground through a second capacitor, the source electrode of the third switch NMOS tube is also connected with the drain electrode of the fourth switch NMOS tube and the source electrode of the sixth switch NMOS tube, and the grid electrode of the third switch NMOS tube is connected with a second control signal; the grid electrode of the sixth switch NMOS tube is connected with a global enabling signal, and the source electrode of the sixth switch NMOS tube is connected with a reference voltage; the source electrode of the fourth switch NMOS tube is grounded through a fourth current source, the grid electrode of the fourth switch NMOS tube is connected with a third control signal, and the third control signal is a signal with the pulse width of 180 degrees different from the opening time of the upper tube, the period of which is twice the switching period, and the phase of the second control signal;
the positive input end and the negative input end of the first comparator are respectively connected with the source electrode of the first switch NMOS tube and the reference voltage, and the output end of the first comparator is connected with the input end of the first transmission gate; the control signal of the first transmission gate is a fourth control signal, the fourth control signal is a signal with pulse width being a switching period and a period being twice the switching period, and the phase is consistent with the second control signal;
the positive input end and the negative input end of the second comparator are respectively connected with the source electrode of the third switch NMOS tube and the reference voltage, and the output end of the second comparator is connected with the input end of the second transmission gate; the control signal of the second transmission gate is a fifth control signal, wherein the fifth control signal is a signal with pulse width being a switching period and a period being twice the switching period, and the phase is consistent with the first control signal;
the output ends of the first transmission gate and the second transmission gate are connected and are connected with one input ends of the first AND gate and the second AND gate; the other input end of the first AND gate is connected with a first control signal; the other input end of the second AND gate is connected with a second control signal;
the positive input end signals of the first operational amplifier and the second operational amplifier are voltage signals which are obtained through the high-side power tube current sampling circuit and are in linear relation with the current when the high-side power tube is started, namely the inductance current, and the first operational amplifier and the second operational amplifier are connected into a unit negative feedback mode, and the output end of the first operational amplifier is connected with the input end of the third transmission gate; the control signal of the third transmission gate is the output signal of the first AND gate, the output end of the third transmission gate is connected with one end of the third capacitor and the input end of the fourth transmission gate, and the other end of the third capacitor is grounded; the control signal of the fourth transmission gate is a sixth control signal, and the sixth control signal is a signal with the same period and pulse width as the fifth control signal but a phase difference of 90 degrees; the output of the second operational amplifier is connected with the input end of the fifth transmission gate; the control signal of the fifth transmission gate is the output signal of the second AND gate, the output end of the fifth transmission gate is connected with one end of the fourth capacitor and the input end of the sixth transmission gate, and the other end of the fourth capacitor is grounded; the control signal of the sixth transmission gate is a seventh control signal, and the period and the pulse width of the seventh control signal are the same as those of the fifth control signal, but the phase difference is-90 degrees.
The beneficial effects of the invention are as follows: the current when the high-side power tube is started is sampled in the chip, and then the value at the moment of half the starting time is extracted by the sampling and holding circuit, and the sampling value at the moment is equal to the sampling value of the load current.
Drawings
Fig. 1 is a schematic diagram of a load current sampling structure according to the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings;
as shown in fig. 1, the load current sampling circuit includes a first switch NMOS, a second switch NMOS, a third switch NMOS, a fourth switch NMOS, a fifth switch NMOS, a sixth switch NMOS, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first current source, a second current source, a third current source, a fourth current source, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate, a first comparator, a second comparator, a first and gate, a second and gate, a first operational amplifier, and a second operational amplifier. The drain of the first switch NMOS tube is connected to the power supply through a first bias circuit, the source thereof is connected to the ground through a first capacitor, the source thereof is connected to the reference voltage through a fifth switch NMOS tube, and the source thereof is also connected to the drain of the second switch tube, the signal phi of the gate connection thereof n The pulse width is the opening time of the upper tube, and the period is a double switching period signal; the source electrode of the second switch NMOS tube is grounded through a second bias current source, and the signal phi connected with the grid electrode thereof n+1 The pulse width is the opening time of the upper tube, the period is the double switching period, the phase and phi n Signals 180 ° apart; the grid electrode of the fifth switch NMOS tube is connected with a global enabling signal; the drain electrode of the third switch NMOS tube is connected to the power supply through a third bias circuit, the source electrode of the third switch NMOS tube is connected to the ground through a second capacitor, the source electrode of the third switch NMOS tube is connected to the reference voltage through a sixth switch NMOS tube, and the source electrode of the third switch NMOS tube is also connected with the reference voltageThe drain electrode of the fourth switch NMOS tube and the grid electrode thereof are connected with the signal phi n+1 The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the fourth switch tube is grounded through a fourth bias current source, and the signal phi connected with the grid electrode thereof n+2 The pulse width is the opening time of the upper tube, the period is the double switching period, the phase and phi n+1 Signals 180 ° apart; the grid electrode of the sixth switch NMOS tube is connected with a global enabling signal; the positive input end and the negative input end of the first comparator are respectively connected with the source electrode of the first switch NMOS tube and the reference voltage, and the output end of the first comparator is connected with the input end of the first transmission gate; the gate signal for controlling the first transmission gate to be opened is a signal with pulse width being a switching period and period being twice the switching period and has the same phase phi n+1 Consistent; the positive input end and the negative input end of the second comparator are respectively connected with the source electrode of the third switch NMOS tube and the reference voltage, and the output end of the second comparator is connected with the input end of the second transmission gate; the gate signal for controlling the second transmission gate to be opened is a signal with pulse width being a switching period and a period being twice the switching period and has the same phase phi n Consistent; the output ends of the first transmission gate and the second transmission gate are connected and respectively connected with one input end of the first AND gate and one input end of the second AND gate; the signal of the other input end of the first AND gate is the same as the grid signal of the first switch NMOS tube; the signal of the other input end of the second AND gate is the same as the gate signal of the second switch NMOS tube; positive input signal V of first and second op-amp S The output of the first operational amplifier is connected with the input end of the third transmission gate in a form of unit negative feedback; the gate signal of the third transmission gate for controlling the opening of the third transmission gate is the output end of the first AND gate, and the output end of the third transmission gate is connected with the input ends of the third capacitor and the fourth transmission gate; the gate signal started by the controller of the fourth transmission gate has the same period as the pulse width of the gate control signal started by the second transmission gate but has a phase difference of 90 degrees; the output of the second operational amplifier is connected with the input end of the fifth transmission gate; the gate signal of the fifth transmission gate for controlling the opening of the fifth transmission gate is the output end of the second AND gate, and the output end of the fifth transmission gate is connected with the input ends of the fourth capacitor and the sixth transmission gate; grid electrode for controlling opening of sixth transmission gateThe signal is the same as the open grid control signal of the second transmission gate in period and pulse width, but the phase difference is-90 degrees.
V S In the n-th switching period, the first bias current charges the first capacitor for an on time, and in the n+1th switching period, the second bias current discharges the first capacitor, and since the second bias current is twice the first bias current, the first comparator is turned from low level to high level in half of the on time in the n+1th switching period, and the first transmission gate is kept on in full period in the n+1th switching period, so that the output of the first transmission gate is a signal with a pulse width half of the on time in the n+1th switching period; the third bias current is used for charging the second capacitor, the fourth bias current is used for discharging the second capacitor, the discharging current is twice of the charging current, the sixth switch NMOS and the reference voltage are used for providing initial voltage for the upper polar plate of the second capacitor to avoid the fourth bias current source from entering a linear region, in the n+1th switch period, the third bias current charges the second capacitor for one opening time, in the n+2th switch period, the fourth bias current discharges the second capacitor, and because the fourth bias current is twice of the third bias current, the second comparator is turned from a low level to a high level in one half of the opening time in the n+2th switch period, and the first transmission gate is kept open in the whole period in the n+2th switch period, so that the output of the second transmission gate is a signal with a pulse width of one half of the opening time; the output of the first transmission gate and the second transmission gate is a signal with a pulse width of half of the on time and a period of the on-off period, and the pulse width of the two signals respectively generated after passing through the first and the second AND gates is half of the on-off periodThe on time and the switching period with the period being twice are 180 degrees different; the first operational amplifier and the second operational amplifier are connected into a unit negative feedback, the output voltage is the inductor current sampling voltage, the signal obtained by the output of the first operational amplifier through the third transmission gate is a voltage signal which is the same as the inductor current sampling voltage in the half opening time of the nth period, remains the time of the nth period and is kept as the moment that the inductor current sampling voltage is in the half opening time in the n+1th full period, and the output of the third transmission gate only transmits the signal after the half opening time through the fourth transmission gate; the signal obtained by the output of the second operational amplifier through the fifth transmission gate is a voltage signal which is the same as the inductor current sampling voltage in the half opening time of the n+1th period, remains in the remaining time of the n+1th period and keeps the inductor current sampling voltage in the n+2th full period at the moment of the half opening time, and the output of the fifth transmission gate only transmits the signal after the half opening time through the sixth transmission gate; the output ends of the fourth transmission gate and the sixth transmission gate are connected together, so that output signals of the fourth transmission gate and the sixth transmission gate can be kept to be sampling voltage of inductive current at the moment of half opening time in a full switching period, and current of the inductive current at the moment of half opening time is a load current value, and sampling of the load current is achieved.
By the above pair signal V S Analysis of the sample-hold process at the moment of half the on time shows that the invention does not need to additionally provide a pin for sampling, has a simple structure, and is more suitable for miniaturized and low-power consumption application.
Claims (1)
1. The load current sampling circuit is characterized by comprising a first switch NMOS tube, a second switch NMOS tube, a third switch NMOS tube, a fourth switch NMOS tube, a fifth switch NMOS tube, a sixth switch NMOS tube, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first current source, a second current source, a third current source, a fourth current source, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate, a first comparator, a second comparator, a first AND gate, a second AND gate, a first operational amplifier and a second operational amplifier; the drain electrode of the first switch NMOS tube is connected to a power supply through a first current source, the source electrode of the first switch NMOS tube is connected to the ground through a first capacitor, the source electrode of the first switch NMOS tube is connected with the source electrode of the fifth switch NMOS tube and the drain electrode of the second switch NMOS tube, the grid electrode of the first switch NMOS tube is connected with a first control signal, and the first control signal is a signal with pulse width being the switching-on time of the upper tube and the period being twice the switching period; the grid electrode of the fifth switch NMOS tube is connected with a global enabling signal, and the drain electrode of the fifth switch NMOS tube is connected with a reference voltage; the grid electrode of the second switch NMOS tube is connected with a second control signal, the source electrode of the second switch NMOS tube is grounded through a second current source, and the second control signal is a signal with the pulse width of 180 DEG different from the first control signal and the upper tube opening time and the period of two times of the switch period; the drain electrode of the third switch NMOS tube is connected to voltage through a third current source, the source electrode of the third switch NMOS tube is connected to ground through a second capacitor, the source electrode of the third switch NMOS tube is also connected with the drain electrode of the fourth switch NMOS tube and the source electrode of the sixth switch NMOS tube, and the grid electrode of the third switch NMOS tube is connected with a second control signal; the grid electrode of the sixth switch NMOS tube is connected with a global enabling signal, and the source electrode of the sixth switch NMOS tube is connected with a reference voltage; the source electrode of the fourth switch NMOS tube is grounded through a fourth current source, the grid electrode of the fourth switch NMOS tube is connected with a third control signal, and the third control signal is a signal with the pulse width of 180 degrees different from the opening time of the upper tube, the period of which is twice the switching period, and the phase of the second control signal;
the positive input end and the negative input end of the first comparator are respectively connected with the source electrode of the first switch NMOS tube and the reference voltage, and the output end of the first comparator is connected with the input end of the first transmission gate; the control signal of the first transmission gate is a fourth control signal, the fourth control signal is a signal with pulse width being a switching period and a period being twice the switching period, and the phase is consistent with the second control signal;
the positive input end and the negative input end of the second comparator are respectively connected with the source electrode of the third switch NMOS tube and the reference voltage, and the output end of the second comparator is connected with the input end of the second transmission gate; the control signal of the second transmission gate is a fifth control signal, wherein the fifth control signal is a signal with pulse width being a switching period and a period being twice the switching period, and the phase is consistent with the first control signal;
the output ends of the first transmission gate and the second transmission gate are connected and are connected with one input ends of the first AND gate and the second AND gate; the other input end of the first AND gate is connected with a first control signal; the other input end of the second AND gate is connected with a second control signal;
the positive input end signals of the first operational amplifier and the second operational amplifier are voltage signals which are obtained through the high-side power tube current sampling circuit and are in linear relation with the current when the high-side power tube is started, namely the inductance current, and the first operational amplifier and the second operational amplifier are connected into a unit negative feedback mode, and the output end of the first operational amplifier is connected with the input end of the third transmission gate; the control signal of the third transmission gate is the output signal of the first AND gate, the output end of the third transmission gate is connected with one end of the third capacitor and the input end of the fourth transmission gate, and the other end of the third capacitor is grounded; the control signal of the fourth transmission gate is a sixth control signal, and the sixth control signal is a signal with the same period and pulse width as the fifth control signal but a phase difference of 90 degrees; the output of the second operational amplifier is connected with the input end of the fifth transmission gate; the control signal of the fifth transmission gate is the output signal of the second AND gate, the output end of the fifth transmission gate is connected with one end of the fourth capacitor and the input end of the sixth transmission gate, and the other end of the fourth capacitor is grounded; the control signal of the sixth transmission gate is a seventh control signal, and the period and the pulse width of the seventh control signal are the same as those of the fifth control signal, but the phase difference is-90 degrees.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210489606.0A CN114814336B (en) | 2022-05-07 | 2022-05-07 | Load current sampling circuit |
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| CN202210489606.0A CN114814336B (en) | 2022-05-07 | 2022-05-07 | Load current sampling circuit |
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| CN114814336B true CN114814336B (en) | 2023-04-28 |
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| CN114814336A (en) | 2022-07-29 |
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