CN114785380B - Direct-current carrier communication circuit with bus conflict detection function and communication method - Google Patents
Direct-current carrier communication circuit with bus conflict detection function and communication method Download PDFInfo
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- CN114785380B CN114785380B CN202210338963.7A CN202210338963A CN114785380B CN 114785380 B CN114785380 B CN 114785380B CN 202210338963 A CN202210338963 A CN 202210338963A CN 114785380 B CN114785380 B CN 114785380B
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- 230000006854 communication Effects 0.000 title claims abstract description 62
- 238000004891 communication Methods 0.000 title claims abstract description 61
- 238000001514 detection method Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims description 21
- 230000008859 change Effects 0.000 claims abstract description 6
- 230000008569 process Effects 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000001960 triggered effect Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 238000010276 construction Methods 0.000 abstract description 6
- 238000009434 installation Methods 0.000 abstract description 5
- 230000035772 mutation Effects 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000004075 alteration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/54—Systems for transmission via power distribution lines
- H04B3/542—Systems for transmission via power distribution lines the information being in digital form
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/46—Monitoring; Testing
- H04B3/462—Testing group delay or phase shift, e.g. timing jitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40228—Modbus
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention discloses a direct current carrier communication circuit with bus conflict detection, which comprises a host computer, two direct current carrier power supply lines and a plurality of slaves, wherein the host computer is connected with the slaves through the two direct current carrier power supply lines; the master computer and the slave computer both comprise a voltage reducing circuit, a singlechip and a communication circuit; the beneficial effects of the invention are as follows: communication data transmission is carried out by utilizing a direct current power supply line, and a communication line can be omitted during construction and installation; the bus communication mode can not affect other nodes when one of the nodes is damaged; when the current of the slave is increased due to excessive current, and the current mutation of the slave cannot influence the communication; the bus is provided with bus conflict detection, when the slave sends data, the slave can monitor the change of the bus data at the same time, and if the conflict is found, the slave can immediately stop sending; when the slave has data to be sent, the data can be immediately sent to the host, and the data delay cannot be increased due to the increase of the number of the slave; addresses can be conveniently allocated in sequence.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a direct current carrier communication circuit with bus conflict detection and a communication method.
Background
In an automated warehouse management system, each bin requires at least one LED indicator light for indicating the state of the bin, and a plurality of detection devices for detecting whether the current bin has articles stored therein; the indication lamp can receive a lighting command from the host machine and lights a specified color; when the detection device detects that an article is stored or taken out, the state of the article needs to be immediately sent to the host; each library bit is a slave; each bank needs to be powered and communicate with the host, and the following schemes are generally adopted in the prior art:
1. a wired communication mode is adopted, and TTL, RS485 and CAN buses are commonly used; the wired mode is adopted, and a group of communication wires are additionally arranged besides the power wires during construction and installation, so that the construction difficulty is increased;
2. by adopting a data forwarding mode, a communication line is also needed, and when one of the slaves is damaged, all the slaves cannot work normally;
3. the existing direct current carrier communication is adopted, the voltage mode is adopted for data transmission, the current mode is adopted for data transmission, when the current is increased due to excessive slave nodes, the current mutation of the slave can influence the current on the bus, so that the data transmission is influenced, and the data loss is easy to cause; in the existing direct current carrier communication, a host acquires data of a slave in a polling mode, and larger delay is caused when the slave is too many; in the existing direct current carrier communication, the addresses of a plurality of slaves are set, and the addresses are not conveniently distributed on site in a mode of short circuit of a dial switch or built-in fixed address, so that confusion is easy.
In order to save communication lines during construction and installation; when one of the nodes is damaged, other nodes are not affected; the influence of the current mutation of the slave to the communication is avoided; the data delay caused by the increase of the number of the slaves is avoided; the addresses are conveniently allocated in sequence, and therefore, a direct current carrier communication circuit with bus conflict detection and a communication method are provided.
Disclosure of Invention
The invention aims to provide a direct current carrier communication circuit with bus conflict detection and a communication method, which can omit a communication line during construction and installation; when one of the nodes is damaged, other nodes are not affected; the influence of the current mutation of the slave to the communication is avoided; the data delay caused by the increase of the number of the slaves is avoided; facilitating the sequential allocation of addresses.
In order to achieve the above purpose, the present invention provides the following technical solutions: the direct current carrier communication circuit with the bus conflict detection comprises a host, two direct current carrier power supply lines and a plurality of slaves, wherein the host is connected with the slaves through the two direct current carrier power supply lines; the host computer and the slave computer both comprise a voltage reducing circuit, a singlechip and a communication circuit.
As a preferable technical scheme of the invention, the invention further comprises two direct current carrier buses, and the master communication circuit and the slave communication circuit are connected through the two direct current carrier buses.
As a preferable technical scheme of the invention, the invention further comprises an external power supply positive electrode and an external power supply negative electrode, wherein the external power supply positive electrode is connected with the host VCC, and the external power supply negative electrode is connected with Bus-of the DC carrier Bus.
The invention also discloses a communication method of the direct current carrier communication circuit with bus conflict detection, which comprises the following steps:
as a preferable technical scheme of the invention, a host sends a query command through a direct current carrier bus, and when a slave receives the query command, if the slave has data to be uploaded, the slave firstly uploads the address of the slave and then sends the data to be uploaded; monitoring the data state of the direct current carrier bus at the same time in the process of sending the self address, if data conflict is found, immediately stopping sending, and if a plurality of slaves all have data to be sent, enabling the slave with the smallest self address value to preempt the direct current carrier bus, so as to send the self data to the host; the host gives feedback immediately after receiving the data.
As a preferred solution of the present invention, there are multiple slaves connected in the whole dc carrier bus, each slave needs to be assigned a unique address.
As a preferable technical scheme of the invention, the host sends an address setting command through the dc carrier bus every a period of time, and the address setting command includes address information i to be set.
As a preferable technical scheme of the invention, if the triggered slave receives an address setting command sent by the direct current carrier bus, the self address is set as i, the address is stored, then a signal is fed back to the host, and a key for triggering the slave is arranged on the slave.
Compared with the prior art, the invention has the beneficial effects that:
(1) Communication data transmission is carried out by utilizing a direct current power supply line, and a communication line can be omitted during construction and installation;
(2) The bus communication mode can not affect other nodes when one of the nodes is damaged;
(3) When the current of the slave is increased due to excessive current, and the current mutation of the slave cannot influence the communication;
(4) The bus is provided with bus conflict detection, when the slave sends data, the slave can monitor the change of the bus data at the same time, and if the conflict is found, the slave can immediately stop sending;
(5) When the slave has data to be sent, the data can be immediately sent to the host, and the data delay cannot be increased due to the increase of the number of the slave;
(6) Addresses can be conveniently allocated in sequence.
Drawings
FIG. 1 is a schematic diagram of a connection structure of a master and a plurality of slaves according to the present invention;
FIG. 2 is a schematic diagram of a connection structure of a master communication circuit and a slave communication circuit according to the present invention;
FIG. 3 is a schematic diagram of a data distribution structure according to the present invention;
fig. 4 is a schematic diagram of a data upload structure according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the master is connected to a plurality of slaves through two dc carrier supply lines, and the master supplies power to each of the slaves while serving as a communication line.
The master computer and the slave computer both comprise a voltage reducing circuit, a singlechip and a communication circuit;
as shown in fig. 2, the left communication circuit of the master computer and the right communication circuit of the slave computer are connected through two direct current carrier buses.
As shown in fig. 2, the positive electrode of the external power supply is connected to the host VCC to supply power to the host, the bus+ of the dc carrier Bus is pulled up to VCC through R1 by the Q1 switching tube, the negative electrode of the external power supply is connected to the Bus-, bus+ and Bus-of the dc carrier Bus to be the positive and negative electrodes of the dc carrier Bus, and connected to the slave to supply power to the slave, and at the same time for communication.
As shown in fig. 2, the host portion: tx1 is a singlechip output port, controls a switching tube Q4, and controls the switching tube Q1 through a resistor R2; tx2 is the singlechip output port, controls switch tube Q5, and bus+ is direct current carrier Bus positive pole, controls switch tube Q2 through resistance R4, and switch tube Q2's collecting electrode Rx1 inserts the singlechip input port.
As shown in fig. 2, the slave portion: bus+ is the direct current carrier Bus positive pole, and through resistance R5 control switch tube Q6, switch tube Q6's collecting electrode Rx access singlechip input port, tx be singlechip output port, control switch tube Q3, bus+ receives electric capacity C1 through D1, supplies power to the slave machine.
As shown in fig. 2, the host communication circuit: the singlechip of the host sets Tx1 to be high level, turns on a Q4 switching tube, turns on a Q1 switching tube through R2, and VCC supplies power to the direct current carrier bus through Q1 to be regarded as high level; the singlechip of the host closes Q1, then sets Tx2 as high level to open Q5, and pulls bus+ of the direct current carrier Bus low to be regarded as low level; the singlechip of the host computer closes Q1 and closes Q5, the host computer is regarded as the host computer to release the direct current carrier Bus, the host computer VCC pulls up the direct current carrier Bus voltage to be high level through the resistor R1, the slave computer can pull down the Bus voltage to be low level at the moment, bus+ of the Bus controls the switch tube Q2 through R4, the collector Rx1 of the switch tube Q2 is connected to the singlechip input port of the host computer, and the singlechip of the host computer can monitor the level change on the Bus.
As shown in fig. 2, the slave communication circuit: the bus+ of the direct current carrier Bus of the slave computer stores electricity for the capacitor C1 through the diode D1, the electric connection voltage reduction circuit on the capacitor C1 supplies power for the whole slave computer, the bus+ of the direct current carrier Bus controls the switch tube Q6 through R5, rx is connected to the input port of the singlechip, the singlechip can monitor the level change on the direct current carrier Bus, the singlechip sets Tx as high level, and the bus+ of the direct current carrier Bus is pulled down through Q3 and is regarded as low level.
As shown in fig. 2, the slave has a dc carrier bus collision detecting function, the single chip of the master turns off Q1 and turns off Q5, that is, when the master releases the dc carrier bus, the slave turns off Q3, the master VCC pulls up the dc carrier bus voltage to a high level through the resistor R1, the slave turns on Q3, the dc carrier bus is set to a low level, if a plurality of slaves turn on Q3 at the same time, the dc carrier bus is still at a low level, if a plurality of slaves are present, the slave X turns on Q3 to set the bus to a low level, and the slave Y does not turn on Q3, the dc carrier bus is still at a low level; the slave X detects that the level of the direct current carrier bus accords with the level sent by the slave X through Q6, and can continue to send; the slave Y detects that the dc carrier bus level does not match the level emitted by itself through Q6, and immediately stops transmission.
In the process of data transmission, as shown in fig. 3, the host firstly turns on Q5 to pull down the dc carrier bus for a period of time t1, then turns off Q5 to turn on Q1, and sets the dc carrier bus to be at a high level to supply power to the dc carrier bus for a period of time t2; conventional: t1< t2 represents data 0, and t1> t2 represents data 1.
In the process of data uploading, as shown in fig. 4, the host firstly starts Q5 to pull down the dc carrier bus for a period of time t1, then closes Q5 to release the dc carrier bus for a period of time t2, and then starts Q1 to be set to be high level to supply power to the dc carrier bus for a period of time t3; the slave sends up data in the process of t2, if the slave Q3 is turned on and the dc carrier bus is at low level in the process of t2, if the slave Q3 is not turned on, the dc carrier bus is pulled up to high level by R1 of the master, and the following is conventional: in the process of t2, the direct current carrier bus is low to represent data 0, the direct current carrier bus is high to represent data 1, in the process of t2, the slave monitors the direct current carrier bus through Q6, if the slave does not start Q3 and the direct current carrier bus is still low, the fact that the slave is transmitting data is indicated, and therefore transmission is stopped.
In the communication process, a host sends a query command through a direct current carrier bus, and when a slave receives the query command, if the slave has data to be uploaded, the slave firstly uploads an address of the slave and then sends the data to be uploaded; monitoring the data state of the direct current carrier bus at the same time in the process of sending the self address, if data conflict is found, immediately stopping sending, and if a plurality of slaves all have data to be sent, enabling the slave with the smallest self address value to preempt the direct current carrier bus, so as to send the self data to the host; the host immediately gives feedback after receiving the data, and the slave indicates that the data is successfully uploaded and the data is not uploaded any more after receiving the feedback; if the host does not receive any data, indicating that there is no slave to upload data, the process may be repeated at intervals.
When a plurality of slaves are connected in the whole direct current carrier bus, each slave needs to be allocated with a unique address; when an address needs to be allocated to each slave, the host sets the address to be set as i, and the conventional i=0;
the host sends an address setting command through the bus every a period of time, wherein the address setting command comprises address information i to be set.
And triggering the slave, if the triggered slave receives an address setting command sent by the direct current carrier bus, setting the self address as i, storing the address, and feeding back a signal to the host.
If the host receives a feedback signal of the slave, the address is successfully set, and the address to be set is added with 1, i=i+1; and triggering the next slave machine, and setting the address of the next slave machine until all the slave machine addresses are set.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. A direct current carrier communication circuit with bus conflict detection is characterized in that: the system comprises a host, two direct current carrier power supply lines and a plurality of slaves, wherein the host is connected with the slaves through the two direct current carrier power supply lines; the master machine and the slave machine both comprise a voltage reducing circuit, an MCU and a communication circuit; the system also comprises two direct current carrier buses, wherein the host communication circuit and the slave communication circuit are connected through the two direct current carrier buses; the power supply system also comprises an external power supply positive electrode and an external power supply negative electrode, wherein the external power supply positive electrode is connected with the host VCC, and the external power supply negative electrode is connected with Bus-of the direct current carrier Bus; the positive pole of the external power supply is connected with the host VCC, the host is powered, the direct current carrier Bus is powered by the switch tube Q1, the bus+ of the direct current carrier Bus is pulled up to VCC by the resistor R1, the negative pole of the external power supply is connected with the Bus-, bus+ and Bus-of the direct current carrier Bus, the positive pole and the negative pole of the direct current carrier Bus are connected with the slave, the slave is powered, and the communication is carried out at the same time; a host part: tx1 is connected to the MCU output port, connected to the switching tube Q4, and controls the switching tube Q1 through the resistor R2; tx2 is connected to the MCU output port, controls the switching tube Q5, pulls down the DC carrier bus to be low level, controls the switching tube Q2 through the resistor R4, and the collector electrode of the switching tube Q2 is connected to the MCU input port; slave machine part: bus+ controls a switch tube Q6 through a resistor R5, a collector electrode of the switch tube Q6 is connected to an MCU input port, tx is connected to an MCU output port, controls a switch tube Q3, and bus+ is connected to a capacitor C1 through a D1 to supply power to a slave; host communication circuitry: the host MCU sets Tx1 to be high level, turns on a Q4 switching tube, turns on the switching tube Q1 through R2, and VCC supplies power to the direct current carrier bus through Q1 to be regarded as high level; the host MCU turns off Q1, then sets Tx2 to be high level, turns on Q5, and pulls bus+ of the direct current carrier Bus low to be regarded as low level; the host MCU turns off Q1 and turns off Q5, and is regarded as the host computer to release the direct current carrier Bus, the host computer VCC pulls up the direct current carrier Bus voltage to the high level through the resistor R1, at this moment the slave computer pulls down the Bus voltage to the low level through Q3, bus+ of the Bus controls the switching tube Q2 through R4, rx1 is accessed to the host computer MCU, the host computer MCU monitors the level change on the Bus; slave communication circuit: the bus+ of the direct current carrier Bus of the slave machine stores electricity for a capacitor C1 through a diode D1, the voltage-reducing circuit of the capacitor C1 is electrically connected with the whole slave machine to supply electricity, the bus+ of the direct current carrier Bus controls a switch tube Q6 through R5, rx is connected with an MCU, the MCU monitors the level change on the direct current carrier Bus, the MCU sets Tx to be high level, and the bus+ of the direct current carrier Bus is pulled down through Q3.
2. The communication method of a direct current carrier communication circuit with bus collision detection according to claim 1, wherein: the method comprises the following steps:
the host computer sends a query command through the direct current carrier bus, and when the slave computer receives the query command, if the slave computer has data to be uploaded, the slave computer firstly uploads the address of the slave computer and then sends the data to be uploaded; monitoring the data state of the direct current carrier bus at the same time in the process of sending the self address, if data conflict is found, immediately stopping sending, and if a plurality of slaves all have data to be sent, enabling the slave with the smallest self address value to preempt the direct current carrier bus, so as to send the self data to the host; the host gives feedback immediately after receiving the data.
3. A communication method of a direct current carrier communication circuit with bus collision detection according to claim 2, characterized in that: when a plurality of slaves are connected in the whole direct current carrier bus, each slave needs to be allocated with a unique address.
4. A communication method of a direct current carrier communication circuit with bus collision detection according to claim 2, characterized in that: the host sends an address setting command through the direct current carrier bus every a period of time, wherein the address setting command comprises address information i to be set.
5. A communication method of a direct current carrier communication circuit with bus collision detection according to claim 2, characterized in that: if the triggered slave receives an address setting command sent by the direct current carrier bus, the self address is set as i, the address is stored, then a signal is fed back to the host, and a key for triggering the slave is arranged on the slave.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210338963.7A CN114785380B (en) | 2022-04-01 | 2022-04-01 | Direct-current carrier communication circuit with bus conflict detection function and communication method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210338963.7A CN114785380B (en) | 2022-04-01 | 2022-04-01 | Direct-current carrier communication circuit with bus conflict detection function and communication method |
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| Publication Number | Publication Date |
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| CN114785380A CN114785380A (en) | 2022-07-22 |
| CN114785380B true CN114785380B (en) | 2024-03-19 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101404521A (en) * | 2008-11-07 | 2009-04-08 | 北京铱钵隆芯科技有限责任公司 | Master-slave mode direct current carrier communication system and its control flow |
| JP2011050000A (en) * | 2009-08-28 | 2011-03-10 | Sony Corp | Communication centralized control system and communication centralized control method |
| CN104184492A (en) * | 2014-07-31 | 2014-12-03 | 中国农业大学 | Method and apparatus for realizing composite communication of power and communication signals in electric power system |
| CN208158584U (en) * | 2018-05-02 | 2018-11-27 | 南京雷芯聚力电子科技有限公司 | A kind of master-slave mode direct current carrier communication system |
| US11106620B1 (en) * | 2020-04-07 | 2021-08-31 | Qualcomm Incorporated | Mixed signal device address assignment |
-
2022
- 2022-04-01 CN CN202210338963.7A patent/CN114785380B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101404521A (en) * | 2008-11-07 | 2009-04-08 | 北京铱钵隆芯科技有限责任公司 | Master-slave mode direct current carrier communication system and its control flow |
| JP2011050000A (en) * | 2009-08-28 | 2011-03-10 | Sony Corp | Communication centralized control system and communication centralized control method |
| CN104184492A (en) * | 2014-07-31 | 2014-12-03 | 中国农业大学 | Method and apparatus for realizing composite communication of power and communication signals in electric power system |
| CN208158584U (en) * | 2018-05-02 | 2018-11-27 | 南京雷芯聚力电子科技有限公司 | A kind of master-slave mode direct current carrier communication system |
| US11106620B1 (en) * | 2020-04-07 | 2021-08-31 | Qualcomm Incorporated | Mixed signal device address assignment |
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| CN114785380A (en) | 2022-07-22 |
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