CN114784111A - 一种sbr-mosfet复合型半导体器件 - Google Patents
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Abstract
本发明提供了一种SBR‑MOSFET复合型半导体器件,属于半导体技术领域,其结构包括N型重掺杂半导体衬底和位于N型重掺杂半导体衬底上表面的N型半导体漂移区;N型半导体漂移区的上表面设有P型重掺杂区和N型掺杂寄生JFET区,P型重掺杂区上表面设有N型重掺杂半导体源区;N型半导体源区一侧设有延伸到N型JFET区的栅极沟槽区,采用“***栅”的形式,其中栅极控制左侧的P型轻掺杂区,右侧为与源极相连的“假栅”,控制右侧的沟道区;假栅侧及底部沟道区采用P型或N型轻掺杂均可。本发明利用***栅和反向导通沟道极大改善了沟槽栅器件性能。本发明SBR嵌入具有优化器件反向恢复特性和开关特性,以及抑制因寄生体二极管导通带来的双极退化效应。
Description
技术领域
本发明设计功率半导体技术领域,具体地说是一种集成超势垒整流器(SBR)的金属氧化物半导体场效应晶体管(MOSFET)。
背景技术
SBR-MOSFET是一种新型的碳化硅(SiC)材料功率器件,具有传统SiC垂直双扩散MOSFET低导通损耗的优点,同时具有更加低的反向恢复损耗和开关损耗。其作为开关器件应用于新能源电动汽车、轨迹交通、节能家电等领域的电机驱动***、逆变器***及电源管理***,是核心功率控制部件。
SBR-MOSFET是一种纵向沟槽结构的功率器件,采用多晶硅“***栅”结构。其中一侧为MOSFET的栅极,另一侧作为SBR的“假栅”,“假栅”通过其上方氧化层的通孔与源极相连。SBR-MOSFET具有较小的栅漏极与栅源极之间的寄生电容,开关速度更快,开关损耗低。
SBR-MOSFET是一种复合型器件,将SBR嵌入MOSFET中,对MSOFET原来的特性并没有明显退化。SBR作为单极型器件,替换了MOSFET寄生体二极管用于反向续流,使得器件的双极退化效应得到遏制,并且使得器件的反向恢复电荷降低,反向恢复损耗降低。
SBR-MOSFET是一种非对称元胞型器件,左侧沟道用作MOSFET正向导通沟道,右侧弯曲结构的沟道则为SBR的导通沟道,用于MOSFET的反向续流。其中,SBR的沟道区既可以使用P型轻掺杂,也可以使用N型轻掺杂。
传统结构以寄生体二极管作为续流二极管,不仅将P区空穴引入N型漂移区,引起器件的双极退化效应,碳化硅材料PN结的高导通势垒也使得反向恢复过程中功率损耗大。
双极退化效应是影响碳化硅器件稳定工作的关键因素。外延层生长过程中形成的基面位错能获取电子空穴复合过程所释放的能量,扩展成堆垛层错,而形成堆垛层错的区域将无法导电,导致器件的有效有源区面积减小,进而引起器件导通电阻的增大。
发明内容
本发明的技术任务是解决现有技术的不足,提供一种SBR-MOSFET复合型半导体器件。
本发明的技术方案是按以下方式实现的:
一种SBR-MOSFET复合型半导体器件,该器件基于碳化硅材料,包括N型重掺杂半导体衬底和位于N型重掺杂半导体衬底上表面的N型半导体漂移区;
N型半导体漂移区的上表面设有P型重掺杂区和N型掺杂寄生JFET区;
P型重掺杂区上表面设有N型重掺杂半导体源区;
N型重掺杂半导体源区设有贯穿N型重掺杂半导体源区并延伸到N型寄生JFET区的控制栅沟槽区;
控制栅沟槽区包含N型掺杂的多晶硅栅极和N型掺杂的多晶硅假栅;
控制栅沟槽区与左侧P型重掺杂区之间设有P型掺杂的沟道区;
控制栅沟槽区与右侧P型重掺杂区之间设有P或N型轻掺杂的沟道区;
控制栅沟槽区设有与N型寄生JFET区、P型掺杂沟道区及N型重掺杂半导体源区相接触的栅极绝缘介质;
控制栅沟槽区设有与P或N型轻掺杂沟道区及N型重掺杂半导体源区相接触的假栅绝缘介质;
控制栅沟槽区设有与N型掺杂的多晶硅栅极、N型掺杂的多晶硅假栅相接触的***栅间绝缘介质;
P或N型轻掺杂的沟道区与右侧P型重掺杂区的左边界对齐,且不超过多晶硅假栅的左边界;
N型重掺杂半导体源区和P型重掺杂区上表面共同引出源电极;
N型掺杂的多晶硅假栅上表面引出源电极;
N型掺杂的多晶硅栅极上表面引出栅电极;
N型重掺杂半导体衬底下表面引出漏电极。
所述栅极绝缘介质与假栅绝缘介质为碳化硅氧化而成,并且假栅绝缘介质厚度较栅极绝缘介质薄;***栅间绝缘介质为多晶硅氧化而成,其厚度于三者中最大。
所述P型重掺杂区与源极相连,与N型半导体漂移区相邻;在器件元胞的右半部分,P型重掺杂区与P或N型轻掺杂沟道区对多晶硅假栅形成半包围结构。
所述N型寄生JFET区的掺杂浓度比N型半导体漂移区高。
所述P型掺杂沟道区用于器件电流从漏电极到源电极的导通,P或N型轻掺杂的沟道区用于器件电流从源电极到漏电极的导通。
本发明与现有技术相比所产生的有益效果是:本发明的一种SBR-MOSFET复合型半导体器件利用SBR替换MOSFET的寄生体二极管进行续流工作,不仅解决了MOSFET反向导通时引起的双极退化问题,器件的反向恢复特性和开关特性均得到优化。
本发明的一种SBR-MOSFET复合型半导体器件,利用P型重掺杂区对SBR结构的电场屏蔽保护作用,在不改变传统结构器件输出特性和阻断特性的基础上,不仅降低了器件了反向开启电压,抑制了体二极管的开启,而且提高了器件的动态特性,具备更好的高频应用优势。
本发明的一种SBR-MOSFET复合型半导体器件,其设计合理,安全可靠,工艺兼容性好,具有很好的推广使用价值。
附图说明
图1是现有技术下的传统结构器件示意图;
图2是本发明的结构示意图;
图3是本发明的实施例与传统器件的反向导通特性示意图;
图4是本发明的实施例与传统器件在反向导通电流为100 A/cm2时的器件内部空穴分布示意图;
图5是本发明的实施例与传统器件的输出特性曲线和阻断特性示意图;
图6是本发明的实施例与传统器件的栅电荷特性示意图;
图7是本发明的实施例与传统器件在I SD≈200 A/cm2时的反向恢复特性示意图。
具体实施方式
下面结合附图及实施例对本发明的一种SBR-MOSFET复合型半导体器件作以下详细说明。
本发明的一种SBR-MOSFET复合型半导体器件,采用***栅结构;该器件包括N型重掺杂半导体衬底21和位于N型重掺杂半导体衬底21上表面的N型半导体漂移区22;所述N型半导体漂移区22上表面设有P型重掺杂区31和N型掺杂寄生JFET区24;所述P型重掺杂区31上表面设有N型重掺杂半导体源区25;N型重掺杂半导体源区25设有贯穿N型重掺杂半导体源区25并延伸到N型寄生JFET区24的控制栅沟槽区4;控制栅沟槽区4包含N型掺杂的多晶硅栅极51和N型掺杂的多晶硅假栅52;控制栅沟槽区4与左侧P型重掺杂区31之间设有P型掺杂的沟道区32;控制栅沟槽区4与右侧P型重掺杂区31之间设有P或N型轻掺杂的沟道区23;控制栅沟槽区4设有与N型寄生JFET区24、P型掺杂沟道区32及N型重掺杂半导体源区25相接触的栅极绝缘介质41;控制栅沟槽区4设有与P或N型轻掺杂沟道区23及N型重掺杂半导体源区25相接触的假栅绝缘介质43;控制栅沟槽区4设有与N型掺杂的多晶硅栅极51、N型掺杂的多晶硅假栅52相接触的绝缘介质42;P或N型轻掺杂的沟道区23与右侧P型重掺杂区31的左边界对齐,且不超过多晶硅假栅52的左边界;N型重掺杂半导体源区25和P型重掺杂区31上表面共同引出源电极12;N型掺杂的多晶硅假栅52上表面引出源电极13;N型掺杂的多晶硅栅极51上表面引出栅电极14;N型重掺杂半导体衬底21下表面引出漏电极11。
如图1为现有技术下的传统结构器件示意,该器件结构利用寄生体二极管续流,PN结的导通使得空穴进入漂移区,与电子的复合过程引起双极退化效应,导致器件的导通电阻增大,以及碳化硅材料的PN结势垒约为2.7 V,导致较高的反向恢复损耗。
如图2所示为本发明的结构示意,相对传统的碳化硅非对称元胞结构,本发明在传统结构优点的基础上,通过采用***栅及P或N型轻掺杂沟道区形成SBR结构用于MOSFET的反向续流。P或N型轻掺杂沟道区在零偏压下被完全耗尽,并且可以通过采用更薄的假栅侧氧化层厚度获取更低的SBR开启电压。
实施例
器件元胞的宽度设为2.5 μm;N型重掺杂半导体衬底21的深度为1μm;N型半导体漂移区22的深度为8μm;控制栅沟槽区4的宽度为0.9 μm,控制栅沟槽区4的深度为1.75 μm;N型掺杂多晶硅栅极51的宽度为0.3 μm;栅极绝缘介质41的厚度为50 nm;假栅绝缘介质43的厚度为10 nm;***栅间绝缘介质42的厚度为0.2 μm;N型重掺杂半导体源区25的宽度为0.35 μm,N型重掺杂半导体源区25的深度为0.4 μm。P型掺杂沟道区32的宽度为0.2μm,P型掺杂沟道区32的深度为1 μm;P或N型轻掺杂的沟道区23沿着假栅绝缘介质43的宽度为0.2μm,且其左边界与N型掺杂多晶硅假栅52的左边界对齐;P型重掺杂区31的深度为2.15 μm。
N型重掺杂半导体衬底21的掺杂浓度设为1ⅹ1018cm-3;N型半导体漂移区22的掺杂浓度设为1.2ⅹ1016 cm-3;N型掺杂多晶硅栅极51的掺杂浓度为1ⅹ1018cm-3;N型掺杂多晶硅假栅52的掺杂浓度为1ⅹ1018cm-3;N型重掺杂半导体源区25的掺杂浓度为5ⅹ1018cm-3;P型掺杂沟道区32的掺杂浓度为1ⅹ1017cm-3;N型掺杂寄生JFET区的掺杂浓度为1ⅹ1017cm-3;P或N型轻掺杂的沟道区23的掺杂浓度为1ⅹ1016cm-3;P型重掺杂区31的掺杂浓度为4ⅹ1018cm-3。
传统结构器件对应区域保持与上述相同的参数设置,不同之处在于:其多晶硅栅极14的宽度为0.84 μm;栅极左侧氧化层41的厚度为50 nm,栅极底部氧化层厚度与左侧一致;栅极右侧氧化层43的厚度为10 nm。
如图3所示,本发明的一种SBR-MOSFET复合型半导体器件在反向导通特性上表现仅1V的开启电压,低于传统器件2.7 V的开启电压。在V DS处于-4 ~ 0 V的范围内,SBR有效抑制了寄生体二极管的开启。
如图4所示,在反向导通电流为100 A/cm2时,本发明的一种SBR-MOSFET复合型半导体器件在漂移区22内的空穴浓度明显低于传统器件,从而有效解决了双极退化的问题。
如图5所示,本发明的一种SBR-MOSFET复合型半导体器件与传统器件在输出特性曲线和阻断特性曲线几乎重合,仅有少量的退化。
如图6所示,本发明的一种SBR-MOSFET复合型半导体器件相比传统器件,其栅漏电荷和栅总电荷(V GS= 15 V)分别降低了20%和63%。
如图7所示,本发明的一种SBR-MOSFET复合型半导体器件相比传统器件,在I SD≈200 A/cm2时,其反向恢复电荷降低了43%。
本发明的一种SBR-MOSFET复合型半导体器件通过SBR结构的引入,不仅使得器件的反向恢复电荷减少,栅漏电荷和栅总电荷也得到相应优化,使得MOSFET在高频应用中更具优势。
Claims (5)
1.一种SBR-MOSFET复合型半导体器件,其特征在于:该器件基于碳化硅材料,包括N型重掺杂半导体衬底(21)和位于N型重掺杂半导体衬底(21)上表面的N型半导体漂移区(22);
N型半导体漂移区(22)的上表面设有P型重掺杂区(31)和N型掺杂寄生JFET区(24);
P型重掺杂区(31)上表面设有N型重掺杂半导体源区(25);
N型重掺杂半导体源区(25)设有贯穿N型重掺杂半导体源区(25)并延伸到N型寄生JFET区(24)的控制栅沟槽区(4);
控制栅沟槽区(4)包含N型掺杂的多晶硅栅极(51)和N型掺杂的多晶硅假栅(52);
控制栅沟槽区(4)与左侧P型重掺杂区(31)之间设有P型掺杂的沟道区(32);
控制栅沟槽区(4)与右侧P型重掺杂区(31)之间设有P或N型轻掺杂的沟道区(23);
控制栅沟槽区(4)设有与N型寄生JFET区(24)、P型掺杂沟道区(32)及N型重掺杂半导体源区(25)相接触的栅极绝缘介质(41);
控制栅沟槽区(4)设有与P或N型轻掺杂沟道区(23)及N型重掺杂半导体源区(25)相接触的假栅绝缘介质(43);
控制栅沟槽区(4)设有与N型掺杂的多晶硅栅极(51)、N型掺杂的多晶硅假栅(52)相接触的***栅间绝缘介质(42);
P或N型轻掺杂的沟道区(23)与右侧P型重掺杂区(31)的左边界对齐,且不超过多晶硅假栅(52)的左边界;
N型重掺杂半导体源区(25) 和P型重掺杂区(31)上表面共同引出源电极(12);
N型掺杂的多晶硅假栅(52)上表面引出源电极(13);
N型掺杂的多晶硅栅极(51)上表面引出栅电极(14);
N型重掺杂半导体衬底(21)下表面引出漏电极(11)。
2.根据权利要求1所述的一种SBR-MOSFET复合型半导体器件,其特征在于:所述栅极绝缘介质(41)与假栅绝缘介质(43)为碳化硅氧化而成,并且假栅绝缘介质(43)厚度较栅极绝缘介质(41)薄;***栅间绝缘介质(42)为多晶硅氧化而成,其厚度于三者中最大。
3.根据权利要求1所述的一种SBR-MOSFET复合型半导体器件,其特征在于:所述P型重掺杂区(31)与源极相连,与所述N型半导体漂移区(22)相邻;在器件元胞的右半部分,所述P型重掺杂区(31)与所述P或N型轻掺杂沟道区(23)对所述多晶硅假栅(52)形成半包围结构。
4.根据权利要求1所述的一种SBR-MOSFET复合型半导体器件,其特征在于:N型寄生JFET区(24)的掺杂浓度比N型半导体漂移区(22)高。
5.根据权利要求1~5任一项所述的一种SBR-MOSFET复合型半导体器件,其特征在于:所述P型掺杂沟道区(32)用于器件电流从漏电极(11)到源电极(12)的导通;所述P或N型轻掺杂的沟道区(23)用于器件电流从源电极(12)到漏电极(11)的导通。
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CN114937692B (zh) * | 2022-07-25 | 2022-10-28 | 深圳市威兆半导体股份有限公司 | 一种具有沟道二极管的阶梯沟槽栅SiC MOSFET结构及其制备方法 |
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