CN114784084A - Vertical structure power device, preparation method and electronic equipment - Google Patents

Vertical structure power device, preparation method and electronic equipment Download PDF

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CN114784084A
CN114784084A CN202210286890.1A CN202210286890A CN114784084A CN 114784084 A CN114784084 A CN 114784084A CN 202210286890 A CN202210286890 A CN 202210286890A CN 114784084 A CN114784084 A CN 114784084A
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layer
doping
drift layer
doped
type
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曾健忠
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Sirius Semiconductor Chengdu Co ltd
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Sirius Semiconductor Chengdu Co ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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Abstract

The power device with the vertical structure comprises a drain electrode doping layer, a drift layer, an inversion super junction, a doped semiconductor column, a surface work function metal, a dielectric layer and a source electrode doping layer, reverse withstand voltage of the power device is improved through the lower doped drift layer, then the inversion super junction is arranged in the drift layer, electric field distribution in the drift layer is changed, the maximum electric field of an interface of a channel and the drift layer is reduced, and the problem that reliability of the device is reduced due to avalanche effect caused by high electric field when reverse bias voltage is connected is solved.

Description

Vertical structure power device, preparation method and electronic equipment
Technical Field
The application belongs to the technical field of semiconductor devices, and particularly relates to a vertical structure power device, a preparation method and electronic equipment.
Background
With the progress of the process level and the popularization of the Field Effect transistors (such as Fin-Field-Effect transistors (finfets), Gate-all-around (GAA) and Nano-sheet) with the three-dimensional structure in the horizontal direction, power devices with the vertical three-dimensional structure, such as tunneling Field Effect transistors, are proposed.
However, the vertical multi-layer structure process still has the problem of low reverse withstand voltage.
Disclosure of Invention
The application aims to provide a vertical structure power device, a preparation method and electronic equipment, and aims to solve the problem that reverse withstand voltage is still low due to the adoption of a vertical multilayer structure process.
The embodiment of the application provides a vertical structure power device, including:
a drain electrode doping layer doped with first type doping ions;
the drift layer is arranged on the drain electrode doping layer, the doping type of the drift layer is the same as that of the drain electrode doping layer, and the doping concentration of the drift layer is smaller than that of the drain electrode doping layer;
the inversion super junction is arranged in the drift layer, and the inversion super junction is doped with second type doped ions;
the doped semiconductor column is arranged on the drift layer and is doped with second type doped ions;
a surface work function metal formed on a side surface of the doped semiconductor pillar;
the dielectric layer is arranged on the drift layer, wherein the depth of the dielectric layer is smaller than the height of the doped semiconductor column;
and the source electrode doping layer is arranged on the dielectric layer and is connected with the doped semiconductor column.
In one embodiment, the number of the doped semiconductor columns is multiple, and the number of the inversion super junctions is one or more.
In one embodiment, the source doping layer has a same doping type as the drift layer, and a doping concentration of the source doping layer is greater than a doping concentration of the drift layer.
In one embodiment, the depth of the inversion super junction is greater than 1/2 times the thickness of the drift layer.
In one embodiment, the vertical structure power device further includes a gate electrode, and the doped semiconductor pillar is connected to the gate electrode through a contact hole.
The second aspect of the embodiments of the present application also provides a manufacturing method of a vertical structure power device, where the manufacturing method includes:
forming a drain electrode doping layer, wherein the drain electrode doping layer is doped with first type doping ions;
forming a drift layer on the drain doping layer, wherein the doping type of the drift layer is the same as that of the drain doping layer, and the doping concentration of the drift layer is less than that of the drain doping layer;
forming an inversion super junction in the drift layer, wherein the inversion super junction is doped with second type doped ions;
forming a doped semiconductor pillar on the drift layer;
forming a surface work function metal on a side surface of the doped semiconductor pillar;
forming a dielectric layer on the drift layer, wherein the depth of the dielectric layer is less than the height of the doped semiconductor column;
and forming a source electrode doping layer on the dielectric layer, wherein the source electrode doping layer is connected with the doped semiconductor column.
In one embodiment, the forming an inversion super junction in the drift layer includes:
determining a super junction doping region on the drift layer by adopting a first mask layer;
and implanting second-type doping ions into the super junction doping region to form the inversion super junction in the drift layer.
In one embodiment, the forming of the doped semiconductor pillar on the drift layer includes:
determining a semiconductor column etching area on the drift layer by adopting a second mask layer, and forming a semiconductor column through an etching process;
implanting a second type of ions into the semiconductor pillar to form the doped semiconductor pillar.
In one embodiment, the forming a dielectric layer on the drift layer includes:
forming a third mask in the region of the doped semiconductor column;
a dielectric layer is formed on the drift layer by depositing a dielectric material and is etched under the protection of said third mask.
The third aspect of the embodiments of the present application further provides an electronic device including the vertical structure power device as described in any one of the above.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the reverse withstand voltage of the power device is improved by the lower doped drift layer through the drain electrode doped layer, the drift layer, the inversion super junction, the doped semiconductor column, the surface work function metal, the dielectric layer and the source electrode doped layer, then the electric field distribution in the drift layer is changed by arranging the inversion super junction in the drift layer, the maximum electric field of the interface of the channel and the drift layer is reduced, and the problem that the reliability of the device is reduced due to the avalanche effect caused by a high electric field when reverse bias voltage is connected is solved.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.
Fig. 1 is a schematic structural diagram of a vertical structure power device according to an embodiment of the present application;
fig. 2 is a schematic flow chart illustrating a method for manufacturing a vertical structure power device according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating the formation of a drain doping layer according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of forming a drift layer and an inversion super junction according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating the formation of a doped semiconductor pillar according to an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating the formation of a dielectric layer according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram illustrating the formation of a source doped layer according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings to facilitate the description of the application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be constructed in operation as a limitation of the application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Currently, many commonly used power devices (IGBT/VDMOS) are implemented by moving the drain (drain) of the device to the bottom of the device in order to improve the voltage endurance, however, other structures still consume a lot of valuable wafer area in the horizontal direction.
Fig. 1 shows a schematic structural diagram of a vertical structure power device provided in an embodiment of the present application, and for convenience of description, only the parts related to the embodiment are shown, and detailed descriptions are as follows:
the power device with the vertical structure comprises a drain electrode doping layer 10, a drift layer 12, an inversion super junction 13, a doped semiconductor column 15, a surface work function metal 17, a dielectric layer 14 and a source electrode doping layer 16.
Specifically, the drain doped layer 10 may be disposed on the substrate, the drain doped layer 10 is doped with a first type of dopant ions, and the drift layer 12 is disposed on the drain doped layer, wherein the doping type of the drift layer 12 is the same as the doping type of the drain doped layer 10, and the doping concentration of the drift layer 12 is less than the doping concentration of the drain doped layer 10.
In one particular application, the substrate may be a silicon-based substrate, or other compound semiconductor substrate, such as gallium nitride, silicon carbide, gallium arsenide, and the like.
The inversion super junction 13 is disposed in the drift layer 12 and disposed in the drift layer 12 between adjacent doped semiconductor columns 15, wherein the inversion super junction 13 is doped with a second type of doping ions, which is different from the first type of doping ions in the drift layer, for example, the first type of doping ions may be N type doping ions, and the second type of doping ions are P type doping ions.
The doped semiconductor column 15 is arranged on the drift layer 12 and doped with second type doped ions, and the surface work function metal 17 is formed on the doped semiconductor column 15; the dielectric layer 14 is disposed on the drift layer 12, wherein the dielectric layer 14 fills the gap between the doped semiconductor pillars 15, the depth of the dielectric layer 14 is smaller than the height of the doped semiconductor pillars 15, and the source doped layer 16 is disposed on the dielectric layer 14 and connected to the doped semiconductor pillars 15.
In this embodiment, the doping concentration of the drift layer 12 is set to be less than that of the drain doping layer 10, the reverse withstand voltage of the power device is increased by the drift layer 12 with lower doping, and then the inversion super junction 13 is arranged in the drift layer 12 to change the electric field distribution in the drift layer 12, so as to reduce the maximum electric field at the interface between the channel and the drift layer 12, and avoid the problem of the reliability reduction of the device caused by the avalanche effect due to the high electric field when the reverse bias voltage is connected.
In one embodiment, the number of the doped semiconductor columns 15 is plural, and the number of the inversion super junctions 13 is one or more.
In one embodiment, the doped semiconductor columns 15 are multiple, a plurality of doped semiconductor columns 15 are arranged on the drift layer 12 in an array, and the inversion super junction 13 is disposed between adjacent doped semiconductor columns 15.
In one embodiment, the distance between adjacent doped semiconductor pillars 15 is the same, and there is no contact between the inversion super junction 13 and the doped semiconductor pillars 15.
In one embodiment, as shown in fig. 1, the doping type of the source doping layer 16 is the same as the doping type of the drift layer 12, and the doping concentration of the source doping layer 16 is greater than the doping concentration of the drift layer 12.
In a specific application, the second type of doping ions are different from the first type of doping ions, for example, the second type of doping ions are P-type doping, and the first type of doping ions are N-type doping, or the second type of doping ions are N-type doping, and the first type of doping ions are P-type doping.
In one embodiment, the first type dopant ions doped in the drain doping layer 10 and the drift layer may be N type dopant ions, for example, aluminum ions, boron ions, and the like.
In one embodiment, the second type dopant ions doped in the inversion super junction 13 and the doped semiconductor column may be P-type dopant ions, for example, phosphorous ions, nitrogen ions, and the like.
In one embodiment, the depth of the inversion super junction 13 is greater than 1/2 of the thickness of the drift layer 12.
In this embodiment, by setting the inversion super junction in the drift layer 12, the electric field distribution inside the power device can be changed in the application scenario of reverse bias of the power device, so as to reduce the maximum electric field inside the power device and avoid the avalanche effect of the device.
In one embodiment, the shape of the inversion super junction 13 may be rectangular, which is perpendicular to the line between the doped semiconductor pillars.
In this embodiment, the inversion super junction 13 may have a rectangular shape, and divides the upper portion of the drift layer 12 into several regions, and the inversion super junctions are disposed between adjacent doped semiconductor pillars 15, so that the maximum electric field in the power device is reduced.
In one embodiment, the doped semiconductor pillar 15 has a doping concentration greater than that of the inversion super junction.
In one embodiment, the vertical structure power device further includes a gate electrode, and the doped semiconductor pillar 15 is connected to the gate electrode through a contact hole.
In the present embodiment, the doped semiconductor pillar 15 is used as a gate region of the power device, and may be connected to a gate electrode by filling a metal wire in the contact hole, and the gate electrode may be disposed on the surface of the package layer.
In one embodiment, the dielectric layer 14 may be silicon oxide or silicon nitride.
In one embodiment, the surface work function metal 17 may be gold or palladium.
The embodiment of the present application further provides a manufacturing method of a vertical structure power device, which is shown in fig. 2 and includes step S101 to step S107.
In step S101, a drain doping layer doped with a first type of dopant ions is formed.
Referring to fig. 3, a drain doping layer 10 is first formed, and the drain doping layer 10 is doped with a first type dopant ion for providing a support for a subsequent process.
In a specific application, a drain electrode may be disposed below the drain doping layer 10, and the drain electrode may be used as a drain of a MOS device or a collector of an IGBT device.
Further, the drain doping layer 10 may be disposed on a substrate, the drain doping layer 10 may be formed by implanting first type dopant ions into the substrate, or the drain doping layer may be formed on the substrate by epitaxy.
Specifically, the substrate may be a silicon-based substrate, or other compound semiconductor substrate, such as gallium nitride, silicon carbide, gallium arsenide, or the like. In step S102, a drift layer is formed on the drain doped layer, wherein a doping type of the drift layer is the same as a doping type of the drain doped layer, and a doping concentration of the drift layer is less than a doping concentration of the drain doped layer.
In this embodiment, as shown in fig. 4, the drift layer 12 may be formed on the drain doped layer 10 by epitaxial growth or ion implantation, the doping type of the drift layer 12 is the same as that of the drain doped layer 10, and the doping concentration of the drift layer 12 is less than that of the drain doped layer.
In step S103, an inversion super junction is formed in the drift layer, and the inversion super junction is doped with second-type doped ions.
Referring to fig. 4, the inversion super junction 13 is disposed in the drift layer 12, wherein the inversion super junction 13 is doped with a second type of doping ions, which is different from the first type of doping ions in the drift layer 12, for example, the first type of doping ions may be N type doping ions, and the second type of doping ions are P type doping ions.
In one embodiment, in step S103, forming an inversion super junction in the drift layer specifically includes:
determining a super junction doping region on the drift layer by adopting a first mask layer;
and implanting second-type doping ions into the super junction doping region to form the inversion super junction in the drift layer.
Specifically, a super junction doping region is determined on the surface of the drift layer 12 through a first mask layer, and then an inversion super junction 13 is formed by injecting second-type doping ions into the drift layer 12 under the protection of the first mask layer.
Specifically, the depth of the ion implantation performed when the inversion super junction 13 is formed is smaller than the thickness of the drift layer 12 and larger than 1/2 of the thickness of the drift layer 12.
In this embodiment, by providing the inversion super junction 13 in the drift layer 12, the electric field distribution inside the power device can be changed in a reverse bias application scenario of the power device, so as to reduce the maximum electric field inside the power device and avoid the avalanche effect of the device.
In one embodiment, the shape of the inversion super junction 13 may be rectangular, which is perpendicular to the line between the doped semiconductor pillars.
In this embodiment, the inversion super junctions 13 may be rectangular to divide the upper portion of the drift layer 12 into several regions, and if a plurality of inversion super junctions 13 are disposed in the drift layer 12, the space between adjacent inversion super junctions 13 may not be too small to accommodate the doped semiconductor column, thereby reducing the maximum electric field in the power device.
In step S104, a doped semiconductor pillar is formed on the drift layer.
In this embodiment, as shown in fig. 5, a channel mask may be used to fabricate a pillar channel by photolithography and etching, and then a second type of dopant ions may be implanted into the pillar channel to form the doped semiconductor pillar 15.
In one embodiment, forming a doped semiconductor pillar on the drift layer may specifically include:
determining a semiconductor column etching area on the drift layer by adopting a second mask layer, and forming a semiconductor column through an etching process;
implanting a second type of ions into the semiconductor pillar to form the doped semiconductor pillar.
Referring to fig. 5, a semiconductor column etching region is determined on the drift layer 12 by the second mask layer, then a semiconductor column is formed by an etching process, at this time, the semiconductor column is mainly doped with a first type of doped ions, and finally, a doped semiconductor column 15 can be formed by injecting a second type of ions into the semiconductor column, wherein the doping concentration of the doped semiconductor column 15 is greater than that of the inversion super junction 13.
In step S105, a surface work function metal is formed on a side surface of the doped semiconductor pillar.
As shown in connection with fig. 5, a surface work function metal 17 may be formed on the upper surface of the doped semiconductor pillar 15.
In one specific application, a metal gate deposition process may be utilized to form a surface work function metal 17 on the surface of the doped semiconductor pillar 15 and on the drift layer.
In step S106, a dielectric layer is formed on the drift layer, wherein a depth of the dielectric layer is smaller than a height of the doped semiconductor pillar.
As shown in fig. 6, the dielectric layer 14 may be formed on the drift layer 12 by a deposition process, and then the doped semiconductor pillar 15 may be etched to expose a portion as needed in preparation for a subsequent source doping layer.
In one embodiment, forming a dielectric layer on the drift layer includes:
forming a third mask in the region of the doped semiconductor column;
a dielectric layer is formed on the drift layer by depositing a dielectric material and is etched under the protection of said third mask.
As shown in fig. 6, the doped semiconductor pillar 15 may be masked by a third mask to prevent the subsequent dielectric material deposition process from affecting the doped semiconductor pillar 15.
The dielectric layer 14 is formed on the drift layer 12 by depositing a dielectric material under the mask of the third mask, and then the dielectric layer 14 may be thinned by a Chemical Mechanical Polishing (CMP) process and an etching process due to the protection of the third mask, so as to expose a portion of the doped semiconductor pillar 15.
In step S107, a source doped layer is formed on the dielectric layer, the source doped layer being connected to the doped semiconductor pillar.
As shown in fig. 1, in the present embodiment, a source doped layer 16 may be formed on the dielectric layer 14 by epitaxially growing a source material, and the source doped layer 16 is connected to the doped semiconductor 15 exposed in step S106.
In an embodiment, after the processes of steps S101 to S107 are completed, the terminals of the different devices can be connected out through the contact holes by using metal wires to connect to the electrodes on the surface of the package layer.
An embodiment of the present application further provides an electronic device, including the vertical structure power device as described in any of the above.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the reverse withstand voltage of the power device is improved by the drift layer with lower doping, and then the electric field distribution in the drift layer is changed by arranging the inversion super junction in the drift layer, so that the maximum electric field of the interface of a channel and the drift layer is reduced, and the problem of reduction of the reliability of the device caused by avalanche effect caused by high electric field when reverse bias voltage is connected is avoided.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the above division of the doped regions is merely illustrated, and in practical applications, the above functional region allocation can be performed by different doped regions according to needs, that is, the internal structure of the device is divided into different doped regions to perform all or part of the above-described functions.
In the embodiment, each doped region may be integrated in one functional region, or each doped region may exist alone physically, or two or more doped regions may be integrated in one functional region, and the integrated functional regions may be implemented by using the same type of doped ions, or by using multiple types of doped ions. In addition, the specific names of the doped regions are only for the convenience of distinguishing from each other, and are not used to limit the scope of the present application. For a specific working process of the middle doped region in the method for manufacturing the device, reference may be made to a corresponding process in the foregoing method embodiment, which is not described herein again.
The above-mentioned embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims (10)

1. A vertical structure power device, comprising:
a drain electrode doping layer doped with first type doping ions;
the drift layer is arranged on the drain electrode doping layer, the doping type of the drift layer is the same as that of the drain electrode doping layer, and the doping concentration of the drift layer is smaller than that of the drain electrode doping layer;
the inversion super junction is arranged in the drift layer, and the inversion super junction is doped with second type doped ions;
the doped semiconductor column is arranged on the drift layer and is doped with second type doped ions;
a surface work function metal formed on a side surface of the doped semiconductor pillar;
the dielectric layer is arranged on the drift layer, wherein the depth of the dielectric layer is less than the height of the doped semiconductor column;
and the source electrode doping layer is arranged on the dielectric layer and is connected with the doped semiconductor column.
2. The vertical structure power device according to claim 1, wherein the number of the doped semiconductor pillars is plural, and the number of the inversion super junctions is one or more.
3. The vertical structure power device of claim 2, wherein a doping type of the source doped layer is the same as a doping type of the drift layer, and a doping concentration of the source doped layer is greater than a doping concentration of the drift layer.
4. The vertical structure power device of claim 1, wherein a depth of the inversion super junction is greater than 1/2 of a thickness of the drift layer.
5. The vertical structure power device of claim 1, further comprising a gate electrode, the doped semiconductor pillar being connected to the gate electrode through a contact hole.
6. A method for manufacturing a vertical structure power device, the method comprising:
forming a drain electrode doping layer, wherein the drain electrode doping layer is doped with first type doping ions;
forming a drift layer on the drain doping layer, wherein the doping type of the drift layer is the same as that of the drain doping layer, and the doping concentration of the drift layer is less than that of the drain doping layer;
forming an inversion super junction in the drift layer, wherein the inversion super junction is doped with second type doped ions;
forming a doped semiconductor pillar on the drift layer;
forming a surface work function metal on a side surface of the doped semiconductor pillar;
forming a dielectric layer on the drift layer, wherein the depth of the dielectric layer is less than the height of the doped semiconductor column;
and forming a source electrode doping layer on the dielectric layer, wherein the source electrode doping layer is connected with the doped semiconductor column.
7. The method of manufacturing the vertical structure power device according to claim 6, wherein the forming an inversion super junction in the drift layer comprises:
determining a super junction doping region on the drift layer by adopting a first mask layer;
and implanting second-type doping ions into the super junction doping region to form the inversion super junction in the drift layer.
8. The method of manufacturing a vertical structure power device according to claim 6, wherein the forming of the doped semiconductor pillar on the drift layer comprises:
determining a semiconductor column etching area on the drift layer by adopting a second mask layer, and forming a semiconductor column through an etching process;
implanting a second type of ions into the semiconductor pillar to form the doped semiconductor pillar.
9. The method of manufacturing a vertical structure power device according to claim 6, wherein the forming a dielectric layer on the drift layer comprises:
forming a third mask in the region of the doped semiconductor column;
a dielectric layer is formed on the drift layer by depositing a dielectric material and is etched under the protection of said third mask.
10. An electronic device comprising the vertical structure power device according to any one of claims 1 to 5.
CN202210286890.1A 2022-03-23 2022-03-23 Vertical structure power device, preparation method and electronic equipment Pending CN114784084A (en)

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