CN114759008A - Chip on film and display device - Google Patents
Chip on film and display device Download PDFInfo
- Publication number
- CN114759008A CN114759008A CN202210418866.9A CN202210418866A CN114759008A CN 114759008 A CN114759008 A CN 114759008A CN 202210418866 A CN202210418866 A CN 202210418866A CN 114759008 A CN114759008 A CN 114759008A
- Authority
- CN
- China
- Prior art keywords
- chip
- boundary
- boundary segment
- leads
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The disclosure provides a chip on film and a display device. The chip on film includes: a substrate; the chip is arranged on the substrate; the plurality of leads are arranged on the substrate and distributed at intervals, one end of each lead is connected to the chip, and the other end of each lead is used for being connected with a plurality of data signal lines of a display panel in a one-to-one correspondence manner; wherein, there are at least two of the leads that have different lengths, and the length of the data signal line connected by the lead with the larger length is smaller than the length of the data signal line connected by the lead with the smaller length. The present disclosure can improve display image quality.
Description
Technical Field
The present disclosure relates to display technologies, and in particular, to a chip on film and a display device.
Background
Flat panel displays have become the mainstream products in the market, and the types of flat panel displays are increasing, such as Liquid crystal displays (Liquid crystal Display 1 Disp1ay, LCD), Organic Light Emitting Diode (OLED) displays, plasma Display panels (P1asma Disp1 aypanel 1, PDP), and Field Emission Displays (FED). The flat panel display in the prior art is developed towards high resolution and high refresh rate. However, the display has a problem of poor display quality.
Disclosure of Invention
The present disclosure provides a chip on film and a display device, which can improve display quality.
According to an aspect of the present disclosure, there is provided a chip on film, including:
a substrate;
the chip is arranged on the substrate;
the plurality of leads are arranged on the substrate and distributed at intervals, one end of each lead is connected to the chip, and the other end of each lead is used for being connected with a plurality of data signal lines of a display panel in a one-to-one correspondence manner;
wherein, there are at least two of the leads that have different lengths, and the length of the data signal line connected by the lead with the larger length is smaller than the length of the data signal line connected by the lead with the smaller length.
Further, the boundary of the chip comprises a first boundary segment, at least part of the leads are sequentially distributed along the extending track of the first boundary segment, and the lengths of the leads sequentially distributed along the first boundary segment are increased or decreased progressively.
Further, a plurality of the leads are distributed along the boundary of the chip in sequence; the boundary of the chip also comprises a second boundary segment, and the starting point of the first boundary segment is superposed with the starting point of the second boundary segment;
the lengths of the lead wires distributed in sequence from the starting point of the first boundary section to the end point of the first boundary section are decreased progressively;
the lengths of the lead wires distributed in sequence from the starting point of the second boundary segment to the end point of the second boundary segment are decreased progressively.
Further, the boundary of the chip comprises two oppositely arranged straight sides;
the starting point of the first boundary segment and the end point of the first boundary segment are positioned on the same straight edge; or
The starting point of the first boundary segment and the end point of the first boundary segment are positioned on different straight edges; or
The starting point of the second boundary segment and the end point of the second boundary segment are positioned on the same straight edge; or
The starting point of the second boundary segment and the end point of the second boundary segment are located on different straight edges.
Further, the end of the first boundary segment coincides with the end of the second boundary segment.
Further, the boundary of the chip includes two straight sides disposed oppositely, the start point of the first boundary segment and the end point of the first boundary segment are located on different straight sides, and a straight line passing through the start point of the first boundary segment and the end point of the first boundary segment is perpendicular to the straight sides.
Further, at least one of the leads with different lengths comprises at least two line segments with different extending directions.
Further, the difference in length between the two leads is proportional to the difference in capacitance between the two leads.
Further, the absolute value of the difference in capacitance between the two lead lines is greater than or equal to the absolute value of the difference in capacitance between the two data signal lines connected to the two lead lines.
According to an aspect of the present disclosure, there is provided a display device including:
the chip on film;
and the display panel comprises a plurality of data signal lines, and the data signal lines are connected with the lead wires in a one-to-one correspondence manner.
The length of the data signal line connected by the lead wire with larger length is smaller than that of the data signal line connected by the lead wire with smaller length, and the capacitance of the lead wire with larger length is larger than that of the lead wire with smaller length, and the capacitance of the data signal line with larger length is larger than that of the data signal line with smaller length, so that the capacitance of the data signal line of the display panel is compensated by the lead wire on the chip on film, and the display image quality of the display panel is improved.
Drawings
Fig. 1 is a schematic diagram of a chip on film according to an embodiment of the disclosure.
Fig. 2 is a schematic diagram of a chip of an embodiment of the disclosure.
Description of reference numerals: 1. a chip; 101. a first straight side; 102. a second straight side; 103. a third straight side; 104. a fourth straight side; 2. a lead wire; 201. a first lead; 202. a second lead; 3. a pad; 4. a first boundary segment; 5. a second boundary segment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary implementations below do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in the description and claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms a, an, etc. do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
In the related art, the display panel includes a plurality of sub-pixels distributed in an array, and the plurality of sub-pixels may form a plurality of pixel columns. The display panel further includes a plurality of display data signal lines, and the pixel circuits of the plurality of sub-pixels in the same pixel column may be connected to the same display data signal line, and the display data signal may be written to the pixel circuits of the sub-pixels by charging the display data signal line. As the size of the display panel is becoming larger, the refresh frequency is increasing, even to 500/1000Hz, the charging rate of the display panel is a great challenge, and the display image quality is poor (e.g. uneven light emission) caused by insufficient charging of the display data signal lines, and some of the defects need to be improved by adding compensation capacitors to the display data signal lines.
The present disclosure performs simulation on the capacitance of the wiring, and finds that the capacitance of the wiring satisfies the following disclosure:
y＝mx+n；
y represents the wiring capacitance, x represents the wiring length, and m is greater than 0, and it is understood that the wiring capacitance and the wiring length are linearly related, and the larger the wiring length, the larger the wiring capacitance.
The disclosed embodiments provide a chip on film. As shown in fig. 1, the chip on film may include a substrate, a chip 1 and a plurality of leads 2, wherein:
the chip 1 is provided on a substrate. The plurality of leads 2 are disposed on the substrate and are spaced apart. One end of each lead 2 is connected to the chip 1, and the other end of each lead 2 is used for one-to-one corresponding connection with a plurality of data signal lines of the display panel. At least two leads 2 in the plurality of leads 2 have different lengths, and the length of the data signal line connected with the lead 2 with the larger length is smaller than the length of the data signal line connected with the lead 2 with the smaller length.
In the chip on film of the present disclosure, the length of the data signal line connected to the lead 2 with the larger length is smaller than the length of the data signal line connected to the lead 2 with the smaller length, and since the capacitance of the lead 2 with the larger length is greater than the capacitance of the lead 2 with the smaller length, and the capacitance of the data signal line with the larger length is greater than the capacitance of the data signal line with the smaller length, the capacitance of the data signal line of the display panel is compensated by the lead 2 on the chip on film, thereby improving the display image quality of the display panel.
The following describes each part of the chip on film according to the embodiment of the present disclosure in detail:
the substrate may be a flexible substrate. The material of the flexible substrate may be PI (Polyimide), PA (Polyamide), or PBO (Poly-p-phenylene benzobisoxazole).
The chip 1 is provided on a substrate. The chip 1 includes a plurality of pins, and the plurality of pins are connected to the plurality of leads 2 in a one-to-one correspondence manner, so as to write data signals into the leads 2, and further write data signals into data signal lines connected to the leads 2. The boundary of the chip 1 may be circular, such as rectangular, square, circular, trapezoidal, etc. The boundary of the chip 1 refers to the boundary of the orthographic projection of the chip 1 on the substrate. The boundary of the chip 1 may comprise two straight sides arranged oppositely. Taking the example that the boundary of the chip 1 is rectangular, the boundary of the chip 1 has a first straight edge 101, a second straight edge 102, a third straight edge 103 and a fourth straight edge 104 which are connected in sequence. The first straight side 101 and the third straight side 103 are arranged opposite to each other, the second straight side 102 and the fourth straight side 104 are arranged opposite to each other, and the length of the first straight side 101 may be greater than the length of the second straight side 102.
As shown in fig. 2, the boundary of the chip 1 includes a first boundary segment 4 (a portion to the left of the straight line L in fig. 2). Taking the example that the boundary of the chip 1 is rectangular or square, the start point of the first boundary segment 4 and the end point of the first boundary segment 4 may be located on the same straight edge of the chip 1. Of course, as shown in fig. 2, the start point O of the first border segment 4 and the end point Q of the first border segment 4 may be located on two oppositely disposed straight sides, respectively, e.g. the start point O of the first border segment 4 is located on the first straight side 101 and the end point Q of the first border segment 4 is located on the third straight side 103. In other embodiments of the present disclosure, the starting point of the first boundary segment 4 and the end point of the first boundary segment 4 may be located on two adjacent straight edges, respectively, for example, the starting point of the first boundary segment 4 is located on the first straight edge 101, and the end point of the first boundary segment 4 is located on the second straight edge 102. A straight line L (see fig. 2) passing through the start point of the first border segment 4 and the end point of the first border segment 4 may be perpendicular to the first straight side 101, and the start point O of the first border segment 4 may be the midpoint of the first straight side 101.
As shown in fig. 2, the boundary of the chip 1 may further comprise a second boundary segment 5 (the portion to the right of the straight line L in fig. 2). Taking the example that the boundary of the chip 1 is rectangular or square, the start point of the second boundary segment 5 and the end point of the second boundary segment 5 may be located on the same straight edge of the chip 1. Of course, the start point of the second boundary segment 5 and the end point of the second boundary segment 5 may be located on two straight sides oppositely arranged, respectively, e.g. as shown in fig. 2, the start point O of the second boundary segment 51At the end point Q of the second boundary segment 5 on the first straight edge 1011At the third straight edge 103. In other embodiments of the present disclosure, the starting point of the second boundary segment 5 and the end point of the second boundary segment 5 may be located on two adjacent straight edges, respectively, for example, the starting point of the second boundary segment 5 is located on the first straight edge 101, and the end point of the second boundary segment 5 is located on the fourth straight edge 104. The starting point O of the first boundary segment 4 may be the starting point O of the second boundary segment 51However, this is not a particular limitation in the embodiments of the present disclosure. The end point Q of the first boundary segment 4 may be equal toEnd point O of the two-boundary segment 51However, the embodiment of the present disclosure is not limited to this. The length of the first border segment 4 may be equal to the length of the second border segment 5, of course the length of the first border segment 4 may be greater or smaller than the length of the second border segment 5.
As shown in fig. 1, a plurality of leads 2 are disposed on the substrate and spaced apart from each other. The plurality of leads 2 may be provided in the same layer, that is, the plurality of leads 2 may be prepared by one photolithography process. The material of the lead 2 may be silver, but the material of the lead 2 may also be copper. In other embodiments of the present disclosure, the lead 2 has a laminated structure in the thickness direction of the substrate. The disclosed embodiment may further include a protective layer covering the lead 2 and the substrate. The protective layer may be an insulating material. The protective layer may be provided with a first binding opening and a second binding opening. The first binding opening and the second binding opening may be spaced apart. The first binding opening may expose one end of each lead 2, and the second binding opening may expose the other end of each lead 2. The first binding opening may be circular, and of course, may also be rectangular or square, but the disclosed embodiments are not limited thereto. The second binding opening may be rectangular, and of course, may also be bar-shaped, but the disclosure is not limited thereto. The chip 1 may be disposed at the first bonding opening, so that the chip 1 is connected to one end of each lead 2. Taking the boundary of the chip 1as a rectangle or a square, the first straight side 101 may be located between the third straight side 103 and the second binding opening, and the strip-shaped second binding opening may be parallel or substantially parallel to the first straight side 101.
At least two of the plurality of leads 2 have different lengths, and the length of the data signal line connected to the lead 2 having the larger length is smaller than the length of the data signal line connected to the lead 2 having the smaller length. The data signal line may be a display data signal line to write a display data signal to the pixel circuit. Of course, the data signal line may be a gate scanning data signal line to write a gate scanning data signal to the pixel circuit. In other embodiments of the present disclosure, the data signal line may also be a touch data signal line for writing a touch driving signal to the touch electrode. Further, at least some of the leads 2 in the plurality of leads 2 are sequentially distributed along the extending track of the first boundary segment 4, and the lengths of the leads 2 sequentially distributed along the first boundary segment 4 are increased or decreased. At least some of the leads 2 in the plurality of leads 2 are sequentially distributed along the extending track of the second boundary section 5, and the lengths of the leads 2 sequentially distributed along the second boundary section 5 are increased or decreased progressively. Wherein the number of said "at least part of the leads 2" may be greater than or equal to 2. The "increasing" means that the length of the lead 2 is gradually increased, and the "decreasing" means that the length of the lead 2 is gradually decreased. In the above-mentioned sequentially distributed leads 2, the distances between two adjacent leads 2 may be equal, and of course, may not be equal. Taking as an example that the starting point of the first boundary segment 4 coincides with the starting point of the second boundary segment 5 and the starting point of the first boundary segment 4 is located at the first straight side 101, the lengths of the lead wires 2 distributed in sequence from the starting point of the first boundary segment 4 to the end point of the first boundary segment 4 are decreased progressively; the lengths of the leads 2 sequentially distributed from the start point of the second boundary segment 5 to the end point of the second boundary segment 5 are decreased progressively. In addition, it should be noted that the cross-sectional areas of the plurality of leads 2 may be the same, and of course, may also be different, but the embodiment of the present disclosure is not limited thereto. The difference in the length of the two leads 2 having different lengths is proportional to the difference in the capacitance of the two leads 2. For example, the difference in the lengths of the first and second leads 201 and 202 is proportional to the difference in the capacitances of the first and second leads 201 and 202. Further, (the capacitance of the first lead 201-the capacitance of the second lead 202) may be greater than or equal to (the capacitance of the data signal line to which the second lead 202 is connected-the capacitance of the data signal line to which the first lead 201 is connected), that is, the absolute value of the difference in the capacitances of the two leads 2 is greater than or equal to the absolute value of the difference in the capacitances of the two data signal lines.
At least one lead 2 in the leads 2 with different lengths comprises at least two line segments with different extending directions. The present disclosure adjusts the length of the lead 2 by controlling the lengths of the run sections extending in different directions. Further, each lead 2 comprises at least two running line segments with different extension directions. In addition, the number of the trace segments included in different leads 2 may be different, but the embodiment of the present disclosure does not limit this. As shown in fig. 1, the first lead 201 includes a running line segment with a line length a, two running line segments with a line length b, a running line segment with a line length c, and a running line segment with a line length d, so that the length of the first lead 201 is (a +2b + c + d); the second lead 202 includes a running line segment with a line length of e, a running line segment with a line length of f, a running line segment with a line length of g, and a running line segment with a line length of h, so that the length of the second lead 202 is (e + f + g + h). In order to make the length of the first lead 201 greater than the length of the second lead 202, the present disclosure may increase the length of a running line segment of a line length b in the first lead 201 to make the length of the first lead 201 greater than the length of the second lead 202.
The embodiment of the disclosure also provides a display device. The display device may include a display panel and the flip chip on film according to any of the above embodiments. The display panel may include a plurality of data signal lines connected to the plurality of lead lines in a one-to-one correspondence. Specifically, as shown in fig. 1, the lead 2 and the data signal line are connected through a pad 3 on the display panel. The display device may be a mobile phone, a tablet computer, a television, or the like. Since the touch panel in the display device of the embodiment of the present disclosure is the same as the touch panel in the embodiment of the touch panel, the touch panel has the same beneficial effects, and details are not repeated herein.
Although the present disclosure has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.
Claims (10)
1. A chip on film, comprising:
a substrate;
the chip is arranged on the substrate;
the plurality of leads are arranged on the substrate and distributed at intervals, one end of each lead is connected to the chip, and the other end of each lead is used for being connected with a plurality of data signal lines of a display panel in a one-to-one correspondence manner;
wherein, there are at least two of the leads that have different lengths, and the length of the data signal line connected by the lead with the larger length is smaller than the length of the data signal line connected by the lead with the smaller length.
2. The chip on film as claimed in claim 1, wherein the chip boundary comprises a first boundary segment, at least some of the leads are sequentially distributed along the extended trace of the first boundary segment, and the lengths of the leads sequentially distributed along the first boundary segment are increased or decreased.
3. The chip on film of claim 2, wherein a plurality of the leads are sequentially distributed along the boundary of the chip; the boundary of the chip also comprises a second boundary segment, and the starting point of the first boundary segment is superposed with the starting point of the second boundary segment;
the lengths of the lead wires distributed in sequence from the starting point of the first boundary section to the end point of the first boundary section are decreased progressively;
the lengths of the lead wires distributed in sequence from the starting point of the second boundary segment to the end point of the second boundary segment are decreased progressively.
4. The chip on film of claim 3, wherein the chip boundary comprises two oppositely disposed straight sides;
the starting point of the first boundary segment and the end point of the first boundary segment are positioned on the same straight edge; or
The starting point of the first boundary segment and the end point of the first boundary segment are positioned on different straight edges; or
The starting point of the second boundary segment and the end point of the second boundary segment are positioned on the same straight edge; or alternatively
The starting point of the second boundary segment and the end point of the second boundary segment are located on different straight edges.
5. The chip on film of claim 3, wherein the end point of the first boundary segment coincides with the end point of the second boundary segment.
6. The chip on film of claim 5, wherein the boundary of the chip comprises two oppositely disposed straight sides, the start point of the first boundary segment and the end point of the first boundary segment are located on different straight sides, and a straight line passing through the start point of the first boundary segment and the end point of the first boundary segment is perpendicular to the straight sides.
7. The chip on film of claim 1, wherein at least one of the leads having different lengths comprises at least two wire segments extending in different directions.
8. The chip on film of claim 1, wherein the difference in length between the two leads is proportional to the difference in capacitance between the two leads.
9. The chip on film according to claim 1, wherein an absolute value of a difference in capacitance between the two leads is greater than or equal to an absolute value of a difference in capacitance between two data signal lines connected to the two leads.
10. A display device, comprising:
a flip-chip on film according to any one of claims 1 to 9;
and the display panel comprises a plurality of data signal lines, and the data signal lines are connected with the lead wires in a one-to-one correspondence manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210418866.9A CN114759008A (en) | 2022-04-20 | 2022-04-20 | Chip on film and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210418866.9A CN114759008A (en) | 2022-04-20 | 2022-04-20 | Chip on film and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114759008A true CN114759008A (en) | 2022-07-15 |
Family
ID=82331444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210418866.9A Pending CN114759008A (en) | 2022-04-20 | 2022-04-20 | Chip on film and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114759008A (en) |
-
2022
- 2022-04-20 CN CN202210418866.9A patent/CN114759008A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10510280B2 (en) | Display panel and display apparatus having the same | |
| US10529273B2 (en) | Display device | |
| US9875699B2 (en) | Display device | |
| US11411058B2 (en) | Flexible display device | |
| KR102173356B1 (en) | Display Panel having the Curved Panel | |
| US9811169B2 (en) | Flexible array substrate, display panel having the same, keyboard assembly, and electronic device thereof | |
| US9389476B2 (en) | Liquid crystal display device and method of driving the same | |
| US9406264B2 (en) | Display device | |
| WO2021164359A1 (en) | Display panel and electronic device | |
| US10818735B2 (en) | Organic light-emitting display panel and display device | |
| US9576520B2 (en) | Display device with groove in a non-display area and method of manufacturing the same | |
| US8643802B2 (en) | Pixel array, polymer stablized alignment liquid crystal display panel, and pixel array driving method | |
| WO2020156057A1 (en) | Display and display panel thereof | |
| US10963114B1 (en) | Touch display panel | |
| CN113724604A (en) | Display substrate and electronic equipment | |
| US11139362B2 (en) | Display panel with asymmetrically disposed pads | |
| CN111948859A (en) | Display substrate and display device | |
| CN115079857A (en) | Display device | |
| US11520200B2 (en) | Display device and method of manufacturing the same | |
| KR20210052741A (en) | Display device | |
| CN114265516B (en) | Touch display panel and display device | |
| CN114759008A (en) | Chip on film and display device | |
| WO2019056854A1 (en) | Array substrate and display panel | |
| CN101852957B (en) | Active element array substrate | |
| WO2021103012A1 (en) | Array substrate and manufacturing method therefor, pixel driving method, and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |