CN114758634B

CN114758634B - Driving module, driving method and display device

Info

Publication number: CN114758634B
Application number: CN202210442567.9A
Authority: CN
Inventors: 袁粲; 李永谦; 袁志东; 吴刘
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2022-04-25
Filing date: 2022-04-25
Publication date: 2023-09-29
Anticipated expiration: 2042-04-25
Also published as: CN114758634A

Abstract

The invention provides a driving module, a driving method and a display device. The driving module comprises A driving units, wherein A is an integer greater than 1; the a-th driving unit provides corresponding a-th driving signals for the pixel circuits in a plurality of rows respectively; a is a positive integer less than or equal to A; the a-th driving unit comprises B driving modules; the b-th driving module included in the a-th driving unit includes at least one stage of a-th driving circuit; b is a positive integer less than or equal to B; the a-th driving circuit comprises a first reset circuit and a reset control end; the reset control end of the last stage of driving circuit in the b-th driving module included in the A driving units is electrically connected with the b-th pull-down control end. The invention can reduce the number of the adopted pull-down control ends, is beneficial to realizing a narrow frame and prevents the overlapping of the overline and the signal line.

Description

Driving module, driving method and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a driving module, a driving method, and a display device.

Background

In the related art, the driving module includes at least two driving units, each driving unit is used for providing different driving signals respectively; the effective display area of the display panel may include a plurality of partitions, each partition is controlled by a corresponding driving module, a last stage driving circuit in the driving module corresponding to each partition in at least two driving units is electrically connected with a corresponding pull-down control end, so that the number of pull-down control ends adopted by the related driving modules is more, and reset control signals provided by the pull-down control ends are provided by COFs (chip on film), which occupy more signal line resources of the COFs (chip on film), increase COF cost, are unfavorable for realizing narrow frames, and are easy to generate conditions of line crossing and signal overlapping.

Disclosure of Invention

The invention mainly aims to provide a driving module, a driving method and a display device, which are used for solving the problems that the existing driving module adopts a large number of pull-down control ends, is not beneficial to realizing a narrow frame and is easy to generate the conditions of line crossing and signal overlapping.

The embodiment of the invention provides a driving module which is used for providing driving signals for a plurality of rows and columns of pixel circuits included in a display panel; c is an integer greater than 1, and the effective display area of the display panel comprises B subareas, wherein B is a positive integer; at least one row of C column pixel circuits are arranged in the subarea;

the driving module comprises A driving units, wherein A is an integer greater than 1; the a-th driving unit is used for providing corresponding a-th driving signals for the pixel circuits in the plurality of rows respectively; a is a positive integer less than or equal to A;

the a-th driving unit comprises B driving modules; the b-th driving module comprises at least one stage of a-th driving circuit, and the a-th driving circuit provides corresponding a-th driving signals for corresponding row of pixel circuits in the b-th partition; b is a positive integer less than or equal to B;

the a-th driving circuit comprises a first reset circuit and a reset control end;

The first reset circuit is respectively and electrically connected with a corresponding reset control end, a corresponding first node and a first voltage end and is used for controlling the communication between the first node and the first voltage end under the control of a reset control signal provided by the reset control end so as to reset the potential of the first node;

the reset control end of the last stage of driving circuit in the b-th driving module included in the A driving units is electrically connected with the b-th pull-down control end, and the b-th pull-down control end is used for providing corresponding reset control signals for the reset control end of the last stage of driving circuit in the b-th driving module included in the A driving units.

Optionally, the a-th driving circuit further comprises a carry signal output end and a carry signal output circuit;

the carry signal output circuit is respectively and electrically connected with the first node, the corresponding second node and the carry signal output end and is used for controlling the carry signal output end to output a carry signal under the control of the potential of the first node and the potential of the second node;

and the reset control end of the driving circuit except the driving circuit of the last stage in the b driving module included in the A driving units is electrically connected with the carry signal output end of the driving circuit of the next stage.

Optionally, the a-th driving circuit further comprises a driving signal output end and a driving signal output circuit;

the driving signal output circuit is respectively and electrically connected with the first node, the corresponding second node and the driving signal output end and is used for controlling the driving signal output end to output corresponding driving signals under the control of the potential of the first node and the potential of the second node;

and the reset control end of the driving circuit except the driving circuit of the last stage in the b driving module included in the A driving units is electrically connected with the driving signal output end of the driving circuit of the next adjacent stage.

Optionally, the first reset circuit includes a first transistor;

the control electrode of the first transistor is electrically connected with the reset control end, the first electrode of the first transistor is electrically connected with the first node, and the second electrode of the first transistor is electrically connected with the first voltage end.

Optionally, the carry signal output circuit includes a second transistor and a third transistor;

the control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the corresponding output clock signal end, and the second electrode of the second transistor is electrically connected with the carry signal output end;

The control electrode of the third transistor is electrically connected with the second node, the first electrode of the third transistor is electrically connected with the carry signal output end, and the second electrode of the third transistor is electrically connected with the second voltage end.

Optionally, the driving signal output circuit includes a fourth transistor and a fifth transistor;

the control electrode of the fourth transistor is electrically connected with the first node, the first electrode of the fourth transistor is electrically connected with the corresponding output clock signal end, and the second electrode of the fourth transistor is electrically connected with the driving signal output end;

the control electrode of the fifth transistor is electrically connected with the second node, the first electrode of the fifth transistor is electrically connected with the driving signal output end, and the second electrode of the fifth transistor is electrically connected with the second voltage end.

Optionally, the a-th driving circuit further includes an input circuit, a second reset circuit, a second node control circuit, a third reset circuit, a first energy storage circuit and a second energy storage circuit;

the input circuit is respectively and electrically connected with the input end, the third voltage end and the first node and is used for controlling the communication between the first node and the third voltage end under the control of an input signal provided by the input end;

The second reset circuit is electrically connected with the frame reset end, the first node and the second voltage end respectively and is used for controlling the communication between the first node and the second voltage end under the control of a frame reset signal provided by the frame reset end;

the third reset circuit is respectively and electrically connected with the second node, the first node and the second voltage end and is used for controlling the communication between the first node and the second voltage end under the control of the potential of the second node;

the second node control circuit is respectively and electrically connected with the control clock signal end, the first node and the second node and is used for controlling the potential of the second node under the control of the control clock signal provided by the control clock signal end and the potential of the first node;

the first energy storage circuit is electrically connected with the first node and is used for storing electric energy;

the second energy storage circuit is electrically connected with the second node and is used for storing electric energy.

Optionally, the input circuit includes a sixth transistor;

the control electrode of the sixth transistor is electrically connected with the input end, the first electrode of the sixth transistor is electrically connected with the third voltage end, and the second electrode of the sixth transistor is electrically connected with the first node Q;

The second reset circuit includes a seventh transistor;

a control electrode of the seventh transistor is electrically connected with the frame reset end, a first electrode of the seventh transistor is electrically connected with the first node, and a second electrode of the seventh transistor is electrically connected with the second voltage end;

the third reset circuit includes an eighth transistor;

the control electrode of the eighth transistor is electrically connected with the second node, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the second voltage end;

the second node control circuit includes a ninth transistor and a tenth transistor;

the control electrode of the ninth transistor and the first electrode of the ninth transistor are electrically connected with the control clock signal end, and the second electrode of the ninth transistor is electrically connected with the second node;

the control electrode of the tenth transistor is electrically connected with the first node, the first electrode of the tenth transistor is electrically connected with the second node, and the second electrode of the tenth transistor is electrically connected with the second voltage end;

the first energy storage circuit comprises a first capacitor, and the second energy storage circuit comprises a second capacitor;

The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the driving signal output end;

the first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the second voltage end.

The embodiment of the invention also provides a driving method which is applied to the driving module and comprises the following steps:

the b-th pull-down control end provides a corresponding reset control signal for the reset control end of the last stage of driving circuit in the b-th driving module included in the A driving units.

Optionally, the display period includes a plurality of reset periods; the driving method includes:

and in the reset time period, under the control of a b-th pull-down control signal provided by the b-th pull-down control end, a first reset circuit in the last stage driving circuit controls the communication between a first node and a first voltage end in the last stage driving circuit so as to reset the potential of the first node.

The invention also provides a display device comprising the driving module.

Optionally, the display device according to at least one embodiment of the present invention further includes a display panel, where the display panel includes a plurality of rows and columns of pixel circuits, and C is an integer greater than 1; the pixel circuit comprises a light emitting element, a driving circuit, a data writing circuit, an initializing circuit and a third energy storage circuit;

The initialization circuit is respectively and electrically connected with a first drive control end, an initial voltage end and a first pole of the light-emitting element and is used for controlling the initial voltage provided by the initial voltage end to be written into the first pole of the light-emitting element under the control of a first drive signal provided by the first drive control end;

the data writing circuit is respectively and electrically connected with a second driving control end, a data line and a control end of the driving circuit and is used for controlling the writing of the data voltage provided by the data line into the control end of the driving circuit under the control of a second driving signal provided by the second driving control end;

the third energy storage circuit is electrically connected with the control end of the driving circuit and is used for storing electric energy;

the first end of the driving circuit is electrically connected with a fourth voltage end, the second end of the driving circuit is electrically connected with the first pole of the light-emitting element, and the driving circuit is used for controlling the communication between the fourth voltage end and the first pole of the light-emitting element under the control of the potential of the control end of the driving circuit;

the second pole of the light-emitting element is electrically connected with the fifth voltage end;

the driving module comprises a first driving unit and a second driving unit;

The first driving unit is used for providing the first driving signal, and the second driving unit is used for providing the second driving signal.

Optionally, the pixel circuit further includes a reference voltage writing circuit; the driving circuit comprises a driving transistor, the initializing circuit comprises a first control transistor, the data writing circuit comprises a second control transistor, the reference voltage writing circuit comprises a third control transistor, and the third energy storage circuit comprises a storage capacitor;

the control electrode of the first control transistor is electrically connected with the first driving control end, the first electrode of the first control transistor is electrically connected with the initial voltage end, and the second electrode of the first control transistor is electrically connected with the first electrode of the light-emitting element;

the control electrode of the second control transistor is electrically connected with the second driving control end, the first electrode of the second control transistor is electrically connected with the data line, and the second electrode of the second control transistor is electrically connected with the control electrode of the driving transistor;

the grid electrode of the third control transistor is electrically connected with a third driving control end, the first electrode of the third control transistor is electrically connected with a reference voltage end, and the second electrode of the third control transistor is electrically connected with the control electrode of the driving transistor;

A first end of the storage capacitor is electrically connected with the grid electrode of the driving transistor, and a second end of the storage capacitor is electrically connected with the first electrode of the light-emitting element;

the first electrode of the driving transistor is electrically connected with the fourth voltage end, and the second electrode of the driving transistor is electrically connected with the first electrode of the light-emitting element; the second pole of the light emitting element is electrically connected with the fifth voltage terminal.

The driving module, the driving method and the display device provided by the embodiment of the invention can reduce the number of the adopted pull-down control ends, are beneficial to realizing a narrow frame, and prevent the overlapping of the overline and the signal line.

Drawings

FIG. 1 is a schematic view of a partition of an effective display area of a display panel;

FIG. 2 is a schematic diagram of a first driving module including a first driving circuit with two stages and a second driving module including a first driving circuit with two stages according to at least one embodiment of the present invention;

FIG. 3 is a block diagram of at least one embodiment of an a-th driving circuit in a driving module according to the present invention;

FIG. 4 is a block diagram of at least one embodiment of an a-th driving circuit in a driving module according to the present invention;

FIG. 5 is a block diagram of at least one embodiment of an a-th driving circuit in a driving module according to the present invention;

FIG. 6 is a circuit diagram of at least one embodiment of an a-th driving circuit in a driving module according to the present invention;

FIG. 7 is a circuit diagram of at least one embodiment of an a-th driving circuit in a driving module according to the present invention;

fig. 8 is a circuit diagram of a last stage first driving circuit 81 in a first driving module included in a first driving unit and a circuit diagram of a last stage second driving circuit 82 in a first driving module included in a second driving unit in a driving module according to at least one embodiment of the present invention;

FIG. 9 is a schematic diagram of a driving circuit corresponding to two partitions in a driving module according to at least one embodiment of the invention;

FIG. 10 is a block diagram of a driving circuit corresponding to a first partition in a driving module according to at least one embodiment of the present invention;

fig. 11 is a timing diagram of operation of the first driving module in the first driving unit and the first driving module in the second driving unit shown in fig. 10;

FIG. 12 is a timing diagram of a common control end of a final row of three partitions (the three partitions are a first partition, a second partition, and a B partition, B is a positive integer) in a driving module according to at least one embodiment of the present invention;

FIG. 13 is a block diagram of at least one embodiment of a pixel circuit in a display device according to the present invention;

FIG. 14 is a circuit diagram of at least one embodiment of the pixel circuit;

FIG. 15 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 14.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The driving module is used for providing driving signals for a plurality of rows and columns of pixel circuits included in the display panel; c is an integer greater than 1, and the effective display area of the display panel comprises B subareas, wherein B is a positive integer; at least one row of C column pixel circuits are arranged in the subarea;

the a-th driving circuit comprises a reset control end and a first reset circuit;

In the driving module of the embodiment of the invention, the reset control end of the last stage driving circuit in the b-th driving module included in the a-th driving unit is electrically connected with the same b-th pull-down control end, and receives the corresponding reset control signal provided by the b-th pull-down control end, so as to optimize the driving signal line and the time sequence, realize the narrow frame of the display product and reduce the driving IC (integrated circuit) Passline, and prevent the occurrence of the overlapping of the overline and the signal line.

In at least one embodiment of the present invention, the pass lines are signal lines of the driving IC, different signals need to use different pass lines, and the number of pass lines that need to be used by the same signal is also different (the number of pass lines that need to be used by the same signal is related to the signal driving capability, for example, a clock signal may only need one pass line, but two pass lines are needed for the first high voltage signal provided by the first high voltage terminal VGH of the current.

In at least one embodiment of the present invention, the driving module may further include at least one driving unit in addition to the a driving units, where the at least one driving unit may also provide driving signals for the pixel circuits in each partition, but the at least one driving unit and the a driving units do not share a pull-down control terminal.

In the related art, the driving module includes at least two driving units (a driving units, a is an integer greater than 1), each driving unit being respectively configured to provide a different driving signal; the effective display area of the display panel may include B partitions (B is a positive integer), each partition is controlled by a corresponding driving module, a last stage driving circuit in a B driving module corresponding to the B partition in at least two driving units is electrically connected with a corresponding pull-down control end, so that the number of pull-down control ends adopted by the related driving modules is a×b, and the reset control signals provided by the pull-down control ends are provided by COF (chip on film), which occupies more COF (chip on film) Passline resources, increases COF cost, is unfavorable for realizing a narrow frame, and is easy to generate conditions of line crossing and signal overlapping. Based on this, in the embodiment of the present invention, the reset control end of the last stage of driving circuit in the b-th driving module included in the a-th driving unit is set to be electrically connected with the same b-th pull-down control end, so as to reduce the number of pull-down control ends used, facilitate the realization of a narrow frame, and prevent the occurrence of the overlapping of the overline and the signal line.

In at least one embodiment of the present invention, the B partitions are sequentially disposed along the extending direction of the data line.

The driving module provided by at least one embodiment of the invention can save B pull-down control ends while ensuring the normal function of the driving circuit, reduce the number and cost of COF signal lines, improve the panel yield, for example, realize narrow-frame display products, and provide technical support for intelligent partition display.

In at least one embodiment of the present invention, a is taken as an example of a2, but not limited thereto. In practice, a may also be equal to 1, 3, 4, or other positive integer.

As shown in fig. 1, in at least one embodiment of the present invention, the effective display area of the display panel may include 9 partitions: a first partition A1, a second partition A2, a third partition A3, a fourth partition A4, a fifth partition A5, a sixth partition A6, a seventh partition A7, an eighth partition A8, and a ninth partition A9;

in fig. 1, a first driving module included in a first driving unit is denoted by G11, and a first driving module included in a second driving unit is denoted by G12; g11 is configured to provide a corresponding first driving signal for at least one row of pixel circuits located in the first partition A1, and G12 is configured to provide a corresponding second driving signal for at least one row of pixel circuits located in the first partition A1;

A second driving module denoted by G21 and included in the first driving unit, and a second driving module denoted by G22 and included in the second driving unit; g21 is configured to provide a corresponding first driving signal for at least one row of pixel circuits located in the second partition A2, and G22 is configured to provide a corresponding second driving signal for at least one row of pixel circuits located in the second partition A2;

a third driving module, denoted by G31, comprised by the first driving unit, and a third driving module, denoted by G32, comprised by the second driving unit; g31 is configured to provide a corresponding first driving signal for at least one row of pixel circuits located in the third partition A3, and G32 is configured to provide a corresponding second driving signal for at least one row of pixel circuits located in the third partition A3;

a fourth driving module denoted by G41 and included in the first driving unit, and a fourth driving module denoted by G42 and included in the second driving unit; g41 is used for providing corresponding first driving signals for at least one row of pixel circuits in the fourth partition A4, and G42 is used for providing corresponding second driving signals for at least one row of pixel circuits in the fourth partition A4;

A fifth driving module denoted by G51 and included in the first driving unit, and a fifth driving module denoted by G52 and included in the second driving unit; g51 is configured to provide a corresponding first driving signal for at least one row of pixel circuits located in the fifth partition A5, and G52 is configured to provide a corresponding second driving signal for at least one row of pixel circuits located in the fifth partition A5;

a sixth driving module, denoted by G61, comprised by the first driving unit, and a sixth driving module, denoted by G62, comprised by the second driving unit; g61 is used for providing corresponding first driving signals for at least one row of pixel circuits located in the sixth partition A6, and G62 is used for providing corresponding second driving signals for at least one row of pixel circuits located in the sixth partition A6;

a seventh driving module denoted by G71 and included in the first driving unit, and a seventh driving module denoted by G72 and included in the second driving unit; g71 is used for providing corresponding first driving signals for at least one row of pixel circuits in the seventh partition A7, and G72 is used for providing corresponding second driving signals for at least one row of pixel circuits in the seventh partition A7;

An eighth driving module denoted by G81 and included in the first driving unit, and an eighth driving module denoted by G82 and included in the second driving unit; g81 is used for providing corresponding first driving signals for at least one row of pixel circuits in the eighth partition A8, and G82 is used for providing corresponding second driving signals for at least one row of pixel circuits in the eighth partition A8;

a ninth driving module denoted by G91 and included in the first driving unit, and a ninth driving module denoted by G92 and included in the second driving unit; g91 is configured to provide a corresponding first driving signal for at least one row of pixel circuits located in the ninth partition A9, and G92 is configured to provide a corresponding second driving signal for at least one row of pixel circuits located in the ninth partition A9.

In fig. 1, a signal providing circuit provided on a COF (chip on film) is denoted by F1, and the signal providing circuit may be used to provide signals such as a clock signal, a start signal, a voltage signal, and a reset control signal to the driving module.

As shown in fig. 1, A2, A3, A4, A5, A6, A7, A8 and A9 are sequentially arranged along the extending direction of the data line, where the extending direction of the data line may be a vertical direction, but not limited thereto.

In at least one embodiment shown in FIG. 1, B is equal to 9 and A is equal to 2;

the driving module comprises a first driving unit and a second driving unit, wherein the first driving unit comprises nine first driving modules, and the second driving unit comprises nine second driving modules;

nine first driving modules included in the first driving unit respectively provide corresponding first driving signals for pixel circuits located in nine partitions, and nine second driving modules included in the second driving unit respectively provide corresponding second driving signals for pixel circuits located in nine partitions.

As shown in fig. 2, in at least one embodiment of the present invention, a first driving module included in a first driving unit includes a two-stage first driving circuit; the first driving module included in the second driving unit comprises a two-stage first driving circuit;

a first-stage first driving circuit in a first driving module included in the first driving unit, which is denoted by S11, and a second-stage first driving circuit in a first driving module included in the first driving unit, which is denoted by S21;

a first-stage second drive circuit in the first drive module included in the second drive unit, denoted by S12, and a second-stage second drive circuit in the first drive module included in the second drive unit, denoted by S22;

S21 is the last-stage first driving circuit in the first driving module included in the first driving unit, S22 is the last-stage second driving circuit in the first driving module included in the second driving unit;

as shown in fig. 2, the reset control terminal of S21 and the reset control terminal of S22 are electrically connected to the first pull-down control terminal STD1, so as to reduce the number of pull-down control terminals electrically connected to the driving module.

As shown in fig. 3, at least one embodiment of the a-th driving circuit includes a reset control terminal STD and a first reset circuit 31;

the first reset circuit 31 is electrically connected to the corresponding reset control terminal STD, the corresponding first node Q, and the first voltage terminal V1, and is configured to control the communication between the first node Q and the first voltage terminal V1 under the control of the reset control signal provided by the reset control terminal STD, so as to reset the potential of the first node Q.

In at least one embodiment of the present invention, the first voltage terminal V1 may be a first low voltage terminal or a ground terminal, but is not limited thereto.

In at least one embodiment of the present invention, the carry signal output circuit may be further electrically connected to a corresponding output clock signal output terminal and a second voltage terminal, and configured to control, under control of a potential of the first node, communication between the carry signal output terminal and the output clock signal output terminal, and control, under control of a potential of the second node, communication between the carry signal output terminal and the second voltage terminal.

In a specific implementation, the a-th driving circuit may further include a carry signal output terminal and a carry signal output circuit; the carry signal output circuit is controlled to output a carry signal through the carry signal output end under the control of the potential of the first node and the potential of the second node; the reset control end of the driving circuit except the last stage driving circuit in each driving module included in each driving unit is electrically connected with the carry signal output end of the driving circuit of the adjacent next stage.

In at least one embodiment of the present invention, the a-th driving circuit further includes a driving signal output terminal and a driving signal output circuit;

In at least one embodiment of the present invention, the driving signal output circuit may be further electrically connected to a corresponding output clock signal output terminal and a second voltage terminal, and configured to control, under control of a potential of the first node, communication between the driving signal output terminal and the output clock signal output terminal, and control, under control of a potential of the second node, communication between the driving signal output terminal and the second voltage terminal.

In specific implementation, the cascade connection can be performed through the driving signal output end, and the a-th driving circuit can also comprise a driving signal output end and a driving signal output circuit; the driving signal output circuit controls the driving signal output end to output a corresponding driving signal under the control of the potential of the first node and the potential of the second node; the reset control end of the driving circuit except the last stage driving circuit in each driving module included in each driving unit is electrically connected with the driving signal output end of the adjacent next stage driving circuit.

In at least one embodiment of the present invention, when each driving circuit includes a driving signal output terminal and a carry signal output terminal, the driving circuits may be cascaded by a carry signal, and when each driving circuit includes a driving signal output terminal, but does not include a carry signal output terminal, the driving circuits may be cascaded by a driving signal.

Optionally, the first reset circuit includes a first transistor;

In at least one embodiment of the present invention, the a-th driving circuit may further include an input circuit, a second reset circuit, a second node control circuit, a third reset circuit, a first tank circuit, and a second tank circuit;

In at least one embodiment of the present invention, the second node control circuit may be further electrically connected to a second voltage terminal, and is configured to control, under control of the control clock signal, communication between the second node and the control clock terminal, and control, under control of a potential of the first node, the second node to be electrically connected to the second voltage terminal.

In a specific implementation, the a-th driving circuit may further include an input circuit, a second reset circuit, a second node control circuit, a third reset circuit, a first energy storage circuit, and a second energy storage circuit; the input circuit controls the potential of the first node under the control of an input signal, and the second reset circuit resets the potential of the first node under the control of a frame reset signal; the third reset circuit resets the potential of the first node under the control of the potential of the second node; the second node control circuit controls the potential of the second node under the control of the control clock signal and the potential of the first node.

In at least one embodiment of the present invention, the third voltage terminal may be a first high voltage terminal, and the second voltage terminal may be a first low voltage terminal, but not limited thereto.

As shown in fig. 4, on the basis of at least one embodiment of the a-th driving circuit shown in fig. 3, the a-th driving circuit may further include an input circuit 41, a second reset circuit 42, a second node control circuit 43, a third reset circuit 44, a first tank circuit 45, a second tank circuit 46, a driving signal output circuit 47, and a driving signal output terminal ga_out;

the input circuit 41 is electrically connected to the input terminal STU, the third voltage terminal V3, and the first node Q, and is configured to control the communication between the first node Q and the third voltage terminal V3 under the control of an input signal provided by the input terminal STU;

the second reset circuit 42 is electrically connected to the frame reset terminal Trs, the first node Q, and the second voltage terminal V2, and is configured to control communication between the first node Q and the second voltage terminal V2 under control of a frame reset signal provided by the frame reset terminal Trs;

the third reset circuit 44 is electrically connected to the second node QB, the first node Q, and the second voltage terminal V2, and is configured to control communication between the first node Q and the second voltage terminal V2 under control of a potential of the second node QB;

The second node control circuit 43 is electrically connected to the first node Q, the second node QB, the control clock signal terminal CLK2, and the second voltage terminal V2, and is configured to control communication between the second node QB and the control clock signal terminal CLK2 under control of a control clock signal provided by the control clock signal terminal CLK2, and control communication between the second node QB and the second voltage terminal V2 under control of a potential of the first node Q;

the first tank circuit 45 is electrically connected to the first node Q, and is configured to store electrical energy;

the second tank circuit 46 is electrically connected to the second node QB, and is configured to store electrical energy;

the driving signal output circuit 47 is electrically connected to the first node Q, the corresponding second node QB, the driving signal output terminal ga_out, the output clock signal terminal CLK1, and the second voltage terminal V2, respectively, and is configured to control, under the control of the potential of the first node Q, the communication between the driving signal output terminal ga_out and the output clock signal terminal CLK1, and control, under the control of the potential of the second node QB, the communication between the driving signal output terminal ga_out and the second voltage terminal V2, so as to control the driving signal output terminal ga_out to output a corresponding driving signal.

At least one embodiment of the a-th driving circuit shown in fig. 4 includes only the driving signal output terminal ga_out, and does not include the carry signal output terminal, and the reset control terminal of the driving circuit except the last driving circuit among the b-th driving modules included in the a-th driving unit is electrically connected to the driving signal output terminal of the adjacent next driving circuit.

As shown in fig. 5, on the basis of at least one embodiment of the a-th driving circuit shown in fig. 4, the a-th driving circuit may further include a carry signal output terminal ga_cr and a carry signal output circuit 51;

the carry signal output circuit 51 is electrically connected to the first node Q, the second node QB, the carry signal output terminal ga_cr, the output clock signal terminal CLK1, and the second voltage terminal V2, and is configured to control communication between the carry signal output terminal ga_cr and the output clock signal terminal CLK1 under control of the potential of the first node Q, and control communication between the carry signal output terminal ga_cr and the second voltage terminal V2 under control of the potential of the second node QB, so as to control output of a carry signal through the carry signal output terminal ga_cr;

at least one embodiment of the a-th driving circuit shown in fig. 5 includes a driving signal output terminal ga_out and a carry signal output terminal ga_cr, and a reset control terminal of a driving circuit except for a last stage driving circuit in a b-th driving module included in the a-th driving unit is electrically connected to a carry signal output terminal of an adjacent next stage driving circuit.

Optionally, the input circuit includes a sixth transistor;

the second reset circuit includes a seventh transistor;

the third reset circuit includes an eighth transistor;

As shown in fig. 6, on the basis of at least one embodiment of the a-th driving circuit shown in fig. 4, the first reset circuit 31 includes a first transistor T1;

the gate of the first transistor T1 is electrically connected to the reset control terminal STD, the source of the first transistor T1 is electrically connected to the first node Q, and the drain of the first transistor T1 is electrically connected to the first low voltage terminal VGL;

the driving signal output circuit 47 includes a fourth transistor T4 and a fifth transistor T5;

the gate of the fourth transistor T4 is electrically connected to the first node Q, the source of the fourth transistor T4 is electrically connected to the corresponding output clock signal terminal CLK1, and the drain of the fourth transistor T4 is electrically connected to the driving signal output terminal ga_out;

the gate of the fifth transistor T5 is electrically connected to the second node QB, the source of the fifth transistor T5 is electrically connected to the driving signal output terminal ga_out, and the drain of the fifth transistor T5 is electrically connected to the first low voltage terminal VGL;

The input circuit 41 includes a sixth transistor T6;

the gate of the sixth transistor T6 is electrically connected to the input terminal STU, the source of the sixth transistor T6 is electrically connected to the first high voltage terminal VGH, and the drain of the sixth transistor T6 is electrically connected to the first node Q;

the second reset circuit 42 includes a seventh transistor T7;

a gate of the seventh transistor T7 is electrically connected to the frame reset terminal Trs, a source of the seventh transistor T7 is electrically connected to the first node Q, and a drain of the seventh transistor T7 is electrically connected to the first low voltage terminal VGL;

the third reset circuit 44 includes an eighth transistor T8;

a gate of the eighth transistor T8 is electrically connected to the second node QB, a source of the eighth transistor T8 is electrically connected to the first node Q, and a drain of the eighth transistor T8 is electrically connected to the first low voltage terminal VGL;

the second node control circuit 43 includes a ninth transistor T9 and a tenth transistor T10;

a gate of the ninth transistor T9 and a source of the ninth transistor T9 are electrically connected to the control clock signal terminal CLK2, and a drain of the ninth transistor T9 is electrically connected to the second node QB;

A gate of the tenth transistor T10 is electrically connected to the first node Q, a source of the tenth transistor T10 is electrically connected to the second node QB, and a drain of the tenth transistor T10 is electrically connected to the first low voltage terminal VGL;

the first tank circuit 45 includes a first capacitor C1, and the second tank circuit 46 includes a second capacitor C2;

a first end of the first capacitor C1 is electrically connected to the first node Q, and a second end of the first capacitor C1 is electrically connected to the driving signal output terminal ga_out;

the first end of the second capacitor C2 is electrically connected to the second node QB, and the second end of the second capacitor C2 is electrically connected to the first low voltage terminal VGL.

In at least one embodiment of the a-th driving circuit shown in fig. 6, the first voltage terminal and the second voltage terminal are both the first low voltage terminal VGL, and the third voltage terminal is the first high voltage terminal VGH, but not limited thereto.

As shown in fig. 7, on the basis of at least one embodiment of the a-th driving circuit shown in fig. 6, at least one embodiment of the a-th driving circuit further includes a carry signal output terminal ga_cr and a carry signal output circuit 51;

the carry signal output circuit 51 includes a second transistor T2 and a third transistor T3;

The grid electrode of the second transistor T2 is electrically connected with the first node Q, the source electrode of the second transistor T2 is electrically connected with a corresponding output clock signal end CLK1, and the drain electrode of the second transistor T2 is electrically connected with the carry signal output end Ga_CR;

the gate of the third transistor T3 is electrically connected to the second node QB, the source of the third transistor T3 is electrically connected to the carry signal output terminal ga_cr, and the drain of the third transistor T3 is electrically connected to the first low voltage terminal VGL.

As shown in fig. 8, reference numeral 81 is a last stage first driving circuit in the first driving module included in the first driving unit, and reference numeral 82 is a last stage second driving circuit in the first driving module included in the second driving unit;

the first driving unit includes a structure of a last stage first driving circuit 81 in the first driving module as shown in fig. 6,

the second driving unit includes a structure of a second driving circuit 82 of the last stage in the first driving module as shown in fig. 6;

in fig. 8, the reference sign STD1 is a first pull-down control terminal, and the first pull-down control terminal STD1 is electrically connected to a reset control terminal in a last stage first driving circuit 81 in a first driving module included in the first driving unit and a reset control terminal in a last stage second driving circuit 82 in the first driving module included in the second driving unit, and is used for providing a reset control signal for the last stage first driving circuit 81 in the first driving module included in the first driving unit and the last stage second driving circuit 82 in the first driving module included in the second driving unit;

In fig. 8, the frame reset terminal denoted by Trs, the first input terminal denoted by g1_stu, the first control clock signal terminal denoted by g1_clk2, the first node denoted by g1_q, the first output clock signal terminal denoted by g1_clk1, the first driving signal output terminal denoted by g1_out, the first second node denoted by g1_qb, the first low voltage terminal denoted by VGL, and the first high voltage terminal denoted by VGH; the second input terminal is denoted by g2_stu, the second control clock signal terminal is denoted by g2_clk2, the second first node is denoted by g2_q, the second output clock signal terminal is denoted by g2_clk1, the second node is denoted by g2_qb, and the second drive signal output terminal is denoted by g2_out.

In fig. 9, driving circuits corresponding to two partitions are shown: the driving circuit corresponding to the first partition and the driving circuit corresponding to the A partition, wherein A is an integer greater than 1.

As shown in fig. 9, the driving module includes a first driving unit and a second driving unit;

the first driving module in the first driving unit comprises a first-stage first driving circuit S11 and a second-stage first driving circuit S21;

The first driving module in the second driving unit comprises a first-stage second driving circuit S12 and a second-stage second driving circuit S22;

the A-th driving module in the first driving unit comprises an N-th first driving circuit SN1 and an N+1th first driving circuit SN+11;

the A-th driving module in the second driving unit comprises an N-th level second driving circuit SN2 and an N+1th level second driving circuit SN+12;

n is an integer greater than 1.

In fig. 9, a control circuit denoted by S11 and K11, a control circuit denoted by S21 and K12, a control circuit denoted by S12 and K22, a control circuit denoted by SN1 and KN1, a control circuit denoted by sn+11 and kn+11, a control circuit denoted by SN2 and kn+12, respectively, are illustrated.

As shown in fig. 9, the input terminal of S11 is connected to a first start signal g1_stu (1), the reset control terminal of S11 is electrically connected to a carry signal output terminal g1_cr (2) of S21, S11 is electrically connected to a first output clock signal terminal g1_clk1 (1) and a first control clock signal terminal g1_clk2 (1), a first node in S11 is denoted as g1_q (1), a second node in S11 is denoted as g1_qb (1), a driving signal output terminal of S11 is denoted as g1_out (1), and a carry signal output terminal of S11 is denoted as g1_cr (1), respectively;

The input end of S21 is electrically connected with G1_CR (1), the reset control end of S21 is electrically connected with a first pull-down control end STD1, S21 is respectively electrically connected with a second first output clock signal end G1_CLK1 (2) and a second first control clock signal end G1_CLK2 (2), a first node in S21 is marked as G1_Q (2), a second node in S21 is marked as G1_QB (2), a driving signal output end of S21 is marked as G1_OUT (2), and a carry signal output end of S21 is marked as G1_CR (2);

the input end of S12 is connected with a first second initial signal G2_STU (1), the reset control end of S12 is electrically connected with a carry signal output end G2_CR (2) of S22, S12 is respectively electrically connected with a first second output clock signal end G2_CLK1 (1) and a first second control clock signal end G2_CLK2 (1), a first node in S12 is marked as G2_Q (1), a second node in S12 is marked as G2_QB (1), a driving signal output end of S12 is marked as G2_OUT (1), and a carry signal output end of S12 is marked as G2_CR (1);

the input end of S22 is electrically connected with G2-CR (1), the reset control end of S22 is electrically connected with a first pull-down control end STD1, S22 is respectively electrically connected with a second output clock signal end G2-CLK 1 (2) and a second control clock signal end G2-CLK 2 (2), a first node in S22 is marked as G2-Q (2), a second node in S22 is marked as G2-QB (2), a driving signal output end of S22 is marked as G2-OUT (2), and a carry signal output end of S22 is marked as G2-CR (2);

The input end of the SN1 is connected with an A first start signal G1_STU (A), the reset control end of the SN1 is electrically connected with a carry signal output end G1_CR (N+1) of SN+11, the SN1 is respectively electrically connected with an N first output clock signal end G1_CLK1 (N) and an N first control clock signal end G1_CLK2 (N), a first node in the SN1 is marked as G1_Q (N), a second node in the SN1 is marked as G1_QB (N), a driving signal output end of the SN1 is marked as G1_OUT (N), and a carry signal output end of the SN1 is marked as G1_CR (N);

the input end of SN+11 is electrically connected with G1_CR (N), the reset control end of SN+11 is electrically connected with the A-th pull-down control end STDA, SN+11 is respectively electrically connected with the N+1st first output clock signal end G1_CLK1 (N+1) and the N+1st first control clock signal end G1_CLK2 (N+1), a first node in SN+11 is marked as G1_Q (N+1), a second node in SN+11 is marked as G1_QB (N+1), the driving signal output end of SN+11 is marked as G1_OUT (N+1), and the carry signal output end of SN+11 is marked as G1_CR (N+1);

the input end of the SN2 is connected with an A second initial signal G2_STU (A), the reset control end of the SN2 is electrically connected with a carry signal output end G2_CR (N+1) of SN+12, the SN2 is respectively electrically connected with an N second output clock signal end G2_CLK1 (N) and an N second control clock signal end G2_CLK2 (N), a first node in the SN2 is marked as G2_Q (N), a second node in the SN2 is marked as G2_QB (N), a driving signal output end of the SN2 is marked as G2_OUT (N), and a carry signal output end of the SN2 is marked as G2_CR (N);

The input terminal of sn+12 is electrically connected to g2_cr (n+1), the reset control terminal of sn+12 is electrically connected to the a-th pull-down control terminal STDA, sn+12 is electrically connected to the n+1st second output clock signal terminal g2_clk1 (n+1) and the n+1st second control clock signal terminal g2_clk2 (n+1), a first node in sn+12 is denoted as g2_q (n+1), a second node in sn+12 is denoted as g2_qb (n+1), the driving signal output terminal of sn+12 is denoted as g2_out (n+1), and the carry signal output terminal of sn+12 is denoted as g2_cr (n+1), respectively.

In at least one embodiment shown in FIG. 9, G1_CLK1 (1) and G1_CLK1 (N) may be connected to a first clock signal G1_CLKA, G1_CLK1 (2) and G1_CLK1 (N+1) may be connected to a first second clock signal G1_CLKB;

g1_clk2 (1) and g1_clk2 (N) may access the first second clock signal g1_clkb, g1_clk2 (2) and g1_clk2 (n+1) may access the first clock signal g1_clka;

g2_clk1 (1) and g2_clk1 (N) may have access to a second first clock signal g2_clka, g2_clk1 (2) and g2_clk1 (n+1) may have access to a second clock signal g2_clkb;

g2_clk2 (1) and g2_clk2 (N) may have access to the second clock signal g2_clkb, g2_clk2 (2) and g2_clk2 (n+1) may have access to the second first clock signal g2_clka.

In at least one embodiment of the present invention, g1_clka and g1_clkb may be inverted with respect to each other, and g2_clka and g2_clkb may be inverted with respect to each other;

in the same driving module, the output clock signals accessed by the adjacent two-stage driving circuits can be mutually inverted, and the control clock signals accessed by the adjacent two-stage driving circuits can be mutually inverted;

but is not limited thereto.

In fig. 10, a driving circuit corresponding to the first partition is shown;

as shown in fig. 10, the driving module includes a first driving unit and a second driving unit; a first driving module in a first driving unit respectively provides first driving signals for a plurality of rows of pixel circuits positioned in the first partition, and a first driving module in a second driving unit respectively provides second driving signals for a plurality of rows of pixel circuits positioned in the first partition;

the first driving module in the first driving unit comprises an M-stage first driving circuit; the first driving module in the second driving unit comprises an M-stage second driving circuit; m is an integer greater than 2;

a first-stage first driving circuit included in a first driving module in the first driving unit is denoted as S11, a second-stage first driving circuit included in the first driving module in the first driving unit is denoted as S21, and an mth-stage first driving circuit included in the first driving module in the first driving unit is denoted as SM1;

The first-stage second driving circuit included in the first driving module in the second driving unit is denoted as S12, the second-stage second driving circuit included in the first driving module in the second driving unit is denoted as S22, and the mth-stage second driving circuit included in the first driving module in the second driving unit is denoted as SM2;

s11, S21, SM1, S12, S22, and SM2 are all electrically connected to the frame reset terminal Trs;

as shown in fig. 10, the input terminal of S11 is connected to the first start signal g1_stu, the reset control terminal of S11 is electrically connected to the driving signal output terminal g1_out (2) of S21, S11 is electrically connected to the first output clock signal terminal g1_clk1 (1) and the first control clock signal terminal g1_clk2 (1), the first node in S11 is denoted as g1_q (1), the second node in S11 is denoted as g1_qb (1), and the driving signal output terminal of S11 is denoted as g1_out (1), respectively;

the input end of S21 is electrically connected with the G1_OUT (1), the reset control end of S21 is electrically connected with the driving signal output end G1_OUT (3) of a third-stage first driving circuit included in a first driving module in the first driving unit, and S21 is respectively electrically connected with a second first output clock signal end G1_CLK1 (2) and a second first control clock signal end G1_CLK2 (2); a first node in S21 is denoted as g1_q (2), a second node in S21 is denoted as g1_qb (2), and a driving signal output terminal of S21 is denoted as g1_out (2);

The input end of the SM1 is electrically connected with a driving signal output end (not shown in fig. 10) of an M-1 stage first driving circuit included in a first driving module in the first driving unit, the reset control end of the SM1 is electrically connected with a first pull-down control end STD1, and the SM1 is electrically connected with an M first output clock signal end g1_clk1 (M) and an M first control clock signal end g1_clk2 (M) respectively; a first node in SM1 is denoted as g1_q (M), a second node in SM1 is denoted as g1_qb (M), and a driving signal output terminal of SM1 is denoted as g1_out (M);

the input end of the S12 is connected with a second initial signal G2_STU, the reset control end of the S12 is electrically connected with a driving signal output end G2_OUT (2) of the S22, the S12 is respectively electrically connected with a first second output clock signal end G2_CLK1 (1) and a first second control clock signal end G2_CLK2 (1), a first node in the S12 is marked as G2_Q (1), a second node in the S12 is marked as G2_QB (1), and a driving signal output end of the S12 is marked as G2_OUT (1);

the input end of S22 is electrically connected with G2-OUT (1), the reset control end of S22 is electrically connected with a driving signal output end G2-OUT (3) of a third-stage second driving circuit included in a first driving module in the second driving unit, S22 is respectively electrically connected with a second output clock signal end G2-CLK 1 (2) and a second control clock signal end G2-CLK 2 (2), a first node in S22 is marked as G2-Q (2), a second node in S22 is marked as G2-QB (2), and a driving signal output end of S22 is marked as G2-OUT (2);

The input end of SM2 is electrically connected with the driving signal output end (not shown in fig. 10) of the M-1 stage second driving circuit included in the first driving module in the second driving unit, the reset control end of SM2 is electrically connected with the first pull-down control end STD1, SM2 is electrically connected with the M second output clock signal end g2_clk1 (M) and the M second control clock signal end g2_clk2 (M), the first node in SM2 is denoted as g2_q (M), the second node in SM2 is denoted as g2_qb (M), and the driving signal output end of SM2 is denoted as g2_out (M);

in at least one embodiment shown in fig. 10, g1_clk1 (1) may be coupled to a first clock signal g1_clka, g1_clk1 (2)) may be coupled to a first second clock signal g1_clkb;

g1_clk2 (1) can be connected to the first second clock signal g1_clkb, g1_clk2 (2) can be connected to the first clock signal g1_clka;

g2_clk1 (1) can be connected to the second first clock signal g2_clka, g2_clk1 (2) can be connected to the second clock signal g2_clkb;

g2_clk2 (1) can be connected to the second clock signal g2_clkb, g2_clk2 (2) can be connected to the second first clock signal g2_clka.

In at least one embodiment of the present invention, G1_CLKA and G1_CLKB may be inverted with respect to each other, and G2_CLKA and G2_CLKB may be inverted with respect to each other.

Fig. 11 is a timing chart of operation of the first driving module in the first driving unit and the first driving module in the second driving unit shown in fig. 10.

As shown in fig. 11, when the first driving module in the first driving unit and the first driving module in the second driving unit shown in fig. 10 are in operation, the driving cycle may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4, a fifth stage P5, a sixth stage P6, a seventh stage P7, and an eighth stage P8, which are sequentially arranged;

when one frame time starts, trs provide high-voltage signals, discharge first nodes in all driving circuits, and reset the potential of the first nodes;

in the first stage P1, g1_stu is high, the potential of g1_q (1) is charged to high, g1_clka is low, and g1_out (1) outputs a low level signal;

in the second phase P2, g1_clka is at a high level, the potential of g1_q (1) is bootstrapped by coupling, and g1_out (1) outputs a high level signal;

in the third phase P3, g1_clka is low, the potential of the driving signal output by g1_out (1) discharges to low, and the potential of g1_q (1) is coupled to be pulled down;

in the fourth stage P4, the STD1 supplies a high level signal by shifting from row to the last row of the present partition, the potential of g1_q (M) is pulled down to a low level, and the potential of g2_q (M) is maintained at a low level;

In the fifth stage P5, g2_stu is high, the potential of g2_q (1) is charged to high, g2_clka is low, and g2_out (1) outputs a low signal;

in the sixth phase P6, g2_clka is high level, the potential of g2_q (1) is bootstrapped by coupling, and g2_out (1) outputs a high level signal;

in the seventh stage P7, g2_clka is low level, the potential of the driving signal output by g2_out (1) is discharged to low level, and the potential of g2_q (1) is coupled to be pulled down;

in the eighth stage P8, the STD1 supplies a high level signal by shifting from row to the last row of the present partition, and the potential of g2_q (M) is pulled down to a low level, at which time the potential of g1_q (M) is maintained at a low level.

When the first driving module in the first driving unit and the first driving module in the second driving unit shown in fig. 10 are in operation, the first driving circuit of the mth stage included in the first driving module of the first driving unit and the second driving circuit of the mth stage included in the first driving module of the second driving unit share the first pull-down control terminal STD1, and have no influence on the potential of the first node in each operation period.

Fig. 12 shows the common timing sequence of the end row pull-down control terminals of three partitions (the three partitions are a first partition, a second partition and a B partition, and B is a positive integer). In fig. 12, a reference numeral STD1 is a first pull-down control terminal to which a last stage first driving circuit included in a first driving module in the first driving unit and a last stage second driving circuit included in a first driving module in the second driving unit are electrically connected together, a reference numeral STD2 is a second pull-down control terminal to which a last stage first driving circuit included in a second driving module in the first driving unit and a last stage second driving circuit included in a second driving module in the second driving unit are electrically connected together, and a reference numeral STDB is a B pull-down control terminal to which a last stage first driving circuit included in a B driving module in the first driving unit and a last stage second driving circuit included in a B driving module in the second driving unit are electrically connected together;

In fig. 12, the frame reset terminal is labeled Trs, the first clock signal is labeled g1_clka, the first second clock signal is labeled g1_clkb, the second first clock signal is labeled g2_clka, and the second clock signal is labeled g2_clkb;

in fig. 12, a first node in the last stage first driving circuit included in the first driving module in the first driving unit is denoted by g1_q (L1), and a driving signal output terminal in the last stage first driving circuit included in the first driving module in the first driving unit is denoted by g1_out (L1);

a first node in a last stage second driving circuit included in a first driving module in the second driving unit, denoted g2_q (L1), and a driving signal output terminal in a last stage second driving circuit included in a first driving module in the second driving unit, denoted g2_out (L1);

a first node in a last stage first driving circuit included in a second driving module in the first driving unit, denoted by g1_q (L2), and a driving signal output terminal in a last stage first driving circuit included in a second driving module in the first driving unit, denoted by g1_out (L2);

A first node in a last stage second driving circuit included in a second driving module in the second driving unit, denoted g2_q (L2), and a driving signal output terminal in the last stage second driving circuit included in the second driving module in the second driving unit, denoted g2_out (L2);

a first node in a last stage first driving circuit included in a B-th driving module in the first driving unit, denoted by g1_q (LB), and a driving signal output terminal in a last stage first driving circuit included in a B-th driving module in the first driving unit, denoted by g1_out (LB);

the first node of the last stage second driving circuit included in the B-th driving module in the second driving unit is denoted by g2_q (LB), and the driving signal output terminal of the last stage second driving circuit included in the B-th driving module in the second driving unit is denoted by g2_out (LB).

As shown in fig. 12, when the driving circuit corresponding to the three partitions is operated, the driving period may include a first period p1_1, a second period p2_1, a third period p1_2, a fourth period p2_2, a fifth period pb_1, and a sixth period pb_2, which are sequentially set;

in the first period p1_1, STD1 provides a high level signal, the potential of g1_q (L1) is discharged to a low level, the fourth transistor in the last stage first driving circuit included in the first driving module in the first driving unit is controlled to be turned off, and the STD1 is shared by the last stage first driving circuit included in the first driving module in the first driving unit and the last stage second driving circuit included in the first driving module in the second driving unit, so that the STD1 discharges g2_q (L1), the potential of g2_q (L1) is maintained to be a low level, and the fourth transistor in the last stage second driving circuit included in the first driving module in the second driving unit is turned off, thereby enhancing the anti-interference effect;

In the third period p1_2, STD1 provides a high level signal, the potential of g2_q (L1) is discharged to a low level, the fourth transistor in the last stage second driving circuit included in the first driving module in the second driving unit is turned off, and since STD1 is shared by the last stage first driving circuit included in the first driving module in the first driving unit and the last stage second driving circuit included in the first driving module in the second driving unit, STD1 discharges g1_q (L1) at this time, the potential of g1_q (L1) is maintained to a low level, and the last stage first driving circuit included in the first driving module in the first driving unit is continuously turned off, thereby enhancing the anti-interference effect;

in the second period of time p2_1, std2 provides a high voltage signal, the potential of g1_q (L2) discharges to a low level, the fourth transistor in the last stage first driving circuit included in the second driving module in the first driving unit is controlled to be turned off, and the STD2 is shared by the last stage first driving circuit included in the second driving module in the first driving unit and the last stage second driving circuit included in the second driving module in the second driving unit, so that the STD2 discharges g2_q (L2), the potential of g2_q (L2) is maintained to be a low level, and the fourth transistor in the last stage second driving circuit included in the second driving module in the second driving unit is turned off, thereby enhancing the anti-interference effect;

In the fourth period of time p2_2, std2 provides a high level signal, the potential of g2_q (L2) is discharged to a low level, the fourth transistor in the last stage second driving circuit included in the second driving module in the second driving unit is turned off, and since STD2 is shared by the last stage first driving circuit included in the second driving module in the first driving unit and the last stage second driving circuit included in the second driving module in the second driving unit, the STD2 discharges g1_q (L2), the potential of g1_q (L2) is maintained to a low level, and the last stage first driving circuit included in the second driving module in the first driving unit is continuously turned off, thereby enhancing the anti-interference effect;

in the fifth period pb_1, the STDB provides a high level signal, the potential of g1_q (LB) discharges to a low level, the fourth transistor in the last stage first driving circuit included in the B-th driving module in the first driving unit is controlled to be turned off, and since the STDB is shared by the last stage first driving circuit included in the B-th driving module in the first driving unit and the last stage second driving circuit included in the B-th driving module in the second driving unit, the STDB discharges g2_q (LB) at this time, the potential of g2_q (LB) is maintained to be a low level, and the fourth transistor in the last stage second driving circuit included in the B-th driving module in the second driving unit is turned off, thereby enhancing the anti-interference effect;

In the fourth period pb_2, the STDB provides a high level signal, the potential of g2_q (LB) is discharged to a low level, the fourth transistor in the last stage second driving circuit included in the B-th driving module in the second driving unit is turned off, and since the last stage first driving circuit included in the B-th driving module in the first driving unit and the last stage second driving circuit included in the B-th driving module in the second driving unit share the STDB, the STDB discharges g1_q (LB) at this time, the potential of g1_q (LB) is maintained to a low level, and the last stage first driving circuit included in the B-th driving module in the first driving unit is continuously turned off, enhancing the anti-interference effect.

The driving method of the embodiment of the invention is applied to the driving module, and comprises the following steps:

In the driving method of the embodiment of the invention, the reset control end of the last stage driving circuit in the b-th driving module included in the a-th driving unit is set to receive the corresponding reset control signal provided by the same b-th pull-down control end, so as to optimize the driving signal line and the time sequence, realize the narrow frame of the display product and reduce the driving IC (integrated circuit) Passline, and prevent the overlapping of the overline and the signal line.

In at least one embodiment of the present invention, the display period may include a plurality of reset periods; the driving method includes:

The display device provided by the embodiment of the invention comprises the driving module.

The display device according to at least one embodiment of the present invention further includes a display panel, where the display panel includes a plurality of rows and columns of pixel circuits, and C is an integer greater than 1; the pixel circuit comprises a light emitting element, a driving circuit, a data writing circuit, an initializing circuit and a third energy storage circuit;

the driving module comprises a first driving unit and a second driving unit;

In at least one embodiment of the present invention, the fourth voltage terminal may be a second high voltage terminal, and the fifth voltage terminal may be a second low voltage terminal, but not limited thereto.

Optionally, at least one embodiment of the pixel circuit may further include a reference voltage write circuit;

the reference voltage writing circuit is electrically connected with the third driving control end, the reference voltage end and the control end of the driving circuit respectively and is used for writing the reference voltage provided by the reference voltage end into the control end of the driving circuit under the control of a third driving signal provided by the third driving control end.

In a specific implementation, the driving unit for generating the third driving signal does not include a reset control terminal, and thus does not need to share a pull-down control terminal with the first driving unit and the second driving unit. In at least one embodiment of the present invention, when the driving unit for generating the third driving signal includes a reset control terminal, the last driving circuit of each driving module in the driving unit may also share a corresponding pull-down control terminal.

As shown in fig. 13, at least one embodiment of the pixel circuit includes a light emitting element E0, a driving circuit 131, a data writing circuit 132, an initializing circuit 133, a third tank circuit 134, and a reference voltage writing circuit 135;

the initializing circuit 133 is electrically connected to the first driving control terminal G1, the initial voltage terminal I1, and the first electrode of the light emitting element E0, and is configured to control writing the initial voltage provided by the initial voltage terminal I1 into the first electrode of the light emitting element E0 under the control of the first driving signal provided by the first driving control terminal G1;

the data writing circuit 132 is electrically connected to the second driving control terminal G2, the data line D1, and the control terminal of the driving circuit 131, and is configured to control writing of the data voltage provided by the data line D1 into the control terminal of the driving circuit 131 under the control of the second driving signal provided by the second driving control terminal G2;

The third tank circuit 134 is electrically connected to the control terminal of the driving circuit 131, and is configured to store electric energy;

the first end of the driving circuit 131 is electrically connected to the fourth voltage end V4, the second end of the driving circuit 131 is electrically connected to the first pole of the light emitting element E0, and the driving circuit 131 is configured to control the fourth voltage end V4 to communicate with the first pole of the light emitting element E0 under the control of the potential of the control end thereof;

the second electrode of the light-emitting element E0 is electrically connected with a fifth voltage end V5;

the reference voltage writing circuit 135 is electrically connected to the third driving control terminal G3, the reference voltage terminal, and the control terminal of the driving circuit 131, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the control terminal of the driving circuit 131 under the control of the third driving signal provided by the third driving control terminal G3.

In at least one embodiment of the present invention, the light emitting element may be an organic light emitting diode, the first pole of the light emitting element may be an anode, and the second pole of the light emitting element may be a cathode.

In at least one embodiment of the present invention, the first driving unit may be configured to provide a corresponding first driving signal to the first driving control terminal G1, and the second driving unit may be configured to provide a corresponding second driving signal to the second driving control terminal G2.

Optionally, the driving circuit includes a driving transistor, the initializing circuit includes a first control transistor, the data writing circuit includes a second control transistor, the reference voltage writing circuit includes a third control transistor, and the third tank circuit includes a storage capacitor;

As shown in fig. 14, in at least one embodiment of the pixel circuit shown in fig. 13, the light emitting element is an organic light emitting diode O1; the driving circuit 131 includes a driving transistor M0, the initializing circuit 133 includes a first control transistor M1, the data writing circuit 132 includes a second control transistor M2, the reference voltage writing circuit 135 includes a third control transistor M3, and the third tank circuit 134 includes a storage capacitor C0;

the grid electrode of M1 is electrically connected with the first drive control end G1, the source electrode of M1 is electrically connected with the initial voltage end I1, and the drain electrode of M1 is electrically connected with the anode of O1; the initial voltage terminal I1 is used for providing an initial voltage Vini;

the grid electrode of M2 is electrically connected with the second drive control end G2, the source electrode of M2 is electrically connected with the data line D1, and the drain electrode of M2 is electrically connected with the grid electrode of M0;

the grid electrode of M3 is electrically connected with the third drive control end G3, the source electrode of M3 is connected with the reference voltage Vref, and the drain electrode of M3 is electrically connected with the grid electrode of M0;

The first end of C0 is electrically connected with the grid electrode of M0, and the second end of C0 is electrically connected with the anode of O1;

the source of M0 is electrically connected to the second high voltage terminal VDD, and the cathode of O1 is electrically connected to the second low voltage terminal VSS.

In at least one embodiment of the pixel circuit shown in fig. 14, the fourth voltage terminal is the second high voltage terminal VDD, and the fifth voltage terminal is the second low voltage terminal VSS, but not limited thereto.

As shown in fig. 15, at least one embodiment of the pixel circuit shown in fig. 14 may include an initialization stage 151, a potential control stage 152, a data writing stage 153, and a light emitting stage 154, which are sequentially arranged in operation;

in the initialization stage 151, G1 provides a high voltage signal, G2 provides a low voltage signal, G3 provides a high voltage signal, M1 is on, M2 is off, M3 is on, vref is written to the gate of M0, vini is written to the anode of O1 to control O1 not to emit light, and the residual charge on the anode of O1 is cleared;

in the potential control stage 152, G1 provides a low voltage signal, G2 provides a low voltage signal, G3 provides a high voltage signal, M1 is turned off, M2 is turned off, and M3 is turned on to write Vref to the gate of M0;

in the data writing stage 153, G1 provides a low voltage signal, G2 provides a high voltage signal, G3 provides a low voltage signal, M1 is turned off, M2 is turned on, and M3 is turned off to write the data voltage Vdata provided by D1 into the gate of M0;

In the light emitting stage 154, G1, G2 and G3 all provide low voltage signals, M1, M2 and M3 are turned off, and M0 drives O1 to emit light.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims

1. A driving module for providing driving signals for a plurality of rows and columns of pixel circuits included in the display panel; c is an integer greater than 1, and the effective display area of the display panel comprises B subareas, wherein B is a positive integer; at least one row of C column pixel circuits are arranged in the subarea; it is characterized in that the method comprises the steps of,

the driving module comprises A driving units, wherein A is an integer greater than 1; the a-th driving unit is used for respectively providing corresponding a-th driving signals for the pixel circuits in the plurality of rows; a is a positive integer less than or equal to A;

the reset control end of the last-stage driving circuit in the b-th driving module included in the A driving units is electrically connected with the b-th pull-down control end, and the b-th pull-down control end is used for providing corresponding reset control signals for the reset control end of the last-stage driving circuit in the b-th driving module included in the A driving units;

the a-th driving circuit further comprises a carry signal output end and a carry signal output circuit; and/or, the a-th driving circuit further comprises a driving signal output end and a driving signal output circuit;

the reset control end of the driving circuit except the last stage driving circuit in the b driving module included in the A driving units is electrically connected with the carry signal output end of the adjacent next stage driving circuit; or, the reset control end of the driving circuit except the driving circuit of the last stage in the b-th driving module included in the A driving units is electrically connected with the driving signal output end of the driving circuit of the next stage.

2. The drive module of claim 1, wherein the first reset circuit comprises a first transistor;

3. The drive module of claim 1, wherein the a-th drive circuit further comprises a carry signal output terminal and a carry signal output circuit; the carry signal output circuit includes a second transistor and a third transistor;

4. The drive module of claim 1, wherein the a-th drive circuit further comprises a drive signal output and a drive signal output circuit; the driving signal output circuit includes a fourth transistor and a fifth transistor;

5. The drive module of any one of claims 1 to 4, wherein the a-th drive circuit further comprises an input circuit, a second reset circuit, a second node control circuit, a third reset circuit, a first tank circuit, and a second tank circuit;

6. The drive module of claim 5, wherein the input circuit comprises a sixth transistor;

the second reset circuit includes a seventh transistor;

the third reset circuit includes an eighth transistor;

7. A driving method applied to the driving module according to any one of claims 1 to 6, characterized in that the driving method comprises:

8. The driving method of claim 7, wherein the display period includes a plurality of reset periods; the driving method includes:

9. A display device comprising the drive module of any one of claims 1 to 6.

10. The display device of claim 9, further comprising a display panel comprising a plurality of rows C columns of pixel circuits, C being an integer greater than 1; the pixel circuit comprises a light emitting element, a driving circuit, a data writing circuit, an initializing circuit and a third energy storage circuit;

the driving module comprises a first driving unit and a second driving unit;

11. The display device according to claim 10, wherein the pixel circuit further comprises a reference voltage writing circuit; the driving circuit comprises a driving transistor, the initializing circuit comprises a first control transistor, the data writing circuit comprises a second control transistor, the reference voltage writing circuit comprises a third control transistor, and the third energy storage circuit comprises a storage capacitor;