CN114744980A - High-integration active dynamic loop filter - Google Patents

Abstract

The invention relates to a high-integration active dynamic loop filter, which comprises: the filter adopts a double-ring structure of a separated charge pump, replaces a resistor with a switch capacitor, has better precision, subtracts resistance thermal noise, generates constant current with proper proportion in the whole input updating period instead of generating large proportion current in the input phase difference period, obtains more stable control current, and reduces burrs and overshoots. Meanwhile, the double-sampling capacitor structure has higher power supply and substrate noise suppression capability, so that better jitter performance is generated. The sampling reset switch capacitor and the annular dynamic amplifier are adopted, so that the whole filter is realized under low voltage and the current matching of the charge pump is ensured to be possible.

Description

High-integration active dynamic loop filter

Technical Field

The invention belongs to the technical field of filters, and particularly relates to a high-integration active dynamic loop filter.

Background

For the application of an active loop filter which works at ultra-low voltage and requires small area and high integration level, a phase-locked loop frequency synthesizer circuit directly influences the performance of a wireless transceiver, the loop filter is an important module of the frequency synthesizer, and has the functions of time domain integration and frequency domain low-pass filtering, clutter components in comparison voltage output by a phase discriminator can be filtered, and more importantly, when the phase discriminator and a voltage-controlled oscillator are designed, the performance of the whole phase-locked loop can be controlled by adjusting loop filter parameters, so the design quality determines important indexes of phase noise, stray, frequency hopping time and the like of the system, and the phase-locked loop and even the whole wireless transceiver system are greatly contributed.

The loop filter is divided into an active filter and a passive filter, a traditional passive structure needs a large capacitance resistor to realize narrow-band bandwidth, on-chip integration is difficult to realize, the development trend of high performance, low power consumption, small area and high integration level of the current design is contradictory to market requirements, and the most common method for reducing the filter capacitance is to use the active filter. The conventional active filter structure is shown in fig. 1, capacitor C₀、C₁And a resistance R₁And the operational amplifier forms a second-order active filter. Although the conventional structure can also reduce the area of the on-chip capacitor, there are two main disadvantages. First, the location of the loop filter poles must be chosen as a compromise between loop phase margin and jitter performance. Second, the loop damping factor requires a large intrinsic phase to stabilize the zero point separation to keep jitter peaks and transient overshoots at specified maximum values.

In response to the above problem, an improved filter structure is proposed, as shown in fig. 2, which separates the integral path CPI from the proportional path CPP, C_INTIs an integrating capacitance, R₁And C_PROPRespectively, the resistance and capacitance of the proportional path. Allowing greater flexibility in the phase margin design of the loop filter. This structure, however, also has the drawbacks of the conventional filter, and above all, it still generates a large proportion of current during the input phase difference, which results in a large glitch and overshoot of the oscillator control current. In addition at low pressureIt is difficult to ensure good matching of the charge pump currents while significantly compressing the input voltage V of the VCO_CTRL. The charge pump mismatch current is the most important performance index of the charge pump, the noise performance and even the function of the phase-locked loop can be seriously influenced by excessive current mismatch, and simultaneously V_CTRLRequires a larger KVCO, also deteriorates the noise performance, and in addition, the resistor R₁There will also be thermal noise.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a highly integrated active dynamic loop filter. The technical problem to be solved by the invention is realized by the following technical scheme:

the invention provides a high-integration active dynamic loop filter, which comprises: an integrating path, a proportional path, a first integrating capacitor, a second integrating capacitor, and an operational amplifier, wherein,

the integral path and the proportional path both adopt a differential structure, the integral path in an internal symmetrical structure comprises an integral path first differential circuit and an integral path second differential circuit, and the proportional path in an internal symmetrical structure comprises a proportional path first differential circuit and a proportional path second differential circuit;

the input end of the integration path first differential circuit inputs a first integration current, and the output end of the integration path first differential circuit is connected with the first end of the first integration capacitor;

the input end of the proportional path first differential circuit inputs a first proportional current, and the output end of the proportional path first differential circuit is respectively connected with the first end of the first integrating capacitor and the inverting input end of the operational amplifier;

the input end of the second differential circuit of the integration path inputs a second integration current, and the output end of the second differential circuit of the integration path is connected with the first end of the second integration capacitor;

a second proportional current is input to the input end of the proportional path second differential circuit, and the output end of the proportional path second differential circuit is respectively connected with the first end of the second integrating capacitor and the positive phase input end of the operational amplifier;

and the second end of the first integrating capacitor and the second end of the second integrating capacitor are both connected with the output end of the operational amplifier, and the second end of the first integrating capacitor and the second end of the second integrating capacitor are used as the output ends of the filter.

In one embodiment of the present invention, the integration path first differential circuit, the integration path second differential circuit, the proportional path first differential circuit, and the proportional path second differential circuit all employ a switched capacitor structure.

In one embodiment of the invention, the integration path first differential circuit comprises a number of switches, a first capacitance and a second capacitance, wherein,

the first end of the first capacitor is respectively connected with the input end and the voltage end of the first differential circuit of the integration path through corresponding switches, and the second end of the first capacitor is respectively connected with the first end of the first integration capacitor and the voltage end through corresponding switches;

the first end of the second capacitor is connected with the input end of the first differential circuit of the integration path and the voltage end through corresponding switches, and the second end of the second capacitor is connected with the first end of the first integration capacitor and the voltage end through corresponding switches.

In one embodiment of the invention, the proportional path first differential circuit includes a number of switches, a third capacitance, and a fourth capacitance, wherein,

the first end of the third capacitor is respectively connected with the input end of the proportional path first differential circuit and the voltage end through corresponding switches;

a first end of the fourth capacitor is respectively connected with the input end of the proportional path first differential circuit and the voltage end through corresponding switches;

the second end of the third capacitor is respectively connected with the first end of the first integrating capacitor and the inverting input end of the operational amplifier;

and the second end of the fourth capacitor is respectively connected with the first end of the first integrating capacitor and the inverting input end of the operational amplifier.

In one embodiment of the present invention, a switch between the first terminal of the first capacitor and the input terminal of the first differential circuit of the integration path, and a switch between the second terminal of the first capacitor and the voltage terminal are turned on or off according to a first switching signal;

a switch between a first end of the second capacitor and an input end of the first differential circuit of the integration path, and a switch between a second end of the second capacitor and the voltage end, wherein the switch is switched on or switched off according to a second switch signal;

a switch between a first end of the first capacitor and the voltage end and a switch between a second end of the first capacitor and a first end of the first integrating capacitor are switched on or off according to a first reset signal;

and the switch between the first end of the second capacitor and the voltage end and the switch between the second end of the second capacitor and the first end of the first integrating capacitor are switched on or off according to a second reset signal.

In one embodiment of the present invention, a switch between the first end of the third capacitor and the input end of the proportional path first differential circuit is turned on or off according to a first switch signal;

the switch between the first end of the fourth capacitor and the input end of the proportional path first differential circuit is switched on or switched off according to a second switch signal;

a switch between the first end of the third capacitor and the voltage end is switched on or off according to a first reset signal;

and a switch between the first end of the fourth capacitor and the voltage end is switched on or off according to a second reset signal.

In one embodiment of the present invention, the first switching signal and the second switching signal are a pair of two-phase non-overlapping clock signals, and the first reset signal and the second reset signal are a pair of two-phase non-overlapping clock signals;

the operating frequency of the two pairs of clock signals is 1/2 times the frequency of the PFD input reference clock.

Compared with the prior art, the invention has the beneficial effects that:

1. according to the high-integration active dynamic loop filter, a double-capacitor structure is adopted to separate sampling, resetting and phase holding, a double-ring structure for separating a charge pump is adopted, and a switch capacitor is used for replacing a resistor, so that the high-integration active dynamic loop filter has better precision and reduces resistance thermal noise;

2. the high-integration active dynamic loop filter has the advantages that the structure allows the size of the loop capacitor to be selected within a certain range, the design flexibility is improved, and the balance between the size of the capacitor and the jitter of the phase-locked loop is obtained to the maximum extent. The sampling reset loop filter generates constant current with proper proportion in the whole input updating period, but not generates large proportion current in the input phase difference period, so that more stable control current is obtained, and burrs and overshoot are reduced;

3. the high-integration active dynamic loop filter has a double-sampling capacitor structure with higher power supply and substrate noise suppression capability, thereby generating better jitter performance, and enabling the whole filter to realize low voltage and ensuring the current matching of a charge pump to be possible.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Drawings

Fig. 1 is a schematic structural diagram of a conventional second-order active filter according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a dual-ring active filter according to an embodiment of the present invention;

fig. 3 is a block diagram of a structure of a highly integrated active dynamic loop filter according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a highly integrated active dynamic loop filter according to an embodiment of the present invention;

fig. 5 is a schematic diagram illustrating the operation of a highly integrated active dynamic loop filter according to an embodiment of the present invention;

fig. 6 is a timing diagram of the operation of a filter according to an embodiment of the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined object, a highly integrated active dynamic loop filter according to the present invention is described in detail below with reference to the accompanying drawings and the detailed description.

The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.

Example one

Referring to fig. 3 and fig. 4 in combination, fig. 3 is a block diagram of a high-integration active dynamic loop filter according to an embodiment of the present invention; fig. 4 is a schematic structural diagram of a highly integrated active dynamic loop filter according to an embodiment of the present invention. As shown in the figure, the high integration active dynamic loop filter of the present embodiment includes: integration path 1, proportional path 2, first integration capacitor C_INT1A second integrating capacitor C_INT2And an operational amplifier OPA.

The integral path 1 and the proportional path 2 both adopt a differential structure, the integral path 1 in an internal symmetric structure includes an integral path first differential circuit 11 and an integral path second differential circuit 12, and the proportional path 2 in an internal symmetric structure includes a proportional path first differential circuit 21 and a proportional path second differential circuit 22.

Specifically, the first integration current CPI _ INP is input to the input terminal of the integration path first differential circuit 11, and the first integration capacitor C is connected to the output terminal_INT1A first end of (a); the input terminal of the proportional path first differential circuit 21 is inputA proportional current CPP _ INP, the output end is respectively connected with the first integrating capacitor C_INT1And an inverting input of the operational amplifier OPA; the input end of the second differential circuit 12 of the integration path inputs a second integration current CPI _ INN, and the output end is connected with a second integration capacitor C_INT2The first end of (a); the input end of the proportional path second differential circuit 22 inputs the second proportional current CPP _ INN, and the output ends are respectively connected to the second integrating capacitors C_INT2And a non-inverting input of the operational amplifier OPA; first integrating capacitor C_INT1Second terminal and second integrating capacitor C_INT2The second ends of the first and second capacitors are connected with the output end of the operational amplifier OPA and the first integrating capacitor C_INT1Second terminal and second integrating capacitor C_INT2As the output of the filter.

In the present embodiment, the integration path first differential circuit 11, the integration path second differential circuit 12, the proportional path first differential circuit 21, and the proportional path second differential circuit 22 all adopt a switched capacitor structure.

The high-integration-level active dynamic loop filter adopts a double-capacitor structure to separate sampling, resetting and phase keeping, adopts a double-ring structure for separating a charge pump, replaces a resistor with a switched capacitor, can have better precision, and reduces resistance thermal noise.

Further, a specific circuit structure of the high-integration active dynamic loop filter of this embodiment is explained, as shown in fig. 4, in this embodiment, the integration path first differential circuit 11 includes a plurality of switches and a first capacitor C_oddiAnd a second capacitor C_eveni. Wherein the first capacitor C_oddiIs connected to the input terminal and the voltage terminal VCOM of the integration path first differential circuit 11 through corresponding switches, respectively, a first capacitor C_oddiThe second end of the first switch is respectively connected with the first integrating capacitor C through the corresponding switch_INT1Is connected to a voltage terminal VCOM; second capacitor C_eveniRespectively connected to the input terminal and voltage terminal VCOM of the integration path first differential circuit 11 through corresponding switches, a second capacitor C_eveniThe second end of the first switch is respectively connected with the first integrating capacitor C through the corresponding switch_INT1Is connected to a voltage terminal VCOM.

In particular, the first capacitance C_oddiAnd the input of the integration path first differential circuit 11, and a first capacitor C_oddiAnd a voltage terminal VCOM, is turned on or off according to the first switching signal PH 1.

Second capacitor C_eveniAnd the input of the integration path first differential circuit 11, and a second capacitor C_eveniAnd the voltage terminal VCOM, is turned on or off according to the second switching signal PH 2.

A first capacitor C_oddiAnd a voltage terminal VCOM, and a first capacitor C_oddiSecond terminal and first integrating capacitor C_INT1Is closed or opened in response to a first reset signal RES 1.

A second capacitor C_eveniAnd a voltage terminal VCOM, and a second capacitor C_eveniSecond terminal and first integrating capacitor C_INT1Is closed or opened in accordance with the second reset signal RES 2.

Further, the integration path second differential circuit 12 and the integration path first differential circuit 11 form a symmetrical structure, and the circuit structure thereof is similar to that of the integration path first differential circuit 11. In the integration path second differential circuit 12, the first capacitor C_oddiThe second end of the first switch is respectively connected with a second integrating capacitor C through a corresponding switch_INT2Is connected to a voltage terminal VCOM; second capacitor C_eveniThe second ends of the first and second integrating capacitors are respectively connected with a second integrating capacitor C through corresponding switches_INT2Is connected to a voltage terminal VCOM.

Correspondingly, in the second differential circuit 12 of the integration path, the first capacitance C_oddiSecond terminal and second integrating capacitor C_INT2Is closed or opened in response to a first reset signal RES 1. A second capacitor C_eveniSecond terminal of (1) and second integrating capacitor C_INT2Of the first endAnd the switch is switched on or off according to a second reset signal RES 2.

Further, in the present embodiment, the proportional path first differential circuit 21 includes a plurality of switches and a third capacitor C_oddpAnd a fourth capacitance C_evenp. Wherein the third capacitor C_oddpIs connected to the input terminal and the voltage terminal VCOM of the proportional path first differential circuit 21 through the corresponding switch, respectively; fourth capacitance C_evenpIs connected to the input terminal and the voltage terminal VCOM of the proportional path first differential circuit 21 through the corresponding switch, respectively; third capacitor C_oddpSecond ends of the first and second capacitors are respectively connected with a first integrating capacitor C_INT1And an inverting input of the operational amplifier OPA; fourth capacitor C_evenpSecond ends of the first and second capacitors are respectively connected with a first integrating capacitor C_INT1And an inverting input terminal of the operational amplifier OPA.

In particular, the third capacitance C_oddpAnd the input terminal of the proportional path first differential circuit 21, and is switched on or off according to a first switching signal PH 1; fourth capacitor C_evenpAnd the input terminal of the proportional path first differential circuit 21, is closed or opened according to a second switching signal PH 2; third capacitor C_oddpAnd a voltage terminal VCOM, which is turned on or off according to the first reset signal RES 1; fourth capacitor C_evenpAnd a voltage terminal VCOM, which is turned on or off according to the second reset signal RES 2.

Further, the proportional path second differential circuit 22 forms a symmetrical structure with the proportional path first differential circuit 21, and the circuit structure thereof is similar to that of the proportional path first differential circuit 21. In the proportional path second differential circuit 22, the third capacitor C_oddpSecond ends of the first and second integrating capacitors are respectively connected with a second integrating capacitor C_INT2And a non-inverting input of the operational amplifier OPA; fourth capacitor C_evenpSecond ends of the first and second integrating capacitors are respectively connected with a second integrating capacitor C_INT2And a non-inverting input of the operational amplifier OPA.

In this embodiment, the first and second switching signals PH1 and PH2 are a pair of two-phase non-overlapping clock signals, and the first and second reset signals RES1 and RES2 are a pair of two-phase non-overlapping clock signals; the operating frequency of the two pairs of clock signals is 1/2 times the frequency of the PFD input reference clock.

The structure of the high-integration active dynamic loop filter of the embodiment allows the size of the loop capacitor to be selected within a certain range, so that the design flexibility is increased, and the balance between the size of the capacitor and the jitter of the phase-locked loop is obtained to the greatest extent. And the sampling reset loop filter generates constant current with proper proportion in the whole input updating period, but not generates large proportion current in the input phase difference period, so that more stable control current is obtained, and burrs and overshoots are reduced. And the double-sampling capacitor structure has higher power supply and substrate noise suppression capability, thereby generating better jitter performance, realizing the whole filter at low voltage and ensuring the current matching of the charge pump to be possible.

Example two

The present embodiment specifically describes the operation process of the high-integration active dynamic loop filter in the first embodiment. Referring to fig. 5 and fig. 6 in combination, fig. 5 is a schematic diagram illustrating an operation of a highly integrated active dynamic loop filter according to an embodiment of the present invention; fig. 6 is a timing diagram of the operation of a filter according to an embodiment of the present invention.

Timing diagrams of the first and second switch signals PH1 and PH2, the first and second reset signals RES1 and RES2, and UP/DOWN are shown in fig. 6, where the UP/DOWN signals are input signals of the pre-stage charge pump, that is, outputs of the PFD, and are four input signals for controlling the first proportional current CPP _ INP, the first integral current CPI _ INP, the second proportional current CPP _ INN, and the second integral current CPI _ INN.

For convenience of illustration, looking only at the inverting input of the OPA, as shown in fig. 5 (a), PH1/PH2 and RES1/RES2 are two pairs of two non-overlapping two-phase clock signals, respectively, operating at half the frequency of the PFD input reference clock. For each alternate clock cycle, the first capacitor C_oddiAnd a second capacitor C_eveniAnd a firstThree capacitors C_oddpAnd a fourth capacitance C_evenpAlternately discharges without mutual influence. Therefore, two paths controlled by the first switching signal PH1 and the second switching signal PH2 are analyzed separately.

When the first switching signal PH1 is at a high level, the first integrated current CPI _ INP couples to the first capacitor C_oddiCharging a first proportional current CPP _ INP to a third capacitor C_oddpCharging, as shown in (b) of fig. 5, the charge of proportional path 2 is accumulated in first integrating capacitor C_INT1At this time, the control voltage V_Ctrl(i.e., the output voltage VOUT of the filter) is,

at this time, the second switching signal PH2 is at low level, and the second capacitor C_eveniAnd a fourth capacitance C_evenpThe charge on the capacitor is maintained. When the first reset signal RES1 is at a high level, the nodes V1a and V1b shown in (a) of fig. 5 are reset, and the first capacitor C is simultaneously reset_oddiIs accumulated in the first integrating capacitor C_INT1At this time, the voltage is controlled

Similarly, when the second switching signal PH2 is at a high level, the first integrated current CPI _ INP flows to the second capacitor C_eveniCharging a first proportional current CPP _ INP to a fourth capacitor C_evenpCharging, as shown in (C) of FIG. 5, the charge of proportional path 2 is accumulated in first integrating capacitor C_INT1The above. When the second reset signal RES2 is at a high level, the nodes V2a and V2b shown in fig. 5 (a) are reset, and at the same time, the second capacitor C is reset_eveniIs accumulated in the first integrating capacitor C_INT1Upper, control voltage

The results of the two paths are superimposed and the timing diagram of the complete process is shown in fig. 6. It can be seen that, ultimately, the charge of the integration path 1 can be integrated at a first integration levelContainer C_INT1Is continuously accumulated, and the charge on the proportional path 2 is accumulated on the first integrating capacitor C_INT1Since there is no memory, it is equivalent to a resistor, and therefore, the switched capacitor structure of proportional path 2 is implemented instead of a resistor.

In this embodiment, the first capacitor C_oddiSecond capacitance C_eveniA third capacitor C_oddpFourth capacitance C_evenpThe alternative operation, the pulse time of the first reset signal RES1 and the second reset signal RES2 is not strictly limited, the reset signal is easier to generate, the reset signal is also used in the integration path, and after each integration, the first integrating capacitor C is used_INT1The amount of charge on is continuously accumulated, and the control voltage of the VCO (integrating capacitor C)_INTThe output terminal voltage) is continuously increased/decreased, a larger range can be reached, and the nodes V1a, V2a, V1b and V2b connected with the preceding stage charge pump are kept in a small range around VCOM before and after each reset, and can be basically considered to be kept unchanged, so that the contradiction between the matching property of the charge pump and the control voltage range in low voltage is solved, the current mismatch of the charge pump is reduced, the control voltage range is expanded, the voltage-controlled gain of the VCO is reduced, and the noise of the whole phase-locked loop is greatly improved.

Compared with a common sampling reset circuit, the high-integration-level active dynamic loop filter of the embodiment adopts a double-capacitor structure to separate sampling, resetting and phase holding, and the voltages at two ends of the capacitor on the integration path and the proportional path are in different states, namely sampling, resetting and phase holding, through the on and off of the switch controlled by the reset signal. The switches controlled by different reset signals work alternately, the pulse time of the reset signals is not strictly limited, the reset signals are easier to generate, meanwhile, the reset signals are also used on an integration path, after each integration, the electric charge on an integration capacitor is accumulated continuously, the output control voltage is increased/decreased continuously to reach a larger range, and a node connected with a preceding charge pump is kept in a small range around a common mode Voltage (VCOM) before and after each reset and basically can be considered to be kept unchanged, so that the contradiction between the matching of the charge pump and the control voltage range in low voltage is solved, the control voltage range is expanded while the current mismatch of the charge pump is reduced, the value of the KVCO is reduced, and the noise of the whole phase-locked loop is greatly improved.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.

Claims (7)

1. A high integration active dynamic loop filter, comprising: an integration path (1), a proportional path (2), a first integration capacitance (C)_INT1) A second integrating capacitor (C)_INT2) And an operational amplifier (OPA), wherein,

the integral path (1) and the proportional path (2) both adopt a differential structure, the integral path (1) in an internal symmetrical structure comprises an integral path first differential circuit (11) and an integral path second differential circuit (12), and the proportional path (2) in an internal symmetrical structure comprises a proportional path first differential circuit (21) and a proportional path second differential circuit (22);

the input end of the integration path first differential circuit (11) inputs a first integration current (CPI _ INP), and the output end is connected with the first integration capacitor (C)_INT1) A first end of (a);

the input end of the proportional path first differential circuit (21) inputs a first proportional current (CPP _ INP), and the output end is respectively connected with the first integrating capacitor (C)_INT1) And an inverting input of the operational amplifier (OPA);

the input end of the second difference circuit (12) of the integration path inputs a second integration current (CPI _ INN), and the output end is connected with the second integration capacitor (C)_INT2) A first end of (a);

the input end of the proportional path second differential circuit (22) inputs a second proportional current (CPP _ INN), and the output ends are respectively connected with the second integrating capacitors (C)_INT2) And a non-inverting input of the operational amplifier (OPA);

the first integrating capacitor (C)_INT1) And said second integrating capacitor (C)_INT2) Are connected to the output of said operational amplifier (OPA), said first integrating capacitor (C)_INT1) And said second integrating capacitor (C)_INT2) As the output of the filter.

2. The highly integrated active dynamic loop filter of claim 1, wherein the integration path first differential circuit (11), the integration path second differential circuit (12), the proportional path first differential circuit (21), and the proportional path second differential circuit (22) all employ a switched capacitor structure.

3. High integration active dynamic loop filter according to claim 2, characterized in that the integration path first difference circuit (11) comprises several switches, a first capacitance (C)_oddi) And a second capacitance (C)_eveni) Wherein, in the step (A),

the first capacitor (C)_oddi) Is connected to an input terminal and a voltage terminal (VCOM) of said integration path first differential circuit (11) respectively through corresponding switches, said first capacitor (C)_oddi) Respectively with said first integrating capacitor (C) via corresponding switches_INT1) Is connected to the voltage terminal (VCOM);

the second capacitance (C)_eveni) Is connected to the input of the first differential circuit (11) of the integration path and to the voltage terminal (VCOM) respectively via corresponding switches, the second capacitor (C)_eveni) Respectively with said first integrating capacitor (C) via corresponding switches_INT1) Is connected to said voltage terminal (VCOM).

4. High integration active dynamic loop filter according to claim 3, characterized in that the proportional path first differential circuit (21) comprises several switches, a third capacitor (C)_oddp) And a fourth capacitance (C)_evenp) Wherein, in the step (A),

the third capacitance (C)_oddp) Is connected to the input of the proportional path first differential circuit (21) and to the voltage terminal (VCOM) respectively through corresponding switches;

the fourth capacitor (C)_evenp) Is connected to the input of the proportional path first differential circuit (21) and to the voltage terminal (VCOM) respectively through corresponding switches;

the third capacitance (C)_oddp) Are respectively connected with the first integrating capacitors (C)_INT1) And an inverting input of the operational amplifier (OPA);

the fourth capacitor (C)_evenp) Are respectively connected with the first integrating capacitors (C)_INT1) And an inverting input of said operational amplifier (OPA).

5. High-integration active dynamic loop filter according to claim 3, characterized in that the first capacitance (C)_oddi) And an input of said integration path first differential circuit (11) toAnd said first capacitance (C)_oddi) And a voltage terminal (VCOM), which is closed or opened according to a first switching signal (PH 1);

the second capacitance (C)_eveni) And an input of the integration path first differential circuit (11), and the second capacitance (C)_eveni) And a voltage terminal (VCOM), which is closed or opened according to a second switching signal (PH 2);

the first capacitor (C)_oddi) And the voltage terminal (VCOM), and the first capacitance (C)_oddi) And said first integrating capacitor (C)_INT1) A switch between the first terminals, which is turned on or off according to a first reset signal (RES 1);

the second capacitance (C)_eveni) And the voltage terminal (VCOM), and the second capacitor (C)_eveni) And said first integrating capacitor (C)_INT1) Is closed or opened in response to a second reset signal (RES 2).

6. High-integration active dynamic loop filter according to claim 4, characterized in that the third capacitance (C)_oddp) And an input of the proportional path first differential circuit (21), is closed or opened in dependence on a first switching signal (PH 1);

the fourth capacitance (C)_evenp) And an input of the proportional path first differential circuit (21), is closed or opened in dependence on a second switching signal (PH 2);

the third capacitance (C)_oddp) And a voltage terminal (VCOM), which is closed or opened according to a first reset signal (RES 1);

the fourth capacitor (C)_evenp) And the voltage terminal (VCOM), is closed or opened according to a second reset signal (RES 2).

7. The high-integration active dynamic loop filter of claim 5 or 6, wherein the first switching signal (PH1) and the second switching signal (PH2) are a pair of two-phase non-overlapping clock signals, and the first reset signal (RES1) and the second reset signal (RES2) are a pair of two-phase non-overlapping clock signals;

the operating frequency of the two pairs of clock signals is 1/2 times the frequency of the PFD input reference clock.

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