CN114743942A - 混合式接合结构及其制作方法 - Google Patents

混合式接合结构及其制作方法 Download PDF

Info

Publication number
CN114743942A
CN114743942A CN202110017678.0A CN202110017678A CN114743942A CN 114743942 A CN114743942 A CN 114743942A CN 202110017678 A CN202110017678 A CN 202110017678A CN 114743942 A CN114743942 A CN 114743942A
Authority
CN
China
Prior art keywords
layer
conductive
dielectric layer
air gap
conductive structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110017678.0A
Other languages
English (en)
Inventor
杨柏宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN202110017678.0A priority Critical patent/CN114743942A/zh
Priority to US17/160,332 priority patent/US11562974B2/en
Publication of CN114743942A publication Critical patent/CN114743942A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • H01L2224/03616Chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/038Post-treatment of the bonding area
    • H01L2224/0383Reworking, e.g. shaping
    • H01L2224/03831Reworking, e.g. shaping involving a chemical process, e.g. etching the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0501Shape
    • H01L2224/05011Shape comprising apertures or cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05026Disposition the internal layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05547Structure comprising a core and a coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805Shape
    • H01L2224/08057Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805Shape
    • H01L2224/0807Shape of bonding interfaces, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/111Manufacture and pre-treatment of the bump connector preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • H01L2224/13014Shape in top view being circular or elliptic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034Bonding interfaces of the bonding area
    • H01L2224/80357Bonding interfaces of the bonding area being flush with the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8036Bonding interfaces of the semiconductor or solid state body
    • H01L2224/80365Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8036Bonding interfaces of the semiconductor or solid state body
    • H01L2224/80379Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开一种混合式接合结构及其制作方法,其中该混合式接合结构包含一第一导电结构和一第二导电结构,第一导电结构包含一第一导电层,一第一缓冲层环绕并接触第一导电层,一第一空气间隙环绕并接触第一缓冲层以及一第一介电层环绕并接触第一空气间隙,第二导电结构包含一第二导电层,一第二缓冲层接触第二导电层,一第二介电层环绕第二缓冲层,其中第二导电层和第一导电层接合,第一介电层和第二介电层接合。

Description

混合式接合结构及其制作方法
技术领域
本发明涉及一种混合式接合结构及其制作方法,特别是涉及一种避免晶片对准偏差时,金属原子扩散至层间介电层的混合式接合结构及其制作方法。
背景技术
近年来各种电子元件的集成度的持续提高,在一方面集成密度的提高来自于最小特征尺寸(minimum feature size)的持续减小,使得更多较小的元件能够整合到给定区域中。除此之外,利用堆叠接合多层晶片形成三维集成电路也是另一种增加元件集成度的方法,接合晶片可以通过两种介电材料之间的黏合来完成两个晶片的接合,或者通过两种金属材料之间的黏合来实现,或者通过结合前述两种黏合机制的方法进行。
然而,对于三维集成电路技术来说仍存在很多待处理的挑战,例如在黏合两片晶片时,晶片的对准误差(misalignment)会使得金属材料接触到层间介电层并且金属原子会扩散入层间介电层造成污染。
发明内容
有鉴于此,本发明提供一种混合式接合结构及其制作方法,以解决晶片对准偏差时,金属原子扩散至层间介电层的问题。
根据本发明的优选实施例,一种混合式接合结构包含一第一导电结构和一第二导电结构,第一导电结构包含一第一导电层,一第一缓冲层环绕并接触第一导电层,一第一空气间隙环绕并接触第一缓冲层以及一第一介电层环绕并接触第一空气间隙,第二导电结构包含一第二导电层,一第二缓冲层接触第二导电层,一第二介电层环绕第二缓冲层,其中第二导电层和第一导电层接合,第一介电层和第二介电层接合。
根据本发明的另一优选实施例,一种混合式接合结构的制作方法包含进行一空气间隙制作工艺,包含提供一第一介电层,然后形成一蚀刻停止层覆盖第一介电层,形成一第二介电层覆盖蚀刻停止层,形成一沟槽位于第二介电层以及蚀刻停止层中,接着依序形成一第一缓冲层和一第一导电层填入沟槽,然后形成一图案化掩模覆盖第二介电层,其中第一缓冲层、第一导电层以及位于第一缓冲层周围的第二介电层由图案化掩模曝露出来,接续进行一蚀刻制作工艺,移除由图案化掩模曝露出来的第二介电层以形成一空气间隙围绕第一缓冲层,最后移除图案化掩模以完成一第N导电结构,其中N为由1至2的正整数。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举优选实施方式,并配合所附的附图,作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用,并非用来对本发明加以限制者。
附图说明
图1至图5A为本发明的第一优选实施例所绘示的一种空气间隙制作工艺的示意图;
图5B为本发明的第一优选实施例的一种空气间隙制作工艺的变化型的示意图;
图5C为本发明的第一优选实施例的一种空气间隙制作工艺的另一变化型的示意图;
图6为图5A、图5B和图5C的上视图;
图7至图10为本发明的第二优选实施例所绘示的一种空气间隙制作工艺的示意图;
图11A、图11B、图11C、图11D、图11E、图11F和图11G为本发明数个优选实施例所绘示的一种混合式接合结构的示意图。
主要元件符号说明
10:第一介电层
12:金属层
14:蚀刻停止层
16:第二介电层
18:沟槽
20:第一缓冲层
22:第一导电层
24:图案化掩模
26:空气间隙
28a:第一导电结构
28b:第二导电结构
28c:第三导电结构
30:牺牲层
32:间隙壁
34:凹槽
100:混合式接合结构
110:第四介电层
112:金属层
114:蚀刻停止层
116:第三介电层
120:第二缓冲层
122:第二导电层
200:混合式接合结构
300:混合式接合结构
400:混合式接合结构
500:混合式接合结构
600:混合式接合结构
700:混合式接合结构
W:宽度
具体实施方式
图1至图5A为根据本发明的第一优选实施例所绘示的一种空气间隙制作工艺。图5B为本发明的第一优选实施例的一种空气间隙制作工艺的变化型。图5C为本发明的第一优选实施例的一种空气间隙制作工艺的另一变化型。如图1所示,提供一第一介电层10,第一介电层10可以设置在一基底(图未示)上,在基底上可以包含数个层间介电层,并且在层间介电层中已形成了金属内连线。基底可以为硅基底、锗基底、砷化镓基底、硅锗基底、磷化铟基底、氮化镓基底、碳化硅基底或是硅覆绝缘基底。此外,基底可以为一尚未切割的晶片、一电路板、一中介板(interposer)或是一切割完成待封装的管芯(die)。此外在第一介电层10中设置有一金属层12,例如一金属插塞。然后形成一蚀刻停止层14覆盖第一介电层10,蚀刻停止层14包含SiC或SiCN,蚀刻停止层14的厚度较佳介于1nm至500nm之间。之后形成一第二介电层16覆盖蚀刻停止层14,接续蚀刻第二介电层16和蚀刻停止层14以形成一沟槽18位于第二介电层16以及蚀刻停止层14中,此时金属层12由沟槽18曝露出来。
如图2所示,依序形成一第一缓冲层20和一第一导电层22填入沟槽18,第一缓冲层20顺应地覆盖第二介电层16和沟槽18,第一导电层22覆盖第一缓冲层20,第一缓冲层20包含TiN、TaN或Ti/TiN,但不限于此,其它能阻挡金属扩散的导电层也可使用,在本实施例中第一缓冲层20的厚度较佳介于1nm至100nm之间,第一缓冲层20较佳利用沉积方式形成。第一导电层22包含Cu、Al、W、Ti、TiN、Ta、Cu/Al、TaN或是上述材料的组合,在本实施例中第一导电层22的厚度较佳介于1nm至5000nm之间,在本实施例中,第一导电层22较佳为Cu并且以电镀方式形成。
如图3所示,进行一化学机械研磨制作工艺,移除在沟槽18之外的第一导电层22和第一缓冲层20。如图4所示,形成一图案化掩模24覆盖第二介电层16以定义出后续空气间隙的位置,其中第一缓冲层20、第一导电层22以及位于第一缓冲层20周围的第二介电层16由图案化掩模24曝露出来,图案化掩模24较佳为光致抗蚀剂。
请参阅图5A、图5B、图5C和图6,其中图6为图5A、图5B和图5C的上视图。首先以图案化掩模24为掩模进行一蚀刻制作工艺,移除由图案化掩模24曝露出来的第二介电层16以形成一空气间隙26围绕第一缓冲层20,在空气间隙26完成之后,移除图案化掩模24。前述蚀刻制作工艺包含一干蚀刻、一部分干蚀刻(partial dry etching)或一湿蚀刻,视产品需求可以任意选择。图5A所绘示的是利用干蚀刻方式进行蚀刻制作工艺,详细来说是利用干蚀刻制作工艺移除第二介电层16直至蚀刻停止层14曝露出来。图5B所绘示的是利用部分干蚀刻方式进行蚀刻制作工艺,如图5B所示,第二介电层16只被移除了部分的厚度并且蚀刻停止层14并未曝露出来。图5C所绘示的是利用湿蚀刻方式进行蚀刻制作工艺,如图5C所示,湿蚀刻移除第二介电层16后,会在第二介电层16表面形成弧形轮廓,图5C的湿蚀刻在尚未蚀刻到蚀刻停止层14前即停止,然而视不同需求,也可以湿蚀刻至曝露出蚀刻停止层14后再停止。在干蚀刻、部分干蚀刻或湿蚀刻中的蚀刻剂都只会移除第二介电层16。在完成空气间隙26并且移除图案化掩模24后,至此本发明的空气间隙制作工艺结束并且一第一导电结构28a业已完成。之后可提供另一基底,重复第一优选实施例中的空气间隙制作工艺,以形成一第二导电结构,第二导电结构可以采用干蚀刻、部分干蚀刻或一湿蚀刻制作,所以第二导电结构可以是图5A、图5B或图5C中的一种。同样地,第二导电结构可以在一尚未切割的晶片、一电路板、一中介板(interposer)或是一切割完成待封装的管芯(die)上。
图7至图10为根据本发明的第二优选实施例所绘示的一种空气间隙制作工艺,其中具有相同功能和位置的元件,将使用第一优选实施例中的元件标号,其相关说明请参阅第一优选实施例,在此不再赘述。
如图7所示,提供一第一介电层10,第一介电层10中设置有一金属层12。然后形成一蚀刻停止层14覆盖第一介电层10,之后形成一牺牲层30覆盖部分蚀刻停止层14,牺牲层30和金属层12至少部分重叠,牺牲层30较佳为含硅材料,例如多晶硅。
如图8所示,形成一间隙壁32环绕牺牲层30,接续形成一第二介电层16覆盖蚀刻停止层14,其中第二介电层16的上表面与牺牲层30的上表面切齐,间隙壁32的位置在后续将会变成空气间隙,因此可以通过间隙壁32的厚度控制空气间隙的大小。如图9所示,移除牺牲层30以及牺牲层30正下方的蚀刻停止层14以形成一沟槽18,之后依序形成一第一缓冲层20和一第一导电层22填入沟槽18并且移除在沟槽18之外的第一缓冲层20和第一导电层22。如图10以及图6所示,移除间隙壁32以形成一空气间隙26围绕第一缓冲层20。至此本发明的空气间隙制作工艺结束并且一第一导电结构28a业已完成。之后可提供另一基底重复第二优选实施例中的空气间隙制作工艺,以形成一第二导电结构。
图11A为根据本发明的优选实施所绘示的一种混合式接合结构的制作方法,其中具有相同功能和位置的元件,将使用第一优选实施例中的元件标号,其相关说明请参阅第一优选实施例,在此不再赘述。
如图11A所示,在利用第一优选实施例的空气间隙制作工艺制作出一第一导电结构28a和一第二导电结构28b之后,将第一导电结构28a中的第一导电层22和第二导电结构28b中的第一导电层22对准接合,将第一导电结构22中的第二介电层16和第二导电结构28b中的第二介电层16对准接合,举例而言,若是第一导电结构28a在一尚未切割的晶片上,第二导电结构28b在另一尚未切割的晶片上,此时的对准接合就是晶片对晶片(wafter towafer)的接合,但不限于此,第一导电结构28a和第二导电结构28b的接合,也可以是管芯对管芯、晶片对中介层等的接合。至此本发明的混合式接合结构100业已完成,在本实施例中的第一导电结构28a和第二导电结构28b中的空气间隙26系利用干蚀刻形成。
本发明的混合式接合结构中可以利用第一优选实施例的制作方式或是第二优选实施例的制作方式,制作出二个导电结构进行接合,或者也可以和没有空气间隙但具有导电层的另一导电结构进行接合。只要在混合式接合结构中两个接合的导电结构其中之一具有空气间隙即可。因此除了图11A中所示例的混合式接合结构100的制作方法,其它还有各种混合式接合结构,下文在图11B、图11C、图11D、图11E、图11F、图11G中将揭露数个变化型,但除了以下的变化型之外,只要是符合在两个接合的导电结构其中之一具有空气间隙环绕缓冲层的结构,都属于本发明的发明范畴,同样地,图11B、图11C、图11D、图11E、图11F、图11G中的对准接合可以是晶片对晶片、管芯对管芯、晶片对中介层等的接合。。
如图11B所示,利用第一优选实施例的空气间隙制作工艺以部分干蚀刻制作出第一导电结构28a和第二导电结构28b之后,将第一导电结构28a中的第一导电层22和第二导电结构28b中的第一导电层22对准接合,将第一导电结构28a中的第二介电层16和第二导电结构28b中的第二介电层16对准接合以完成混合式接合结构200。
如图11C所示,利用第一优选实施例的空气间隙制作工艺以湿蚀刻制作出第一导电结构28a和第二导电结构28b之后,将第一导电结构22a中的第一导电层22和第二导电结构28b中的第一导电层22对准接合,将第一导电结构28a中的第二介电层16和第二导电结构28b中的第二介电层16对准接合以完成混合式接合结构300。
如图11D所示,利用第一优选实施例的空气间隙制作工艺制作出一第一导电结构28a,并且另外提供一第三导电结构28c,第三导电结构28c包含一第二导电层122,一第二缓冲层120接触第二导电层122,第三介电层116接触第二缓冲层120,换而言之,第三导电结构28c中没有空气间隙,此外在第三介电层116下方设置有一第四介电层110,第四介电层中设置有一金属层112和第二导电层122重叠,第四介电层110和第三介电层116之间设置有一蚀刻停止层114。之后将第一导电结构28a中第一导电层22和第三导电结构28c的第二导电层122接合以及将第一导电结构22a中第二介电层16与第三导电结构28c中的第三介电层116接合以完成混合式接合结构400。虽然在本变化型中是以干蚀刻的第一导电结构28a作为示例,但采用部分干蚀刻(图5B)或湿蚀刻(图5C)所制作出的第一导电结构28a,也适用于本变化型。
如图11E所示,利用第二优选实施例的空气间隙制作工艺制作出第一导电结构28a和第二导电结构28b之后,将第一导电结构28a中的第一导电层22和第二导电结构22b中的第一导电层22对准接合,将第一导电结构28a中的第二介电层16和第二导电结构28b中的第二介电层16对准接合以完成混合式接合结构500。
如图11F所示,利用第二优选实施例的空气间隙制作工艺制作出第一导电结构28a之后,另外提供如前文所述没有空气间隙的第三导电结构28c,然后将第一导电结构28a中的第一导电层22和第三导电结构28c中的第二导电层122对准接合,将第一导电结构22a中的第二介电层16和第三导电结构28c中的第三介电层116对准接合以完成混合式接合结构600。
如图11G所示,利用第一优选实施例的空气间隙制作工艺以干蚀刻制作出第一导电结构28a以及以湿蚀刻制作工艺制作出第二导电结构28b之后,将第一导电结构28a中的第一导电层22和第二导电结构28b中的第一导电层22接合,将第一导电结构28a中的第二介电层16和第二导电结构28b中的第二介电层16接合以完成混合式接合结构700,值得注意的是:在接合的过程中发生对准误差,所以第一导电结构28a中的第一导电层22会有部分没有贴合在第二导电结构28b中的第一导电层22上,而是接触空气间隙26,然而第一导电层22的金属原子无法通过空气间隙26扩散,因此就可以避免金属原子扩散而造成污染的问题。
图11A、图11B、图11C、图11D、图11E、图11F和图11G为根据本发明数个优选实施例所绘示的一种混合式接合结构,其中具有相同功能和位置的元件,将使用第一优选实施例中的元件标号,其相关说明请参阅第一优选实施例,在此不再赘述。
如图11A所示,一种混合式接合结构100包含一第一导电结构28a和一第二导电结构28b,第一导电结构28a和第二导电结构28b的上视图结构位置相同,都是以图6作为示例,请同时参阅图6和图11A,第一导电结构28a和第二导电结构28b相同,都是包含一第一导电层22,一第一缓冲层20环绕并接触第一导电层22,一空气间隙26环绕并接触第一缓冲层20以及一第二介电层16环绕并接触空气间隙26,第二介电层16的上表面和第一导电层22的上表面切齐,第一导电结构28a中的第一导电层22接触并贴合第二导电结构28b中的第一导电层22,第一导电结构28a中的第二介电层16接触并贴合第二导电结构28b中的第二介电层16。空气间隙26的深度等于第二介电层16的深度,一蚀刻停止层14由空气间隙26曝露出来。此外空气间隙26的宽度W介于0.01μm至10μm之间。再者,空气间隙26在第二介电层16中形成一凹槽34,凹槽34底部为水平表面,凹槽34的侧壁为垂直侧壁,并且凹槽34的底部宽度和凹槽的开口宽度相同。
第一导电结构28a和第二导电结构28b中的第二介电层16之下还设置了第一介电层10,第一介电层10中设置有一金属层12,例如一金属插塞,蚀刻停止层14在第一介电层10和第二介电层16之间。蚀刻停止层14包含SiC或SiCN,蚀刻停止层14的厚度较佳介于1nm至500nm之间。
第一介电层10和第二介电层16的材料各自包含氧化硅、氮氧化硅、磷硅酸盐玻璃(phosphosilicate glass)、硼磷硅酸盐玻璃(borophosphosilicate)、氟硅玻璃(fluorinated silicate glass)、有机硅酸盐玻璃(organosilicate glasses)、碳氧化硅(SiOC)、旋涂式玻璃(Spin-on glass)、旋涂式聚合物(spin-on-polymer)、碳化硅或是上述材料组合。第二介电层16的厚度较佳介于1nm至5000nm之间。第一缓冲层20包含TiN、TaN或Ti/TiN。第一缓冲层20的厚度较佳介于1nm至100nm之间。第一导电层22包含Cu、Al、W、Ti、TiN、Ta、Cu/Al、TaN或是上述材料的组合,在本实施例中第一导电层22的厚度较佳介于1nm至5000nm之间。此外,空气间隙26中可以包含空气、氧气、氮气或是惰性气体。
如图11B所示,混合式接合结构200是利用第一导电结构28a和第二导电结构28b接合,第一导电结构28a和第二导电28b结构相同,和图11A的混合式接合结构100的差异之处在于混合式接合结构200中的空气间隙26的深度小于第二介电层16的深度,其余部分都和混合式接合结构100相同,在此不再赘述。
如图11C所示,混合式接合结构300是利用第一导电结构28a和第二导电结构28b接合,第一导电结构28a和第二导电结构28b相同,混合式接合结构300和图11A的混合式接合结构100的差异之处在于混合式接合结构300的空气间隙26在第二介电层16中形成一凹槽34,凹槽34底部为弧形。其余部分都和混合式接合结构100相同,在此不再赘述。
如图11D所示,混合式接合结构400利用第一导电结构28a和第三导电结构28c接合而成,和图11A的混合式接合结构100的差异之处在于混合式接合结构400的第三导电结构28c中没有空气间隙,详细来说,第三导电结构28c包含一第二导电层122,一第二缓冲层120接触第二导电层122,第三介电层116接触第二缓冲层120,在混合式接合结构400中,第二导电层122和第一导电层22接合,第二介电层16和第三介电层116接合。第二导电层122包含Cu、Al、W、Ti、TiN、Ta、Cu/Al、TaN或是上述材料的组合,第二导电层122的厚度较佳介于1nm至5000nm之间,第二缓冲层120包含TiN、TaN或Ti/TiN。第二缓冲层120的厚度较佳介于1nm至100nm之间,第三介电层116和第二介电层16可选自相同的材料类别。其余部分都和混合式接合结构100相同,在此不再赘述。
如图11E所示,混合式接合结构500是利用第一导电结构28a和第二导电结构28b接合,第一导电结构28a和第二导电结构28b的构造相同,混合式接合结构500和图11A的混合式接合结构100的差异之处在于混合式接合结构500的空气间隙26在第二介电层16中形成一凹槽34,凹槽34侧壁为弧形,并且凹槽34的底部宽度比凹槽34的开口宽度大。其余部分都和混合式接合结构100相同,在此不再赘述。
如图11F所示,混合式接合结构600利用第一导电结构28a和第三导电结构28c接合而成,和图11E的混合式接合结构500的差异之处在于混合式接合结构600的第三导电结构28c中没有空气间隙,第三导电结构28c的结构和图11D的相同,请参阅前文。在混合式接合结构600中,第三导电结构28c的第二导电层122和第一导电结构28a的第一导电层22接合,第一导电结构28a的第二介电层16和第三导电结构28c的第三介电层116接合。其余部分都和混合式接合结构500相同,在此不再赘述。
如图11G所示,混合式接合结构700利用第一导电结构28a和第二导电结构28b接合而成,和混合式接合结构100的差异之处在于混合式接合结构700的第一导电结构28a和第二导电结构28b两者的空气间隙26形状不同并且第一导电结构28a和第二导电结构28b之间有对准误差,因此第一导电结构28a的第一导电层22会和第二导电结构28b的空气间隙26重叠并接触。
本发明利用在缓冲层远离导电层的周围设置了空气间隙,如此可以避免进行混合式接合时,因为对准误差,造成导电层接触层间介电层后的扩散污染。此外,由于空气间隙的介电常数约为1,因此以空气间隙取代部分的介电层可以降低元件之间的寄生电容。再者和将空气间隙设置在导电层和缓冲层之间的结构相比,本发明将空气间隙设置在缓冲层远离导电层的侧边,如此不会占用导电层的位置,可以使混合式接合结构维持较低的电阻。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。

Claims (20)

1.一种混合式接合结构,其特征在于,包含:
第一导电结构,其中该第一导电结构包含:
第一导电层;
第一缓冲层,环绕并接触该第一导电层;
第一空气间隙,环绕并接触该第一缓冲层;以及
第一介电层,环绕并接触该第一空气间隙;
第二导电结构,其中该第二导电结构包含:
第二导电层;
第二缓冲层,接触该第二导电层;
第二介电层,环绕该第二缓冲层;其中该第二导电层和该第一导电层接触并接合,该第一介电层和该第二介电层接触并接合。
2.如权利要求1所述的混合式接合结构,另包含第二空气间隙环绕并接触该第二缓冲层。
3.如权利要求1所述的混合式接合结构,其中该第一空气间隙的深度小于该第一介电层的深度。
4.如权利要求1所述的混合式接合结构,其中该第一空气间隙的深度等于该第一介电层的深度。
5.如权利要求1所述的混合式接合结构,其中该第一空气间隙在该第一介电层中形成凹槽。
6.如权利要求5所述的混合式接合结构,其中该凹槽底部为弧形。
7.如权利要求5所述的混合式接合结构,其中该凹槽底部为水平表面。
8.如权利要求1所述的混合式接合结构,其中该第一导电层包含Cu、Al、W、Ti、TiN、Ta、Cu/Al或TaN,该第二导电层包含Cu、Al、W、Ti、TiN、Ta、Cu/Al或TaN。
9.如权利要求1所述的混合式接合结构,其中该第一空气间隙的宽度介于0.01μm至10μm之间,该第二空气间隙的宽度介于0.01μm至10μm之间。
10.如权利要求1所述的混合式接合结构,其中该第一介电层的上表面和该第一导电层的上表面切齐。
11.一种混合式接合结构的制作方法,包含:
进行空气间隙制作工艺,包含:
提供第一介电层;
形成蚀刻停止层覆盖该第一介电层;
形成第二介电层覆盖该蚀刻停止层;
形成沟槽位于该第二介电层以及该蚀刻停止层中;
依序形成第一缓冲层和第一导电层填入该沟槽;
形成图案化掩模覆盖该第二介电层,其中该第一缓冲层、该第一导电层以及位于该第一缓冲层周围的该第二介电层由该图案化掩模曝露出来;
进行蚀刻制作工艺,移除由该图案化掩模曝露出来的该第二介电层以形成空气间隙围绕该第一缓冲层;
移除该图案化掩模以完成第N导电结构,其中N为由1至2的正整数。
12.如权利要求11所述的混合式接合结构的制作方法,另包含:
重复进行该空气间隙制作工艺以完成第一导电结构和第二导电结构;以及
将第一导电结构中的该第一导电层和该第二导电结构中的该第一导电层接合,将该第一导电结构中的该第二介电层和该第二导电结构中的该第二介电层接合。
13.如权利要求11所述的混合式接合结构的制作方法,另包含:
提供第三导电结构,包含:
第二导电层;
第二缓冲层环绕并接触该第二导电层;以及
第三介电层环绕并接触该第二缓冲层;
将该第一导电结构中的该第一导电层和该第三导电结构的该第二导电层接合以及将该第一导电结构中该第二介电层与该第三导电结构中的第三介电层接合。
14.如权利要求11所述的混合式接合结构的制作方法,其中该蚀刻制作工艺包含干蚀刻、部分干蚀刻(partial dry etching)或湿蚀刻。
15.如权利要求11所述的混合式接合结构的制作方法,其中该第一导电层包含Cu、Al、W、Ti、TiN、Ta、Cu/Al或TaN。
16.如权利要求11所述的混合式接合结构的制作方法,其中该空气间隙的宽度介于0.01μm至10μm之间。
17.一种混合式接合结构的制作方法,包含:
进行空气间隙制作工艺以完成第N导电结构,其中N为由1至2的正整数,其中该空气间隙制作工艺,包含:
提供第一介电层;
形成蚀刻停止层覆盖该第一介电层;
形成牺牲层覆盖部分该蚀刻停止层
形成间隙壁环绕该牺牲层;
形成第二介电层覆盖该蚀刻停止层,其中该第二介电层的上表面与该牺牲层的上表面切齐;
移除该牺牲层以及该牺牲层正下方的该蚀刻停止层以形成沟槽;
依序形成第一缓冲层和第一导电层填入该沟槽;以及
移除该间隙壁以形成空气间隙围绕该缓冲层。
18.如权利要求17所述的混合式接合结构的制作方法,另包含:
重复进行该空气间隙制作工艺以完成第一导电结构和第二导电结构;以及
将第一导电结构中的该第一导电层和该第二导电结构中的该第一导电层接合,将该第一导电结构中的该第二介电层和该第二导电结构中的该第二介电层接合。
19.如权利要求17所述的混合式接合结构的制作方法,另包含:
提供第三导电结构,包含:
第二导电层;
第二缓冲层环绕并接触该第二导电层;以及
第三介电层环绕并接触该第二缓冲层;
将该第一导电结构中的该第一导电层和该第三导电结构的该第二导电层接合以及将该第一导电结构中该第二介电层与该第三导电结构中的第三介电层接合。
20.如权利要求17所述的混合式接合结构的制作方法,其中该空气间隙的宽度介于0.01μm至10μm之间。
CN202110017678.0A 2021-01-07 2021-01-07 混合式接合结构及其制作方法 Pending CN114743942A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202110017678.0A CN114743942A (zh) 2021-01-07 2021-01-07 混合式接合结构及其制作方法
US17/160,332 US11562974B2 (en) 2021-01-07 2021-01-27 Hybrid bonding structure and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110017678.0A CN114743942A (zh) 2021-01-07 2021-01-07 混合式接合结构及其制作方法

Publications (1)

Publication Number Publication Date
CN114743942A true CN114743942A (zh) 2022-07-12

Family

ID=82218986

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110017678.0A Pending CN114743942A (zh) 2021-01-07 2021-01-07 混合式接合结构及其制作方法

Country Status (2)

Country Link
US (1) US11562974B2 (zh)
CN (1) CN114743942A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11817420B2 (en) * 2021-07-19 2023-11-14 Micron Technology, Inc. Systems and methods for direct bonding in semiconductor die manufacturing

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094183B (zh) * 2011-10-29 2015-07-29 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
US9142517B2 (en) * 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US9443796B2 (en) * 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US9390965B2 (en) * 2013-12-20 2016-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Air-gap forming techniques for interconnect structures
US10157823B2 (en) * 2014-10-31 2018-12-18 Qualcomm Incorporated High density fan out package structure
US9691733B1 (en) * 2016-07-28 2017-06-27 United Microelectronics Corp. Bonded semiconductor structure and method for forming the same
US11031285B2 (en) * 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
CN112585740A (zh) * 2018-06-13 2021-03-30 伊文萨思粘合技术公司 作为焊盘的tsv
US11158573B2 (en) * 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11393780B2 (en) * 2019-07-26 2022-07-19 Sandisk Technologies Llc Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
US20210320075A1 (en) * 2019-07-26 2021-10-14 Sandisk Technologies Llc Bonded assembly containing bonding pads spaced apart by polymer material, and methods of forming the same
US11107775B1 (en) * 2020-03-31 2021-08-31 Nanya Technology Corporation Semiconductor device with electrically floating contacts between signal-transmitting contacts
US11302662B2 (en) * 2020-05-01 2022-04-12 Nanya Technology Corporation Semiconductor package with air gap and manufacturing method thereof
US11551969B2 (en) * 2020-09-23 2023-01-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure with backside interconnection structure having air gap

Also Published As

Publication number Publication date
US20220216167A1 (en) 2022-07-07
US11562974B2 (en) 2023-01-24

Similar Documents

Publication Publication Date Title
US11705386B2 (en) Semiconductor device including TSV and method of manufacturing the same
KR102308486B1 (ko) 접합된 웨이퍼를 위한 보호 구조체
KR101476544B1 (ko) 개선된 비아 랜딩 프로파일을 위한 신규한 패터닝 방법
JP5562087B2 (ja) ビア構造とそれを形成するビアエッチングプロセス
US7544602B2 (en) Method and structure for ultra narrow crack stop for multilevel semiconductor device
TWI398913B (zh) 具有密封環結構之半導體裝置及其製造方法
JP4347637B2 (ja) トレンチ側壁のバッファー層を使用して半導体装置用金属配線を形成する方法及びそれにより製造された装置
CN106033741B (zh) 金属内连线结构及其制作方法
CN108511386B (zh) 分段式防护环及芯片边缘密封件
US11107726B2 (en) Method for manufacturing bonding pad in semiconductor device
CN114743942A (zh) 混合式接合结构及其制作方法
US20210125925A1 (en) Semiconductor device and method of fabricating the same
US11715710B2 (en) Method of treatment of an electronic circuit for a hybrid molecular bonding
US10790227B2 (en) Semiconductor device with interconnect structure and fabrication method thereof
KR102607594B1 (ko) Tsv를 포함하는 반도체 장치
CN111223774B (zh) 用于晶片平坦化的方法和通过其制造的图像传感器
CN110931373B (zh) 一种半导体器件及其制造方法
TW202215555A (zh) 形成半導體裝置的方法
CN110660745B (zh) 半导体结构及其形成方法
CN218069837U (zh) 半导体结构
KR102555240B1 (ko) Tsv를 포함하는 반도체 장치 및 그 제조 방법
KR20230159268A (ko) 굴곡진 계면을 갖는 금속 구조들을 포함하는 집적회로 소자 및 그 형성 방법
TW202415276A (zh) 矽電容結構及其製作方法
CN117238885A (zh) 半导体器件及其制造方法
KR20230020659A (ko) 반도체 소자

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination