CN114725173A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN114725173A CN114725173A CN202210343669.5A CN202210343669A CN114725173A CN 114725173 A CN114725173 A CN 114725173A CN 202210343669 A CN202210343669 A CN 202210343669A CN 114725173 A CN114725173 A CN 114725173A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
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Abstract
The present invention provides a display panel including a first display region and a second display region, the display panel including: the pixel structure comprises a substrate base plate, a plurality of first pixel units and a plurality of second pixel units, wherein the plurality of first pixel units and the plurality of second pixel units are positioned on the substrate base plate, the first pixel units comprise first light-emitting devices and first pixel circuits, and the second pixel units comprise second light-emitting devices and second pixel circuits; the first light emitting device is located in the first display area, the first pixel circuit, the second light emitting device and the second pixel circuit are located in the second display area, and the first light emitting device and the first pixel circuit are connected through a connecting wire; the first and second light emitting devices are independently reset. The embodiment of the invention can control the display difference of the first display area and the second display area by controlling the first light emitting device and the second light emitting device to be independently reset.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
An under-screen camera area of a high PPI (pixel density) OLED (Organic Light-Emitting Diode, abbreviated as OLED) full-screen display panel usually only retains an EL (electroluminescent) device portion, and a driving circuit portion thereof is disposed at a compressed pixel position of a Normal (Normal) display area, and the EL device portion and a corresponding driving circuit portion thereof are connected through a transparent material (e.g., ITO, Indium tin oxide) for driving. Meanwhile, in order to improve the transmittance of the under-screen camera area, the light emitting area of the EL device is made small. The display effect of the camera area under the screen and the display effect of the normal display area can be different due to the fact that the external drive and the light-emitting area are different.
Disclosure of Invention
The invention provides a display panel and a display device, which can reduce the display difference between a photosensitive area and a normal display area under a screen.
A first aspect of the present invention provides a display panel comprising a first display region and a second display region, the second display region at least partially surrounding the first display region;
the display panel includes: the pixel structure comprises a substrate base plate, a plurality of first pixel units and a plurality of second pixel units, wherein the plurality of first pixel units and the plurality of second pixel units are positioned on the substrate base plate, the first pixel units comprise first light-emitting devices and first pixel circuits, and the second pixel units comprise second light-emitting devices and second pixel circuits;
the first light emitting device is located in the first display area, the first pixel circuit, the second light emitting device and the second pixel circuit are located in the second display area, an orthographic projection of the second light emitting device on the substrate base plate and an orthographic projection of the second pixel circuit on the substrate base plate are at least partially overlapped, and the first light emitting device and the first pixel circuit are connected through a connecting wire;
the first and second light emitting devices are independently reset.
Wherein the display panel further comprises: a third initialization signal line and a second initialization signal line positioned in the second display area;
the first light emitting device and the second light emitting device reset independently, specifically:
the first pixel circuit is coupled to the third initialization signal line, and the second pixel circuit is coupled to the second initialization signal line; the third initialization signal line is configured to provide a third initialization signal to the first pixel circuit, and the second initialization signal line is configured to provide a second initialization signal to the second pixel circuit.
The absolute value of the voltage value corresponding to the third initialization signal is smaller than the absolute value of the voltage value corresponding to the second initialization signal.
Wherein the first pixel circuit and the second pixel circuit respectively comprise a seventh transistor, the third initialization signal line is coupled with a first pole of the seventh transistor in the first pixel circuit, and the seventh transistor is coupled with the first light emitting device;
the second initialization signal line is coupled to a first electrode of a seventh transistor in the second pixel circuit, the seventh transistor being coupled to a second light emitting device.
The display panel comprises a first gate metal layer, a second gate metal layer and a first source drain metal layer which are sequentially stacked along the direction far away from the substrate base plate, the third initialization signal line is made of the first source drain metal layer, and the second initialization signal line is made of the second gate metal layer.
The third initialization signal line is positioned in the second display area;
the display panel further includes: the light-emitting control signal wire is made of a first grid metal layer, and the second reset signal wire is made of a first grid metal layer;
the orthographic projection of the third initialization signal line on the substrate base plate is positioned between the orthographic projection of the light-emitting control signal line on the substrate base plate and the orthographic projection of the second reset signal line on the substrate base plate.
The plurality of second pixel units comprise a plurality of second pixel circuits, the plurality of second pixel circuits are divided into a plurality of groups of second pixel circuits, each group of second pixel circuits comprises N rows of second pixel circuits, the N rows of second pixel circuits are distributed along a first direction, wherein N is more than or equal to2, and N is a positive integer;
the plurality of first pixel units comprise a plurality of first pixel circuits, the plurality of first pixel circuits are divided into a plurality of columns of first pixel circuits, and the plurality of columns of first pixel circuits are arranged along a first direction.
And a column of first pixel circuits is arranged between two adjacent groups of second pixel circuits.
Wherein the display panel further comprises: a first data line positioned in the second display region and configured to supply a first data voltage to the first pixel circuit;
the first data line comprises two first switching parts and a second switching part, the two first switching parts extend along a first direction, the second switching part extends along a second direction, the two first switching parts are connected with two ends of the second switching part respectively, at least part of the first display area is located between the two first switching parts, and the first direction and the second direction are crossed.
The two first switching parts and the third initialization signal line are made of the same material in the same layer;
the orthographic projection of the first transfer part on the substrate base plate is positioned between the orthographic projection of the light-emitting control signal line on the substrate base plate and the orthographic projection of the second reset signal line on the substrate base plate.
And the second switching part is made of a second source drain metal layer.
Wherein the second display area further comprises: a plurality of dummy pixel circuits on the substrate base; the plurality of virtual pixel circuits are divided into a plurality of columns of virtual pixel circuits, and at least part of the virtual pixel circuits in at least one column of virtual pixel circuits are multiplexed into a first pixel circuit;
the display panel further includes: a second data line configured to provide a second data voltage to the column of dummy pixel circuits, at least a portion of the second data line being multiplexed as the second switching section.
Wherein the display panel further comprises:
a first initialization signal line, a power signal line, a first reset signal line, a first scan line and a second scan line;
the first pixel driving circuit further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a storage capacitor; wherein the content of the first and second substances,
a gate of the first transistor is coupled to the first reset signal line, and a first pole of the first transistor is coupled to the first initialization signal line; a second pole of the first transistor is coupled to a gate of the third transistor;
a first pole of the second transistor is coupled to a second pole of the third transistor, a second pole of the second transistor is coupled to a gate of the third transistor, and a gate of the second transistor is coupled to the corresponding first scan line;
a first pole of the third transistor is coupled to a second pole of the fourth transistor, a second pole of the third transistor is coupled to a first pole of the sixth transistor, and a gate of the third transistor is a first pole plate of a storage capacitor;
a first pole of the fourth transistor is coupled to the corresponding first data line, a second pole of the fourth transistor is coupled to the first pole of the third transistor, and a gate of the fourth transistor is coupled to the corresponding second scan line;
a gate of the fifth transistor is coupled to a corresponding light emission control signal line, a first pole of the fifth transistor is coupled to a power signal line, and a second pole of the fifth transistor is coupled to a first pole of the third transistor;
a gate of the sixth transistor is coupled to a corresponding light emission control signal line, a first pole of the sixth transistor is coupled to a second pole of the third transistor, and the second pole of the sixth transistor is coupled to an anode of the light emitting element;
a gate of the seventh transistor is coupled to the corresponding second reset signal line, a second pole of the seventh transistor is coupled to the second pole of the sixth transistor, and a first pole of the seventh transistor is coupled to the third initialization signal line;
the first plate of the storage capacitor is multiplexed as the grid electrode of the third transistor, and the second plate of the storage capacitor is coupled with the power signal wire.
A second aspect of the present invention provides a display device, including the display panel described above, and a photosensitive sensor, where the photosensitive sensor is located on a backlight side of the display panel, and an orthogonal projection of the photosensitive sensor on the display panel is located in the first display area.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention can control the display difference of the first display area and the second display area by controlling the first light emitting device and the second light emitting device to be independently reset.
Drawings
Fig. 1 is a schematic diagram illustrating a connection between a dummy pixel circuit and a first light emitting device according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a first pixel circuit according to an embodiment of the invention;
fig. 3 is a circuit layout diagram of a first pixel circuit according to an embodiment of the invention;
fig. 4 is a circuit diagram of a second pixel circuit according to an embodiment of the invention;
fig. 5 is a circuit layout diagram of a second pixel circuit according to an embodiment of the invention;
fig. 6 is a schematic diagram of a third initialization signal line according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a third initialization signal line and a first data line according to an embodiment of the present invention;
FIG. 8 is a schematic winding diagram of a first data line according to an embodiment of the present invention;
fig. 9 is a schematic view of a first transition portion according to an embodiment of the present invention.
Reference numerals
A1-first display area A2-second display area
1-first pixel circuit 2-second pixel circuit 3-first light emitting device
4-second light emitting device 5-virtual pixel circuit
L1-connection trace
627-connecting electrode 627 a-first connecting electrode 627 b-second connecting electrode
31-first transfer hole 32-second transfer hole 33-third transfer hole 34-fourth transfer hole
35-fifth transfer hole 36-sixth transfer hole
111-winding part
1111-first transfer part 1112-second transfer part
10-first scanning line 11-first data line 12-second scanning line 13-second initialization signal line
14-first reset signal line 15-first initialization signal line 16-power signal line 17-light emission control signal line 18-second reset signal line 19-third initialization signal line
20-second data line
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
With the trend of full-screen, the display screen ratio of the mobile phone is an important index. The Camera is placed below the screen by a Full Display with Camera (FDC), and the area of a Display screen above the Camera can still be normally displayed, so that a Full screen is realized. In order to improve the light transmittance of the FDC region, it is general to avoid designing a pixel circuit in the FDC region, to keep only a light emitting device portion, and to make a light emitting area of the light emitting device small. The pixel circuit of the FDC area can adopt a virtual pixel circuit, and the virtual pixel circuit is a newly added pixel circuit after compressing the pixel circuit of the display area outside the FDC area. Since the dummy pixel circuit and the light emitting device of the FDC region have a certain distance therebetween, the dummy pixel circuit and the light emitting device of the FDC region are connected by a connection wiring.
Under low gray scale, the difference of display image quality can be caused by tiny current difference, and because the FDC area is different from the luminous area of the Normal area, and the FDC area has a capacitor caused by transparent wiring pull wires, the display difference exists between the area of the camera under the screen and the Normal display area.
The embodiment of the invention provides a display panel and a display device, which can solve the problem that a camera area and a normal display area under a screen have display difference.
An embodiment of the present invention provides a display panel including a first display area and a second display area at least partially surrounding the first display area;
the display panel includes: the pixel structure comprises a substrate base plate, a plurality of first pixel units and a plurality of second pixel units, wherein the plurality of first pixel units and the plurality of second pixel units are positioned on the substrate base plate, the first pixel units comprise first light-emitting devices and first pixel circuits, and the second pixel units comprise second light-emitting devices and second pixel circuits;
the first light emitting device is located in the first display area, the first pixel circuit, the second light emitting device and the second pixel circuit are located in the second display area, an orthographic projection of the second light emitting device on the substrate base plate and an orthographic projection of the second pixel circuit on the substrate base plate are at least partially overlapped, and the first light emitting device and the first pixel circuit are connected through a connecting wire;
the first and second light emitting devices are independently reset.
The embodiment of the invention can reduce the display difference between the first display area and the second display area by controlling the first light emitting device and the second light emitting device to be independently reset.
Optionally, the length of the connection trace is 2mm to 4 mm.
The length of the connecting wiring provided by the embodiment of the invention is 2-4 mm, so that the capacitance on the connecting wiring can be reduced, and the display effect can be improved.
Referring to fig. 1, 6 and 7, the display panel according to the embodiment of the present invention includes a first display region a1 and a second display region a 2. As an example, first display region a1 is an FDC region, and second display region a2 is a Normal region (Normal display region).
The first display region a1 retains only the first light emitting device 3 of the first pixel unit, and the first pixel circuit 1 of the first pixel unit is located in the second display region a2, which can ensure the light transmissivity of the first display region a 1. The first pixel circuit 1 is connected to the first light emitting device 3 through the transverse connection wiring L1, so that the first display region a1 can achieve a light emitting display effect.
The second display area a2 is also provided with the second light emitting device 4 and the second pixel circuit 2 of the second pixel unit. The orthographic projection of the second light emitting device 4 on the substrate and the orthographic projection of the second pixel circuit 2 on the substrate at least partially overlap.
Fig. 1 shows a second light emitting device 4, a first light emitting device 3, a second pixel circuit 2, a first pixel circuit 1, a connection electrode 627, a connection wiring L1. Each pixel circuit is connected to the light emitting device through the connection electrode 627. That is, each pixel cell has one connection electrode 627. That is, the second pixel circuit 2 is connected to the second light emitting device 4 through the connection electrode 627 (first connection electrode 627a), and the first pixel circuit 1 is connected to the first light emitting device 3 through the connection electrode 627 (second connection electrode 627 b).
For example, as shown in fig. 1, one end of the connection wiring L1 is connected to the first light emitting device 3, and the other end of the connection wiring L1 is connected to the first pixel circuit 1 through the connection electrode 627 (connection electrode second 627 b). For example, the connecting electrode 627 may be formed of a single conductive member, or may include two different conductive members located at different layers. For example, the connecting electrode 627 may include one conductive member in one conductive layer and another conductive member in another conductive layer.
As shown in fig. 1, one connecting trace L1 passes through the area where the pixel circuit of the pixel unit is located to connect the first pixel circuit 1 and the first light emitting device 3 on both sides of the pixel unit, respectively. For example, the area where the pixel circuits of the pixel unit are located overlaps with the plurality of connection wirings L1 passing through the area. The region in the second display area a2 where the first pixel circuits 1 are disposed may be referred to as an auxiliary area Ra, which may also be referred to as a transition area. Fig. 1 illustrates that one second pixel circuit 2 overlaps at most two connection traces L1, and in other embodiments, one second pixel circuit 2 may also overlap more connection traces L1. For example, in some embodiments, one second pixel circuit 2 may overlap with 5 to 15 connection wirings L1. How many connecting traces L1 a second pixel circuit 2 overlaps can be determined according to the needs. As shown in fig. 1, the first pixel circuit 1 may also overlap with the connection wiring L1 not connected thereto.
In some embodiments, the area where the first pixel circuit 1 is disposed may be obtained by compressing the size of the second pixel circuit 2 in the second direction. For example, as shown in fig. 1, in the auxiliary area, the first pixel circuits 1 are arranged in one column every set column of the second pixel circuits 2. For example, the number of columns of the second pixel circuits 2 between two adjacent columns of the first pixel circuits 1 may be determined as needed.
The embodiment of the invention independently resets the first and second light emitting devices 3 and 4 in order to reduce the display difference of the first light emitting device 3 of the first display region a1 and the second light emitting device 4 of the second display region a 2.
Optionally, the display panel further comprises: a third initialization signal line and a second initialization signal line positioned in the second display area;
the first light emitting device and the second light emitting device reset independently, specifically:
the first pixel circuit is coupled to the third initialization signal line, and the second pixel circuit is coupled to the second initialization signal line; the third initialization signal line is configured to provide a third initialization signal to the first pixel circuit, and the second initialization signal line is configured to provide a second initialization signal to the second pixel circuit.
According to the embodiment of the invention, the third initialization signal line is added, the first pixel circuit is coupled with the third initialization signal, the second pixel circuit is coupled with the second initialization signal line, so that the initialization signals of the first pixel circuit and the second pixel circuit can be separately set, and the purpose of independently controlling the first pixel circuit and the second pixel circuit is achieved.
Referring to fig. 2 to 7, the third initialization signal lines 19 are positioned at opposite sides of the first display area a1 in the first direction D1 and are not positioned at opposite sides of the second display area a2 in the second direction D2. The third initialization signal line 19 is coupled to the first pixel circuit 1, and the second initialization signal line 13 is coupled to the second pixel circuit 2.
The first direction and the second direction cross each other. Illustratively, the first direction and the second direction are perpendicular to each other.
Optionally, an absolute value of a voltage value corresponding to the third initialization signal is smaller than an absolute value of a voltage value corresponding to the second initialization signal.
According to the embodiment of the invention, the absolute value of the voltage value corresponding to the third initialization signal is smaller than the absolute value of the voltage value corresponding to the second initialization signal, so that the display difference between the FDC region and the Normal region due to the fact that the light-emitting areas are different and the FDC region has the ITO capacitor can be made up.
As an example, the voltage corresponding to the third initialization signal and the voltage corresponding to the second initialization signal are both negative voltages. The voltage value corresponding to the third initialization signal is-2.5V, and the voltage value corresponding to the second initialization signal is-3V.
In low gray scale, the difference of display image quality can be caused by small current difference, and because the FDC region and the Normal region have different light-emitting areas and an ITO capacitor exists in the FDC region, the initialization voltage is independently set to ensure that the off-state current is kept consistent, so that the display effect of the FDC region is kept consistent with that of the Normal region.
Optionally, the first pixel circuit and the second pixel circuit respectively include a seventh transistor, the third initialization signal line is coupled to a first pole of the seventh transistor in the first pixel circuit, and the seventh transistor is coupled to the first light emitting device;
the second initialization signal line is coupled to a first electrode of a seventh transistor in the second pixel circuit, the seventh transistor being coupled to a second light emitting device.
The embodiment of the present invention achieves the object of independently controlling the first pixel circuit and the second pixel circuit by separately setting the initialization signal of the seventh transistor in the first pixel circuit from the initialization signal of the seventh transistor in the second pixel circuit, and independently resetting the first light emitting device and the second light emitting device since the seventh transistor is configured to initialize the light emitting device.
Referring to fig. 2 to 7, the first pole of the seventh transistor T7 in the first pixel circuit is coupled to the third initialization signal line 19 through a fifth via 35, the fifth via 35 penetrating the first gate insulating layer, the second gate insulating layer, and the first interlayer insulating layer. A first pole of a seventh transistor T7 in the second pixel circuit is connected to the first source-drain metal layer through a fifth via 35 and then coupled to the second initialization signal line 13 through a sixth via 36, where the sixth via 36 penetrates through the first protection layer and the first planarization layer. The second pole of the seventh transistor T7 in the first pixel circuit and the second pixel circuit is coupled to the anode of the light emitting device, so that different initialization signals coupled to the first pole of the seventh transistor T7 can achieve different initialization of the anode of the light emitting device, further making the display effect of the light emitting devices in different display regions different.
Optionally, the display panel includes a first gate metal layer, a second gate metal layer, and a first source-drain metal layer, which are sequentially stacked in a direction away from the substrate, the third initialization signal line is made of the first source-drain metal layer, and the second initialization signal line is made of the second gate metal layer.
According to the embodiment of the invention, the third initialization signal line is made of the first source-drain metal layer, and the second initialization signal line is made of the second gate metal layer, so that the third initialization signal line and the second initialization signal line can be separated.
The display panel provided by the embodiment of the invention sequentially comprises the following components from a position close to a substrate base plate to a position far away from the substrate base plate: the organic light-emitting diode comprises an active layer, a first grid insulating layer, a first grid metal layer, a second grid insulating layer, a second grid metal layer, a first interlayer insulating layer, a first source drain metal layer, a first protective layer, a first flat layer, a second source drain metal layer, a second flat layer, ITO1, a third flat layer, ITO2, a fourth flat layer, ITO3, a fifth flat layer, an anode layer, a pixel defining layer, a spacer layer, an organic light-emitting function layer and a cathode layer.
Optionally, the third initialization signal line is located in the second display area;
the display panel further includes: the light-emitting control signal wire is made of a first grid metal layer, and the second reset signal wire is made of a first grid metal layer;
the orthographic projection of the third initialization signal line on the substrate base plate is positioned between the orthographic projection of the light-emitting control signal line on the substrate base plate and the orthographic projection of the second reset signal line on the substrate base plate.
In the embodiment of the invention, the orthographic projection of the third initialization signal line on the substrate base plate is positioned between the orthographic projection of the light-emitting control signal line on the substrate base plate and the orthographic projection of the second reset signal line on the substrate base plate, so that the third initialization signal line and the light-emitting control signal line or the second reset signal line can be prevented from forming parasitic capacitance.
Referring to fig. 3, the light emission control signal line 17 is configured to provide a light emission control signal to the fifth transistor T5 and the sixth transistor T6; the second reset signal line 18 is configured to supply a reset signal to the gate of the seventh transistor T7 included in the first pixel circuit. The third initialization signal line 19 is obtained by longitudinally compressing the line width, the pitch and the clearance space of the film layer. The orthographic projection of the third initialization signal line 19 on the substrate does not overlap with the orthographic projection of the light emission control signal line 17 on the substrate; the orthographic projection of the third initialization signal line 19 on the substrate does not overlap with the orthographic projection of the second reset signal line 18 on the substrate.
Further, the orthographic projection of the third initialization signal line 19 on the base substrate is located between the orthographic projection of the light emission control signal line 17 on the base substrate and the orthographic projection of the second reset signal line 18 on the base substrate.
Optionally, the plurality of second pixel units include a plurality of second pixel circuits, the plurality of second pixel circuits are divided into a plurality of groups of second pixel circuits, each group of second pixel circuits includes N rows of second pixel circuits, the N rows of second pixel circuits are arranged along a first direction, where N is greater than or equal to2 and N is a positive integer;
the plurality of first pixel units comprise a plurality of first pixel circuits, the plurality of first pixel circuits are divided into a plurality of columns of first pixel circuits, and the plurality of columns of first pixel circuits are arranged along a first direction.
Optionally, a column of first pixel circuits is disposed between two adjacent groups of the second pixel circuits. Optionally, each group of second pixel circuits comprises two columns of second pixel circuits.
Embodiments of the present invention implement a column of first pixel circuits by compressing every two columns of second pixel circuits, with shorter ITO connection traces than implementing a column of first pixel circuits by compressing every seven or eight columns of second pixel circuits.
Optionally, the second display area further comprises: the second display area further comprises: a plurality of dummy pixel circuits on the substrate base; the plurality of virtual pixel circuits are divided into a plurality of columns of virtual pixel circuits, and at least part of the virtual pixel circuits in at least one column of virtual pixel circuits are multiplexed into a first pixel circuit. According to the invention, at least part of the virtual pixel circuit positioned in the second display area is multiplexed into the first pixel circuit, so that a driving circuit corresponding to the first light-emitting device can be prevented from being arranged in the first display area, and the transmittance of the first display area is improved.
Fig. 6 shows only the dummy pixel circuit 5 multiplexed as the first pixel circuit 1, and does not show a portion of the dummy pixel circuit 5 not multiplexed as the first pixel circuit 1.
Referring to fig. 6 and 9, each two columns of the second pixel circuits 2 are laterally compressed to form a column of dummy pixel circuits 5, at least a part of the dummy pixel circuits 5 is multiplexed into the first pixel circuit 1, and the first pixel circuit 1 is used to drive the first light emitting device located in the first display area a 1. The second pixel circuits are arranged in a plurality of columns along the first direction, and every two columns of the second pixel circuits and one column of the first pixel circuits are alternately arranged.
Optionally, the display panel further comprises: a first data line positioned in the second display region and configured to supply a first data voltage to the first pixel circuit;
the first data line comprises two first switching parts and a second switching part, the two first switching parts extend along a first direction, the second switching part extends along a second direction, the two first switching parts are connected with two ends of the second switching part respectively, at least part of the first display area is located between the two first switching parts, and the first direction and the second direction are crossed.
According to the embodiment of the invention, as the first light emitting device and the first pixel circuit have a certain distance, and the main body parts of the first light emitting device and the first data line are positioned on the same straight line extending along the second direction, the first data line can realize the purpose of providing the first data voltage for the first pixel circuit by adopting a winding design.
Referring to fig. 7 to 9, the display panel includes a first data line 11, and the first data line 11 includes a main body portion and a winding portion 111. Wherein, the main portion of the first data line 11 and the first light emitting device are located on the same straight line extending along the second direction.
The winding portion 111 of the first data line 11 includes two first junctions 1111 and a second junction 1112. The first transition portion 1111 extends along the first direction D1, and the second transition portion 1112 extends along the second direction D2.
The main portion of the first data line 11 is coupled to one of the first switch portions 1111 through the first switch hole 31, wherein one of the first switch portions 1111 is coupled to the second switch portion 1112 through the second switch hole 32, the second switch portion 1112 is coupled to the other first switch portion 1111 through the third switch hole 33, and the other first switch portion is switched back to the main portion of the first data line 11 through the fourth switch hole 34. At least a portion of the first display area a1 is disposed between the two first transfer portions 1111.
Optionally, the two first switching parts and the third initialization signal line are made of the same material in the same layer;
the orthographic projection of the first transfer part on the substrate base plate is positioned between the orthographic projection of the light-emitting control signal line on the substrate base plate and the orthographic projection of the second reset signal line on the substrate base plate.
According to the embodiment of the invention, the longitudinal film layer, the distance and the clearance area space are compressed, and the longitudinal pitch is kept unchanged, so that not only the third initialization signal line is compressed, but also the first switching part is compressed, and the switching problem of the first data line is solved.
Referring to fig. 7, the first transfer portions are not located at two opposite sides of the first display area a1 in the first direction D1, but located at two opposite sides of the second display area a2 in the second direction D2, at different positions from the third initialization signal lines. The transverse signal lines obtained by the longitudinal compression are divided into two types, one is used as a third initialization signal line, and the other is used as a transverse patch cord of the first data line.
Optionally, the second via is made of a second source-drain metal layer.
According to the embodiment of the invention, the second switching part is made of the second source-drain metal layer, and the first switching part is made of the first source-drain metal layer, so that the overlapping capacitance on the first data line can be reduced.
In the prior art, due to the limitation of the switching mode, overlapping capacitance is generated between the main body part of one data line and a plurality of transverse switching parts included by other data lines, but the switching mode of the invention is more flexible, and the first data line is prevented from generating more overlapping capacitance in the switching process.
Optionally, the display panel further comprises: a second data line configured to provide a second data voltage to the column of virtual pixel circuits, the second data line coupled with the virtual pixel circuits, at least a portion of the second data line multiplexed as the second switching section.
The embodiment of the invention realizes the longitudinal switching of the first data line by multiplexing at least part of the second data line into the second switching part.
Referring to fig. 7 and 9, the second data line 20 is connected to the dummy pixel circuit 5. When the dummy pixel circuit 5 is multiplexed as the first pixel circuit 1, the first data line 11 is configured to provide the first data voltage to the first pixel circuit 1, and at this time, a main portion of the first data line 11 and the first light emitting device 3 are located on the same straight line extending along the second direction, a certain distance exists between the first data line 11 and the second data line 20, and the first data line 11 needs to be switched to the second data line 20, so that at least a portion of the second data line is multiplexed as the second switching portion 1112 of the first data line 11.
Optionally, the display panel further comprises:
a first initialization signal line, a power signal line, a first reset signal line, a first scan line and a second scan line;
the first pixel driving circuit further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a storage capacitor; wherein, the first and the second end of the pipe are connected with each other,
a gate of the first transistor is coupled to the first reset signal line, and a first pole of the first transistor is coupled to the first initialization signal line; a second pole of the first transistor is coupled to a gate of the third transistor;
a first pole of the second transistor is coupled to a second pole of the third transistor, a second pole of the second transistor is coupled to a gate of the third transistor, and a gate of the second transistor is coupled to the corresponding first scan line;
a first pole of the third transistor is coupled to a second pole of the fourth transistor, a second pole of the third transistor is coupled to a first pole of the sixth transistor, and a gate of the third transistor is a first pole plate of a storage capacitor;
a first pole of the fourth transistor is coupled to the corresponding first data line, a second pole of the fourth transistor is coupled to the first pole of the third transistor, and a gate of the fourth transistor is coupled to the corresponding second scan line;
a gate of the fifth transistor is coupled to a corresponding light emission control signal line, a first pole of the fifth transistor is coupled to a power signal line, and a second pole of the fifth transistor is coupled to a first pole of the third transistor;
a gate of the sixth transistor is coupled to a corresponding light emission control signal line, a first pole of the sixth transistor is coupled to a second pole of the third transistor, and the second pole of the sixth transistor is coupled to an anode of the light emitting element;
a gate of the seventh transistor is coupled to the corresponding second reset signal line, a second pole of the seventh transistor is coupled to the second pole of the sixth transistor, and a first pole of the seventh transistor is coupled to the third initialization signal line;
the first plate of the storage capacitor is multiplexed as the grid electrode of the third transistor, and the second plate of the storage capacitor is coupled with the power signal line.
The first pixel circuit provided by the embodiment of the invention is a 7T1C pixel circuit, and can ensure stable display of the first light-emitting device.
Referring to fig. 2 to 7, the first transistor is a first reset transistor, the second transistor is a compensation transistor, the third transistor is a driving transistor, the fourth transistor is a data writing transistor, the fifth transistor is a first light emitting control transistor, the sixth transistor is a second light emitting control transistor, and the seventh transistor is a second reset transistor.
A second pole of the first reset transistor T1 is coupled to the gate of the driving transistor T3.
The gate of the first reset transistor T1 is coupled to the first reset signal line 14;
the initialization signal lines include a first initialization signal line 15 and a second initialization signal line 13;
a first pole of the first reset transistor T1 is coupled to the first initialization signal line 15.
The scan lines include a first scan line 10 and a second scan line 12;
a first pole of the compensation transistor T2 is coupled to the second pole of the driving transistor T3, a second pole of the compensation transistor T2 is coupled to the gate of the driving transistor T3, and a gate of the compensation transistor T2 is coupled to the first scan line 10;
a first pole of the data write transistor T4 is coupled to the corresponding first data line 11, a second pole of the data write transistor T4 is coupled to a first pole of the driving transistor T3, and a gate of the data write transistor T4 is coupled to the second scan line 12;
a gate of the first light emission controlling transistor T5 is coupled to the corresponding light emission control signal line 17, a first pole of the first light emission controlling transistor T5 is coupled to the power signal line 16, and a second pole of the first light emission controlling transistor T5 is coupled to the first pole of the driving transistor T3;
the gate of the second light emission control transistor T6 is coupled to the corresponding light emission control signal line 17, the first electrode of the second light emission control transistor T6 is coupled to the second electrode of the driving transistor T3, the second electrode of the second light emission control transistor T6 is coupled to the anode of the light emitting element EL, and the cathode of the light emitting element EL receives the negative power supply signal VSS;
the gate of the second reset transistor T7 is coupled to the second reset signal line 18, the second pole of the second reset transistor T7 is coupled to the second pole of the second light emission controlling transistor T6, and the first pole of the second reset transistor T7 is coupled to a second initialization signal line 13;
illustratively, the second reset signal line 18 to which the gate of the second reset transistor T7 in the current first pixel circuit is coupled is the same line as the first reset signal line 14 to which the gate of the first reset transistor T1 in the next row of first pixel circuits adjacent in the first direction is coupled.
The second initialization signal line 13 or the first initialization signal line 15 is made using a second gate metal layer.
A second aspect of the present invention provides a display device, including the display panel described above, and a photosensitive sensor, where the photosensitive sensor is located on a backlight side of the display panel, and an orthogonal projection of the photosensitive sensor on the display panel is located in the first display area.
The Display panel comprises an OLED Display panel, a micro (micrometer Light Emitting Diode) Display panel, a QLED (Quantum-dot Light Emitting Diode) Display panel and an LCD (Liquid Crystal Display) Display panel.
The sensor is used for under-screen shooting, under-screen fingerprint identification or under-screen bottom identification.
The display device includes but is not limited to: radio frequency unit, network module, audio output unit, input unit, sensor, display unit, user input unit, interface unit, memory, processor, and power supply. It will be appreciated by those skilled in the art that the above-described display device is not limited in its construction and that the display device may include more or fewer of the elements described above, or some of the elements may be combined, or a different arrangement of elements may be used. In the embodiment of the present invention, the display device includes, but is not limited to, a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
The display device may be: the display device comprises a television, a display, a digital photo frame, a mobile phone, a tablet personal computer and any other product or component with a display function, wherein the display device further comprises a flexible circuit board, a printed circuit board and a back plate.
In the embodiments of the methods of the present invention, the sequence numbers of the steps are not used to limit the sequence of the steps, and for those skilled in the art, the sequence of the steps is not changed without creative efforts.
It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the embodiments, since they are substantially similar to the product embodiments, the description is simple, and the relevant points can be referred to the partial description of the product embodiments.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (14)
1. A display panel comprising a first display region and a second display region, the second display region at least partially surrounding the first display region;
the display panel includes: the pixel structure comprises a substrate base plate, a plurality of first pixel units and a plurality of second pixel units, wherein the plurality of first pixel units and the plurality of second pixel units are positioned on the substrate base plate, the first pixel units comprise first light-emitting devices and first pixel circuits, and the second pixel units comprise second light-emitting devices and second pixel circuits;
the first light emitting device is located in the first display area, the first pixel circuit, the second light emitting device and the second pixel circuit are located in the second display area, an orthographic projection of the second light emitting device on the substrate base plate and an orthographic projection of the second pixel circuit on the substrate base plate are at least partially overlapped, and the first light emitting device and the first pixel circuit are connected through a connecting wire;
the first and second light emitting devices are independently reset.
2. The display panel according to claim 1, characterized in that the display panel further comprises:
a third initialization signal line and a second initialization signal line in the second display area;
the first light emitting device and the second light emitting device reset independently, specifically:
the first pixel circuit is coupled to the third initialization signal line, and the second pixel circuit is coupled to the second initialization signal line; the third initialization signal line is configured to provide a third initialization signal to the first pixel circuit, and the second initialization signal line is configured to provide a second initialization signal to the second pixel circuit.
3. The display panel according to claim 2, wherein an absolute value of a voltage value corresponding to the third initialization signal is smaller than an absolute value of a voltage value corresponding to the second initialization signal.
4. The display panel according to claim 2, wherein the first pixel circuit and the second pixel circuit each include a seventh transistor, the third initialization signal line is coupled to a first electrode of the seventh transistor in the first pixel circuit, and the seventh transistor is coupled to the first light emitting device;
the second initialization signal line is coupled to a first electrode of a seventh transistor in the second pixel circuit, the seventh transistor being coupled to a second light emitting device.
5. The display panel according to claim 2, wherein the display panel comprises a first gate metal layer, a second gate metal layer and a first source-drain metal layer which are sequentially stacked along a direction away from the substrate, the third initialization signal line is made of the first source-drain metal layer, and the second initialization signal line is made of the second gate metal layer.
6. The display panel according to claim 5, wherein the third initialization signal line is located in the second display region;
the display panel further includes: the light-emitting control signal wire is made of a first grid metal layer, and the second reset signal wire is made of a first grid metal layer;
the orthographic projection of the third initialization signal wire on the substrate base plate is positioned between the orthographic projection of the light-emitting control signal wire on the substrate base plate and the orthographic projection of the second reset signal wire on the substrate base plate.
7. The display panel according to claim 6, wherein the plurality of second pixel units comprise a plurality of second pixel circuits, the plurality of second pixel circuits are divided into a plurality of groups of second pixel circuits, each group of second pixel circuits comprises N columns of second pixel circuits, the N columns of second pixel circuits are arranged along a first direction, wherein N is greater than or equal to2 and N is a positive integer;
the plurality of first pixel units comprise a plurality of first pixel circuits, the plurality of first pixel circuits are divided into a plurality of columns of first pixel circuits, and the plurality of columns of first pixel circuits are arranged along a first direction.
8. The display panel according to claim 7, wherein a column of the first pixel circuits is disposed between two adjacent groups of the second pixel circuits.
9. The display panel according to claim 8, characterized in that the display panel further comprises: a first data line positioned in the second display region and configured to supply a first data voltage to the first pixel circuit;
the first data line comprises two first switching parts and a second switching part, the two first switching parts extend along the first direction, the second switching part extends along the second direction, the two first switching parts are connected with two ends of the second switching part respectively, at least part of the first display area is located between the two first switching parts, and the first direction and the second direction are crossed.
10. The display panel according to claim 9, wherein the two first switching portions and the third initialization signal line are made of the same material in the same layer;
the orthographic projection of the first transfer part on the substrate base plate is positioned between the orthographic projection of the light-emitting control signal line on the substrate base plate and the orthographic projection of the second reset signal line on the substrate base plate.
11. The display panel according to claim 9, wherein the second via is formed by a second source-drain metal layer.
12. The display panel according to claim 11, wherein the second display region further comprises: a plurality of dummy pixel circuits on the substrate base; the plurality of virtual pixel circuits are divided into a plurality of columns of virtual pixel circuits, and at least part of the virtual pixel circuits in at least one column of virtual pixel circuits are multiplexed into a first pixel circuit;
the display panel further includes: a second data line configured to provide a second data voltage to the column of dummy pixel circuits, at least a portion of the second data line being multiplexed as the second switching section.
13. The display panel according to claim 9, characterized in that the display panel further comprises:
the display device comprises a first initialization signal line, a power signal line, a first reset signal line, a first scanning line and a second scanning line;
the first pixel driving circuit further includes: the storage capacitor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a storage capacitor; wherein the content of the first and second substances,
a gate of the first transistor is coupled to the first reset signal line, and a first pole of the first transistor is coupled to the first initialization signal line; a second pole of the first transistor is coupled to a gate of the third transistor;
a first pole of the second transistor is coupled to a second pole of the third transistor, a second pole of the second transistor is coupled to a gate of the third transistor, and a gate of the second transistor is coupled to the corresponding first scan line;
a first pole of the third transistor is coupled to a second pole of the fourth transistor, a second pole of the third transistor is coupled to a first pole of the sixth transistor, and a gate of the third transistor is a first pole plate of a storage capacitor;
a first pole of the fourth transistor is coupled to the corresponding first data line, a second pole of the fourth transistor is coupled to the first pole of the third transistor, and a gate of the fourth transistor is coupled to the corresponding second scan line;
a gate of the fifth transistor is coupled to a corresponding light emission control signal line, a first pole of the fifth transistor is coupled to a power signal line, and a second pole of the fifth transistor is coupled to a first pole of the third transistor;
a gate of the sixth transistor is coupled to a corresponding light emission control signal line, a first pole of the sixth transistor is coupled to a second pole of the third transistor, and the second pole of the sixth transistor is coupled to an anode of the light emitting element;
a gate of the seventh transistor is coupled to the corresponding second reset signal line, a second pole of the seventh transistor is coupled to the second pole of the sixth transistor, and a first pole of the seventh transistor is coupled to the third initialization signal line;
the first plate of the storage capacitor is multiplexed as the grid electrode of the third transistor, and the second plate of the storage capacitor is coupled with the power signal line.
14. A display device comprising the display panel according to any one of claims 1 to 13, and a light-sensitive sensor located on a backlight side of the display panel, wherein an orthogonal projection of the light-sensitive sensor on the display panel is located in the first display region.
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| CN202210343669.5A CN114725173A (en) | 2022-03-31 | 2022-03-31 | Display panel and display device |
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| CN202210343669.5A CN114725173A (en) | 2022-03-31 | 2022-03-31 | Display panel and display device |
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| CN115000147A (en) * | 2022-08-01 | 2022-09-02 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
| CN115346486A (en) * | 2022-07-13 | 2022-11-15 | 武汉天马微电子有限公司 | Display panel and display device |
| CN115938284A (en) * | 2022-11-11 | 2023-04-07 | 武汉天马微电子有限公司 | Display panel and display device |
| WO2023240456A1 (en) * | 2022-06-14 | 2023-12-21 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
| WO2024031531A1 (en) * | 2022-08-11 | 2024-02-15 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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| WO2023240456A1 (en) * | 2022-06-14 | 2023-12-21 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
| CN115346486A (en) * | 2022-07-13 | 2022-11-15 | 武汉天马微电子有限公司 | Display panel and display device |
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| WO2024046047A1 (en) * | 2022-08-31 | 2024-03-07 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
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