CN114710138B - Multi-channel amplification attenuation phase-shift serial port control multifunctional chip - Google Patents
Multi-channel amplification attenuation phase-shift serial port control multifunctional chip Download PDFInfo
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- CN114710138B CN114710138B CN202210637624.9A CN202210637624A CN114710138B CN 114710138 B CN114710138 B CN 114710138B CN 202210637624 A CN202210637624 A CN 202210637624A CN 114710138 B CN114710138 B CN 114710138B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/36—Networks for connecting several sources or loads, working on the same frequency band, to a common load or source
- H03H11/365—Networks for connecting several sources or loads, working on the same frequency band, to a common load or source particularly adapted as input circuit for receivers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/16—Networks for phase shifting
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/24—Frequency-independent attenuators
- H03H11/245—Frequency-independent attenuators using field-effect transistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a multi-channel amplification attenuation phase-shift serial port control multifunctional chip, which belongs to the technical field of integrated circuit design and comprises a three-level amplification switch network, a one-to-three power distribution network, a first numerical control attenuation phase-shift network, a second numerical control attenuation phase-shift network, a third numerical control attenuation phase-shift network, a serial drive network and a direct-pass network; the invention has the advantages of multi-channel signal switching work, high channel isolation, low noise, high gain, low power consumption, high attenuation phase-shifting precision, high integration degree and the like.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a multi-channel amplification attenuation phase-shift serial port control multifunctional chip.
Background
Along with the development of radar technology, requirements of miniaturization, light weight, reliable performance and the like are provided for a receiving front end, a receiver is developing towards high integration and microminiaturization, a multichannel receiver in the fields is a core component of a phased array radar, more T/R modules are needed because the number of antenna array surface sub-arrays of the phased array radar can reach dozens to hundreds, and a receiving circuit integrating multiple channels in a receiving chip can reduce the overall weight and volume of a T/R assembly, so that the miniaturization and integration development of the phased array radar is facilitated, and the phased array radar has good and wide application prospects. But also put forward higher design requirements on the performances of the multi-channel simultaneous working such as low noise, low power consumption, high amplitude and phase control precision, high integration degree, channel isolation degree, reliability and the like.
Disclosure of Invention
Aiming at the defects in the prior art, the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip provided by the invention has the advantages of multi-channel signal switching work, high channel isolation degree, low noise, high gain, low power consumption, high attenuation phase-shifting precision, high integration degree and the like.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a multi-channel amplification attenuation phase-shift serial port control multifunctional chip comprises a three-level amplification switch network, a one-to-three power distribution network, a first numerical control attenuation phase-shift network, a second numerical control attenuation phase-shift network, a third numerical control attenuation phase-shift network, a serial drive network and a direct-pass network;
the input end of the three-level amplification switch network is used as the radio frequency input end of the multi-channel amplification attenuation phase-shift serial port control multifunctional chip, the first output end of the three-level amplification switch network is connected with the input end of the one-to-three power distribution network, the second output end of the three-level amplification switch network is connected with the input end of the through network, the first output end of the one-to-three power distribution network is connected with the input end of the first numerical control attenuation phase-shift network, the second output end of the one-to-three power distribution network is connected with the input end of the second numerical control attenuation phase-shift network, and the third output end of the one-to-three power distribution network is connected with the input end of the third numerical control attenuation phase-shift network;
the straight-through network, the first numerical control attenuation phase-shifting network, the second numerical control attenuation phase-shifting network and the third numerical control attenuation phase-shifting network are also connected with the serial drive network;
the output end of the first numerical control attenuation phase-shift network is used as the first radio-frequency output end of the multi-channel amplification attenuation phase-shift serial port control multifunctional chip, the output end of the second numerical control attenuation phase-shift network is used as the second radio-frequency output end of the multi-channel amplification attenuation phase-shift serial port control multifunctional chip, the output end of the first numerical control attenuation phase-shift network is used as the third radio-frequency output end of the multi-channel amplification attenuation phase-shift serial port control multifunctional chip, and the output end of the through network is used as the fourth radio-frequency output end of the multi-channel amplification attenuation phase-shift serial port control multifunctional chip.
The invention has the beneficial effects that: the first numerical control attenuation phase-shifting network, the second numerical control attenuation phase-shifting network and the third numerical control attenuation phase-shifting network all comprise attenuation units and phase-shifting units with the same structure, wherein the attenuation units adopt an improved pi-shaped attenuation structure, and the structure can improve high-frequency additional phase shift and reduce the influence of high-frequency parasitic capacitance on attenuation precision by increasing the parallel capacitance of a series switch tube and the stacking form of a parallel switch tube; the phase shift unit adopts an improved reflection type phase shift structure, and the structure can improve high-frequency phase shift precision and amplitude modulation by increasing the form of a series capacitor of a series switch tube and a parallel capacitor of a parallel switch tube. The number of the attenuation phase-shift units can be increased according to the practical application.
Further, the three-stage amplification switch network comprises a capacitor C1;
one end of the capacitor C1 is used as an input end of the three-stage amplification switch network, and the other end of the capacitor C1 is respectively connected with one end of the resistor R1 and one end of the microstrip line TL 1;
the other end of the resistor R1 is connected with a grounded capacitor C7, a gate of a field effect transistor M4, a drain of the field effect transistor M4 and one end of a resistor R3 respectively, a source of the field effect transistor M4 is connected with a grounded resistor R2, the other end of the resistor R3 is connected with one end of the resistor R4, one end of a resistor R7, one end of an inductor L3, one end of a resistor R10 and the grounded capacitor C8 respectively and serves as a VD port of the three-stage amplification switch network, the other end of the resistor R10 is connected with the grounded capacitor C9, the other end of the resistor R7 is connected with one end of a grounded resistor R9 and one end of a resistor R8 respectively, and the other end of the resistor R4 is connected with one end of a grounded resistor R6 and one end of a resistor R5 respectively;
the other end of the microstrip line TL1 is connected to a gate of a field effect transistor M1, the source of the field effect transistor M1 is grounded, the drain of the field effect transistor M1 is connected to one end of a capacitor C2 and one end of an inductor L1 respectively, the other end of the capacitor C2 is connected to the other end of a resistor R5 and one end of a microstrip line TL2 respectively, the other end of the microstrip line TL2 is connected to a gate of the field effect transistor M2, the other end of the inductor L1 is connected to the sources of a grounded capacitor C5 and a field effect transistor M2 respectively, the drain of the field effect transistor M2 is connected to one end of a capacitor C3 and one end of an inductor L3 respectively, the other end of the capacitor C3 is connected to the other end of the microstrip line R3 and one end of the microstrip line TL3 respectively, the other end of the microstrip line 3 is connected to the gate of the field effect transistor M3, the other end of the drain of the inductor L3 is connected to one end of the microstrip line 3, the other end of the microstrip line TL4 is connected with one end of a capacitor C4, the other end of the capacitor C4 is respectively connected with one end of the microstrip line TL5 and the source electrode of the field effect transistor M5, and the drain electrode of the field effect transistor M7, the other end of the microstrip line TL5 is respectively connected with one end of a resistor R11 and the drain electrode of the field effect transistor M6, the other end of the resistor R11 is connected with the source electrode of the field effect transistor M6, and is used as a first output end of the three-stage amplification switch network, the grid electrode of the field effect transistor M6 is used as a Ve port of the three-stage amplification switch network, the drain electrode of the field effect transistor M5 is grounded, the grid electrode of the field effect transistor M5 is used as a Vf port of the three-stage amplification switch network, the grid electrode of the field effect transistor M7 is used as a Vg port of the three-stage amplification switch network, the source electrode of the field effect transistor M7 is connected with one end of a microstrip line TL6, the other end of the microstrip line TL6 is used as a second output end of the three-stage amplification switch network;
and the VD port, the Ve port, the Vf port and the Vg port are connected with corresponding ports of the serial drive network.
The beneficial effects of the above further scheme are: the public channel of the invention adopts a current multiplexing three-stage amplification switch network, and realizes the switching characteristics of low noise, high gain, low power consumption, low insertion loss and high isolation switches. The bias part adopts an active bias network and a passive bias network, and the active bias can reduce the sensitivity of the circuit to process fluctuation and improve the linearity of the circuit at the same time. The power supply feed port adopts parallel C to ground and series RC to ground circuits to mainly realize the suppression of low-frequency and high-frequency self-excitation unstable signals of the power supply. VD is the working drain voltage of the three-stage amplification switch network.
Further, the one-to-three power division network comprises a microstrip line TL 7;
one end of the microstrip line TL7 is used as an input end of the one-to-three power division network, the other end of the microstrip line TL7 is connected to one end of an inductor L4, one end of an inductor L5, and one end of an inductor L6, the other end of the inductor L4 is connected to one end of a ground capacitor C10, one end of a resistor R12, and one end of an inductor L7, the other end of the inductor L5 is connected to the other end of the resistor R12, one end of the inductor L8, and one end of the resistor R13, and the other end of the inductor L6 is connected to the other end of the resistor R13, one end of the inductor L9, and the ground capacitor C11;
the other end of the inductor L7 is connected with one end of a microstrip line TL8 and one end of a resistor R14, the other end of the resistor R14 is connected with the other end of the inductor L8, one end of the microstrip line TL9 and one end of a resistor R15, the other end of the resistor R15 is connected with the other end of the inductor L9 and one end of the microstrip line TL10, the other end of the microstrip line TL8 serves as a first output end of a one-to-three power distribution network, the other end of the microstrip line TL9 serves as a second output end of the one-to-three power distribution network, and the other end of the microstrip TL10 serves as a third output end of the one-to-three power distribution network.
The beneficial effects of the above further scheme are: the one-to-three power distribution network adopts a Wilkinson power divider structure and adopts lumped element design to reduce the area, and the structure can carry out equal-amplitude equal-phase equal-proportion distribution on radio frequency input signals, thereby ensuring the amplitude consistency of three channels and higher isolation between the channels.
Further, the first digitally controlled attenuated phase-shifting network includes a field effect transistor M8;
the drain electrode of the field effect transistor M8 is used as the input end of the first numerical control attenuation phase-shifting network and is respectively connected with one end of an inductor L10 and one end of an inductor L12, and the source electrode of the field effect transistor M8 is respectively connected with one end of an inductor L11 and one end of an inductor L13;
the other end of the inductor L10 is connected with one end of a capacitor C12 and one end of a resistor R16 respectively, the other end of the capacitor C12 is connected with the other end of an inductor L11, the other end of a resistor R16 and one end of a resistor R17 respectively, the other end of the resistor R17 is connected with the drain electrode of a field-effect tube M11, the source electrode of the field-effect tube M11 is connected with the drain electrode of the field-effect tube M12, and the source electrode of the field-effect tube M12 is grounded;
the other end of the inductor L12 is connected with one end of a capacitor C13, one end of a resistor R18 and one end of a resistor R19 respectively, the other end of the capacitor C13 is connected with the other end of an inductor L13 and the other end of a resistor R18 respectively, the other end of the resistor R19 is connected with the drain electrode of a field-effect tube M9, the source electrode of the field-effect tube M9 is connected with the drain electrode of the field-effect tube M10, and the source electrode of the field-effect tube M10 is grounded;
the source of the field-effect transistor M8 is further connected to one end of an inductor L14 and the drain of a field-effect transistor M13, the other end of the inductor L14 is connected to one end of an inductor L15 and the other end of an inductor L16, the other end of the inductor L16 is connected to the drain of a grounded capacitor C15 and the drain of the field-effect transistor M14, the source of the field-effect transistor M14 is grounded, and the other end of the inductor L15 is connected to the source of the field-effect transistor M13 through a capacitor C14 and serves as the output end of the first digitally controlled attenuated phase-shifting network;
the grid of the field-effect tube M12, the grid of the field-effect tube M11, the grid of the field-effect tube M9 and the grid of the field-effect tube M10 are connected with each other and are used as Vb1 ports of the first numerical control attenuation phase-shift network, the grid of the field-effect tube M8 is used as Va1 ports of the first numerical control attenuation phase-shift network, the grid of the field-effect tube M13 is used as Vc1 ports of the first numerical control attenuation phase-shift network piece, and the grid of the field-effect tube M14 is used as Vd1 ports of the first numerical control attenuation phase-shift network piece;
the Va1 port, the Vb1 port, the Vc1 port and the Vd1 port are connected with corresponding ports of a serial drive network.
Furthermore, the circuit structures of the second numerical control attenuation phase-shifting network and the third numerical control attenuation phase-shifting network are the same as the circuit structure of the first numerical control attenuation phase-shifting network;
the second numerically-controlled attenuation phase-shifting network is provided with a Va2 port, a Vb2 port, a Vc2 port and a Vd2 port of the second numerically-controlled attenuation phase-shifting network, and the Va2 port, the Vb2 port, the Vc2 port and the Vd2 port are all connected with corresponding ports of the serial drive network;
the third numerical control attenuation phase-shifting network is provided with a Va3 port, a Vb3 port, a Vc3 port and a Vd3 port of the third numerical control attenuation phase-shifting network, and the Va3 port, the Vb3 port, the Vc3 port and the Vd3 port are all connected with corresponding ports of the serial drive network.
The beneficial effects of the above further scheme are: the circuit structures of the first to third numerical control attenuation phase-shifting networks in the further scheme are the same so as to ensure the amplitude-phase consistency of the three channels. Wherein the attenuation unit adopts novel pi type structure, realizes high accuracy attenuation and low insertion loss characteristic, moves the unit and adopts novel reflection formula unit with shifting the phase, realizes that the high accuracy moves the phase and low insertion loss characteristic.
Further, the pass-through network comprises a field effect transistor M29;
the source of the field effect transistor M29 is used as a first input end of the through network, the drain of the field effect transistor M29 is connected with one end of a microstrip line TL11, the other end of the microstrip line TL11 is respectively connected with the source of the field effect transistor M30, the source of the field effect transistor M31 and one end of a resistor R28, the drain of the field effect transistor M30 is grounded, and the other end of the resistor R28 is connected with the drain of the field effect transistor M31 and is used as an output end of the through network;
the grid electrode of the field effect transistor M29 is connected with the grid electrode of the field effect transistor M31 and is used as a Vg port of the through network, and the grid electrode of the field effect transistor M30 is used as a Vh port of the through network;
and the Vg port and the Vh port are both connected with corresponding ports of the serial drive network.
The beneficial effects of the above further scheme are: the direct connection network is realized by adopting two series of parallel switch tubes, and has the characteristics of low insertion loss and matched output.
Drawings
FIG. 1 is a block diagram of a multi-channel attenuation phase-shift serial port control multifunctional chip provided by the invention.
FIG. 2 is a schematic diagram of a multi-channel attenuation phase-shift serial port control multifunctional chip circuit provided by the invention.
Fig. 3 is a schematic port diagram of a serial driving network according to the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Example 1:
the embodiment of the invention provides a multi-channel amplification attenuation phase-shift serial port control multifunctional chip, which comprises a three-level amplification switch network, a one-to-three power distribution network, a first numerical control attenuation phase-shift network, a second numerical control attenuation phase-shift network, a third numerical control attenuation phase-shift network, a serial drive network and a direct-pass network, wherein the three-level amplification switch network is connected with the first numerical control attenuation phase-shift network;
the input end of the three-level amplification switch network is used as the radio frequency input end of the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip, the first output end of the three-level amplification switch network is connected with the input end of a one-to-three power distribution network, the second output end of the three-level amplification switch network is connected with the input end of a through network, the first output end of the one-to-three power distribution network is connected with the input end of a first numerical control attenuation phase-shifting network, the second output end of the one-to-three power distribution network is connected with the input end of a second numerical control attenuation phase-shifting network, and the third output end of the one-to-three power distribution network is connected with the input end of a third numerical control attenuation phase-shifting network;
the straight-through network, the first numerical control attenuation phase-shifting network, the second numerical control attenuation phase-shifting network and the third numerical control attenuation phase-shifting network are also connected with the serial drive network;
the output end of the first numerical control attenuation phase-shifting network is used as a first radio frequency output end of the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip, the output end of the second numerical control attenuation phase-shifting network is used as a second radio frequency output end of the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip, the output end of the first numerical control attenuation phase-shifting network is used as a third radio frequency output end of the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip, and the output end of the through network is used as a fourth radio frequency output end of the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip.
As shown in fig. 2, the three-stage amplification switching network in the present embodiment includes a capacitor C1;
one end of the capacitor C1 is used as an input end of the three-stage amplification switch network, and the other end of the capacitor C1 is respectively connected with one end of the resistor R1 and one end of the microstrip line TL 1;
the other end of the resistor R1 is respectively connected with a grounding capacitor C7, a grid electrode of a field effect transistor M4, a drain electrode of the field effect transistor M4 and one end of a resistor R3, a source electrode of the field effect transistor M4 is connected with a grounding resistor R2, the other end of the resistor R3 is respectively connected with one end of the resistor R4, one end of a resistor R7, one end of an inductor L3, one end of a resistor R10 and the grounding capacitor C8 and serves as a VD port of the three-stage amplification switch network, the other end of the resistor R10 is connected with the grounding capacitor C9, the other end of the resistor R7 is respectively connected with one ends of a grounding resistor R9 and a resistor R8, and the other end of the resistor R4 is respectively connected with one ends of a grounding resistor R6 and a resistor R5;
the other end of the microstrip line TL1 is connected with the grid of the field effect transistor M1, the source of the field effect transistor M1 is grounded, the drain of the field effect transistor M1 is respectively connected with one end of a capacitor C2 and one end of an inductor L1, the other end of the capacitor C2 is respectively connected with the other end of a resistor R5 and one end of a microstrip line TL2, the other end of a microstrip line TL2 is connected with the grid of the field effect transistor M2, the other end of the inductor L1 is respectively connected with a grounded capacitor C5 and the source of the field effect transistor M2, the drain of the field effect transistor M2 is respectively connected with one end of a capacitor C3 and one end of an inductor L2, the other end of a capacitor C3 is respectively connected with the other end of a resistor R8 and one end of a microstrip line TL3, the other end of the microstrip line TL3 is connected with the grid of the microstrip line M3, the other end of the inductor L2 is respectively connected with the ground capacitor C6 and the source of the field effect transistor M3, the drain of the field effect transistor M3 is respectively connected with the other end of the microstrip line TL3 and one end of the inductor 4, the other end of the microstrip line TL4 is connected with one end of a capacitor C4, the other end of the capacitor C4 is connected with one end of a microstrip line TL5, a source electrode of a field effect transistor M5 and a drain electrode of a field effect transistor M7 respectively, the other end of the microstrip line TL5 is connected with one end of a resistor R11 and a drain electrode of the field effect transistor M6 respectively, the other end of a resistor R11 is connected with a source electrode of the field effect transistor M6 and serves as a first output end of the three-stage amplification switch network, a grid electrode of the field effect transistor M6 serves as a Ve port of the three-stage amplification switch network, a drain electrode of the field effect transistor M5 is grounded, a grid electrode of the field effect transistor M5 serves as a Vf port of the three-stage amplification switch network, a grid electrode of the field effect transistor M7 serves as a Vg port of the three-stage amplification switch network, a source electrode of the field effect transistor M7 is connected with one end of the microstrip line 6, and the other end of the microstrip line TL6 serves as a second output end of the three-stage amplification switch network;
the VD port, the Ve port, the Vf port and the Vg port are connected with corresponding ports of the serial driving network, wherein the VD port corresponds to the working positive voltage of the serial driving network, the Ve port and the Vf port correspond to the switch switching voltage required by the three-stage amplification switch network, and the Vg port corresponds to the switch switching signal required by the through network.
As shown in fig. 2, the one-to-three power division network in this embodiment includes a microstrip line TL 7;
one end of a microstrip line TL7 is used as an input end of a one-to-three power division network, the other end of the microstrip line TL7 is respectively connected with one end of an inductor L4, one end of an inductor L5 and one end of an inductor L6, the other end of the inductor L4 is respectively connected with one end of a grounded capacitor C10, one end of a resistor R12 and one end of an inductor L7, the other end of an inductor L5 is respectively connected with the other end of the resistor R12, one end of the inductor L8 and one end of the resistor R13, and the other end of the inductor L6 is respectively connected with the other end of the resistor R13, one end of the inductor L9 and the grounded capacitor C11;
the other end of the inductor L7 is connected with one end of a microstrip line TL8 and one end of a resistor R14 respectively, the other end of the resistor R14 is connected with the other end of the inductor L8, one end of the microstrip line TL9 and one end of a resistor R15 respectively, the other end of the resistor R15 is connected with the other end of the inductor L9 and one end of a microstrip line TL10 respectively, the other end of the microstrip line TL8 serves as a first output end of a one-to-three power distribution network, the other end of the microstrip line TL9 serves as a second output end of the one-to-three power distribution network, and the other end of the microstrip line TL10 serves as a third output end of the one-to-three power distribution network.
As shown in FIG. 2, the first digitally controlled attenuated phase-shifting network in this embodiment comprises a field effect transistor M8;
the drain electrode of the field effect transistor M8 is used as the input end of the first numerical control attenuation phase-shifting network and is respectively connected with one end of an inductor L10 and one end of an inductor L12, and the source electrode of the field effect transistor M8 is respectively connected with one end of an inductor L11 and one end of an inductor L13;
the other end of the inductor L10 is connected with one end of a capacitor C12 and one end of a resistor R16 respectively, the other end of the capacitor C12 is connected with the other end of an inductor L11, the other end of a resistor R16 and one end of a resistor R17 respectively, the other end of the resistor R17 is connected with the drain electrode of a field-effect tube M11, the source electrode of the field-effect tube M11 is connected with the drain electrode of the field-effect tube M12, and the source electrode of the field-effect tube M12 is grounded;
the other end of the inductor L12 is connected with one end of a capacitor C13, one end of a resistor R18 and one end of a resistor R19 respectively, the other end of the capacitor C13 is connected with the other end of the inductor L13 and the other end of the resistor R18 respectively, the other end of the resistor R19 is connected with the drain electrode of the field-effect tube M9, the source electrode of the field-effect tube M9 is connected with the drain electrode of the field-effect tube M10, and the source electrode of the field-effect tube M10 is grounded;
the source electrode of the field-effect tube M8 is also connected with one end of an inductor L14 and the drain electrode of the field-effect tube M13 respectively, the other end of the inductor L14 is connected with one end of an inductor L15 and one end of an inductor L16 respectively, the other end of the inductor L16 is connected with a grounded capacitor C15 and the drain electrode of the field-effect tube M14 respectively, the source electrode of the field-effect tube M14 is grounded, and the other end of the inductor L15 is connected with the source electrode of the field-effect tube M13 through a capacitor C14 and serves as the output end of the first numerical control attenuation phase-shift network;
the grid of the field-effect tube M12, the grid of the field-effect tube M11, the grid of the field-effect tube M9 and the grid of the field-effect tube M10 are connected with each other and are used as a Vb1 port of a first numerical control attenuation phase-shift network, the grid of the field-effect tube M8 is used as a Va1 port of the first numerical control attenuation phase-shift network, the grid of the field-effect tube M13 is used as a Vc1 port of the first numerical control attenuation phase-shift network piece, and the grid of the field-effect tube M14 is used as a Vd1 port of the first numerical control attenuation phase-shift network piece;
the Va1 port, Vb1 port, Vc1 port, and Vd1 port are all connected to corresponding ports of the serial drive network.
In this embodiment, the circuit structures of the second and third digitally controlled attenuation and phase-shift networks are the same as the circuit structure of the first digitally controlled attenuation and phase-shift network;
the second digital attenuation phase-shifting network is provided with a Va2 port, a Vb2 port, a Vc2 port and a Vd2 port of the second digital attenuation phase-shifting network, and the Va2 port, the Vb2 port, the Vc2 port and the Vd2 port are connected with corresponding ports of the serial drive network;
the third numerically-controlled attenuation phase-shifting network is provided with a Va3 port, a Vb3 port, a Vc3 port and a Vd3 port of the third numerically-controlled attenuation phase-shifting network, and the Va3 port, the Vb3 port, the Vc3 port and the Vd3 port are connected with corresponding ports of the serial drive network.
In the embodiment, ports Va 1-Vb 1 are attenuation control signals of a first numerical control attenuation phase-shifting network channel, and Vc 1-Vd 1 are phase-shifting control signals of the first numerical control attenuation phase-shifting network channel; va 2-Vb 2 are attenuation control signals of a second numerically-controlled attenuation phase-shift network channel, and Vc 2-Vd 2 are phase-shift control signals of the second numerically-controlled attenuation phase-shift network channel; va 3-Vb 3 are attenuation control signals of the third numerical control attenuation phase-shifting network channel, and Vc 3-Vd 3 are phase-shifting control signals of the third numerical control attenuation phase-shifting network channel.
As shown in fig. 2, the through network in the present embodiment includes a field effect transistor M29;
the source electrode of the field effect transistor M29 is used as a first input end of the through network, the drain electrode of the field effect transistor M29 is connected with one end of a microstrip line TL11, the other end of the microstrip line TL11 is respectively connected with the source electrode of the field effect transistor M30, the source electrode of the field effect transistor M31 and one end of a resistor R28, the drain electrode of the field effect transistor M30 is grounded, and the other end of the resistor R28 is connected with the drain electrode of the field effect transistor M31 and is used as an output end of the through network;
the grid electrode of the field effect transistor M29 is connected with the grid electrode of the field effect transistor M31 and is used as a Vg port of the through network, and the grid electrode of the field effect transistor M30 is used as a Vh port of the through network;
the Vg port and the Vh port are both connected with corresponding ports of the serial drive network and correspond to switch switching signals required by the through network.
As shown in fig. 3, the serial driving network in this embodiment integrates module units such as a super-buffer not gate, a not gate, an and gate, and level conversion, and implements a function of converting serial data into parallel data output; the three groups of Va 1-Vd 1, Va 2-Vd 2 and Va 3-Vd 3 are control signals required by the first-third attenuation phase-shifting networks, Ve and Vf are switch switching signals required by the three-stage amplification switch networks, Vg and Vh are switch switching signals required by the through networks, output is provided by the serial driving networks, and the change of the phase-shifting attenuation state is realized through high-low level switching. VD is a working positive voltage of the serial driving network, VS is a working negative voltage of the serial driving network, CLK is a clock signal, DATA is a DATA input signal, LOAD is a primary latch signal, END is a secondary latch signal, AD 0-AD 3 are chip selection signals, and SO is serial DATA output. CLK is a clock signal, DATA is a DATA input signal, LOAD is a primary latch signal, END is a secondary latch signal, AD 0-AD 3 are chip address bits, and SO is serial DATA output.
Example 2:
in this embodiment, a specific working principle and a specific process of the chip of the present invention are described with reference to fig. 2:
the radio frequency input signal enters a three-stage amplification switch network through an input end RFin to perform low-noise amplification of the signal and switch switching channel selection, and is switched to an amplitude-phase control state, the signal is subjected to equal-amplitude equal-phase distribution of the amplified radio frequency signal into three-way signals with consistent amplitudes and phases through a one-to-three-way power division network, and finally amplitude-phase conversion of four-way signals is performed through a numerical control phase-shifting attenuation network 1-3, wherein the attenuation unit adopts novel bridge T-shaped and pi-shaped structures, so that high-precision attenuation and low insertion loss characteristics are realized. The phase shift unit adopts a novel reflection type unit and a bridge high-low pass type unit, and high-precision phase shift and low insertion loss characteristics are realized. And when the direct connection state is switched, the signal is output through the direct connection network. The structure has the advantages of low noise, high gain, low power consumption, high integration, high channel isolation and high channel consistency, and can realize the simultaneous amplification, amplitude-phase control and direct state switching of multiple channels of radio frequency signals.
Claims (5)
1. A multi-channel amplification attenuation phase-shift serial port control multifunctional chip is characterized by comprising a three-level amplification switch network, a one-to-three power distribution network, a first numerical control attenuation phase-shift network, a second numerical control attenuation phase-shift network, a third numerical control attenuation phase-shift network, a serial drive network and a direct-pass network;
the input end of the three-level amplification switch network is used as the radio frequency input end of the multi-channel amplification attenuation phase-shift serial port control multifunctional chip, the first output end of the three-level amplification switch network is connected with the input end of the one-to-three power distribution network, the second output end of the three-level amplification switch network is connected with the input end of the through network, the first output end of the one-to-three power distribution network is connected with the input end of the first numerical control attenuation phase-shift network, the second output end of the one-to-three power distribution network is connected with the input end of the second numerical control attenuation phase-shift network, and the third output end of the one-to-three power distribution network is connected with the input end of the third numerical control attenuation phase-shift network;
the straight-through network, the first numerical control attenuation phase-shifting network, the second numerical control attenuation phase-shifting network and the third numerical control attenuation phase-shifting network are also connected with the serial drive network;
the output end of the first numerical control attenuation phase-shifting network is used as a first radio-frequency output end of the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip, the output end of the second numerical control attenuation phase-shifting network is used as a second radio-frequency output end of the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip, the output end of the first numerical control attenuation phase-shifting network is used as a third radio-frequency output end of the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip, and the output end of the through network is used as a fourth radio-frequency output end of the multi-channel amplification attenuation phase-shifting serial port control multifunctional chip;
the three-stage amplification switch network comprises a capacitor C1;
one end of the capacitor C1 is used as an input end of the three-stage amplification switch network, and the other end of the capacitor C1 is respectively connected with one end of the resistor R1 and one end of the microstrip line TL 1;
the other end of the resistor R1 is connected with a ground capacitor C7, a gate of a field effect transistor M4, a drain of the field effect transistor M4 and one end of a resistor R3 respectively, a source of the field effect transistor M4 is connected with a ground resistor R2, the other end of the resistor R3 is connected with one end of the resistor R4, one end of a resistor R7, one end of an inductor L3, one end of a resistor R10 and the ground capacitor C8 respectively and serves as a VD port of the three-stage amplification switch network, the other end of the resistor R10 is connected with the ground capacitor C9, the other end of the resistor R7 is connected with one end of a ground resistor R9 and one end of a resistor R8 respectively, and the resistor R4 is connected with one end of a ground resistor R6 and one end of a resistor R5 respectively;
the other end of the microstrip line TL1 is connected to a gate of a field effect transistor M1, the source of the field effect transistor M1 is grounded, the drain of the field effect transistor M1 is connected to one end of a capacitor C2 and one end of an inductor L1 respectively, the other end of the capacitor C2 is connected to the other end of a resistor R5 and one end of a microstrip line TL2 respectively, the other end of the microstrip line TL2 is connected to a gate of the field effect transistor M2, the other end of the inductor L1 is connected to the sources of a grounded capacitor C5 and a field effect transistor M2 respectively, the drain of the field effect transistor M2 is connected to one end of a capacitor C3 and one end of an inductor L3 respectively, the other end of the capacitor C3 is connected to the other end of the microstrip line R3 and one end of the microstrip line TL3 respectively, the other end of the microstrip line 3 is connected to the gate of the field effect transistor M3, the other end of the drain of the inductor L3 is connected to one end of the microstrip line 3, the other end of the microstrip line TL4 is connected with one end of a capacitor C4, the other end of the capacitor C4 is respectively connected with one end of the microstrip line TL5 and the source electrode of the field effect transistor M5, and the drain electrode of the field effect transistor M7, the other end of the microstrip line TL5 is respectively connected with one end of a resistor R11 and the drain electrode of the field effect transistor M6, the other end of the resistor R11 is connected with the source electrode of the field effect transistor M6, and is used as a first output end of the three-stage amplification switch network, the grid electrode of the field effect transistor M6 is used as a Ve port of the three-stage amplification switch network, the drain electrode of the field effect transistor M5 is grounded, the grid electrode of the field effect transistor M5 is used as a Vf port of the three-stage amplification switch network, the grid electrode of the field effect transistor M7 is used as a Vg port of the three-stage amplification switch network, the source electrode of the field effect transistor M7 is connected with one end of a microstrip line TL6, the other end of the microstrip line TL6 is used as a second output end of the three-stage amplification switch network;
and the VD port, the Ve port, the Vf port and the Vg port are connected with corresponding ports of the serial drive network.
2. The multi-functional chip of multi-channel amplification attenuation phase-shift serial port control according to claim 1, wherein the one-to-three power division network comprises a microstrip line TL 7;
one end of the microstrip line TL7 is used as an input end of the one-to-three power division network, the other end of the microstrip line TL7 is connected to one end of an inductor L4, one end of an inductor L5, and one end of an inductor L6, the other end of the inductor L4 is connected to one end of a ground capacitor C10, one end of a resistor R12, and one end of an inductor L7, the other end of the inductor L5 is connected to the other end of the resistor R12, one end of the inductor L8, and one end of the resistor R13, and the other end of the inductor L6 is connected to the other end of the resistor R13, one end of the inductor L9, and the ground capacitor C11;
the other end of the inductor L7 is connected with one end of a microstrip line TL8 and one end of a resistor R14, the other end of the resistor R14 is connected with the other end of the inductor L8, one end of the microstrip line TL9 and one end of a resistor R15, the other end of the resistor R15 is connected with the other end of the inductor L9 and one end of the microstrip line TL10, the other end of the microstrip line TL8 serves as a first output end of a one-to-three power distribution network, the other end of the microstrip line TL9 serves as a second output end of the one-to-three power distribution network, and the other end of the microstrip line TL10 serves as a third output end of the one-to-three power distribution network.
3. The multi-channel amplification attenuation phase-shift serial port control multifunctional chip as claimed in claim 1, wherein the first digitally controlled attenuation phase-shift network comprises a field effect transistor M8;
the drain electrode of the field effect transistor M8 is used as the input end of the first numerical control attenuation phase-shifting network and is respectively connected with one end of an inductor L10 and one end of an inductor L12, and the source electrode of the field effect transistor M8 is respectively connected with one end of an inductor L11 and one end of an inductor L13;
the other end of the inductor L10 is connected with one end of a capacitor C12 and one end of a resistor R16 respectively, the other end of the capacitor C12 is connected with the other end of an inductor L11, the other end of a resistor R16 and one end of a resistor R17 pair respectively, the other end of the resistor R17 is connected with the drain electrode of a field-effect tube M11, the source electrode of the field-effect tube M11 is connected with the drain electrode of the field-effect tube M12, and the source electrode of the field-effect tube M12 is grounded;
the other end of the inductor L12 is connected with one end of a capacitor C13, one end of a resistor R18 and one end of a resistor R19 respectively, the other end of the capacitor C13 is connected with the other end of an inductor L13 and the other end of a resistor R18 respectively, the other end of the resistor R19 is connected with the drain electrode of a field-effect tube M9, the source electrode of the field-effect tube M9 is connected with the drain electrode of the field-effect tube M10, and the source electrode of the field-effect tube M10 is grounded;
the source electrode of the field effect transistor M8 is also connected with one end of an inductor L14 and the drain electrode of a field effect transistor M13 respectively, the other end of the inductor L14 is connected with one end of an inductor L15 and the other end of an inductor L16 respectively, the other end of the inductor L16 is connected with a grounded capacitor C15 and the drain electrode of the field effect transistor M14 respectively, the source electrode of the field effect transistor M14 is grounded, and the other end of the inductor L15 is connected with the source electrode of the field effect transistor M13 through a capacitor C14 and serves as the output end of the first numerical control attenuation phase shift network;
the grid of the field-effect tube M12, the grid of the field-effect tube M11, the grid of the field-effect tube M9 and the grid of the field-effect tube M10 are connected with each other and are used as Vb1 ports of the first numerical control attenuation phase-shift network, the grid of the field-effect tube M8 is used as Va1 ports of the first numerical control attenuation phase-shift network, the grid of the field-effect tube M13 is used as Vc1 ports of the first numerical control attenuation phase-shift network piece, and the grid of the field-effect tube M14 is used as Vd1 ports of the first numerical control attenuation phase-shift network piece;
the Va1 port, the Vb1 port, the Vc1 port and the Vd1 port are connected with corresponding ports of a serial drive network.
4. The multi-channel amplification attenuation phase-shift serial port control multifunctional chip of claim 3, wherein the circuit structures of the second numerical control attenuation phase-shift network and the third numerical control attenuation phase-shift network are the same as the circuit structure of the first numerical control attenuation phase-shift network;
the second numerically-controlled attenuation phase-shifting network is provided with a Va2 port, a Vb2 port, a Vc2 port and a Vd2 port of the second numerically-controlled attenuation phase-shifting network, and the Va2 port, the Vb2 port, the Vc2 port and the Vd2 port are all connected with corresponding ports of the serial drive network;
the third numerical control attenuation phase-shifting network is provided with a Va3 port, a Vb3 port, a Vc3 port and a Vd3 port of the third numerical control attenuation phase-shifting network, and the Va3 port, the Vb3 port, the Vc3 port and the Vd3 port are all connected with corresponding ports of the serial drive network.
5. The multi-channel amplification attenuation phase-shift serial port control multifunctional chip as claimed in claim 1, wherein the pass-through network comprises a field effect transistor M29;
the source of the field effect transistor M29 is used as a first input end of the through network, the drain of the field effect transistor M29 is connected with the source of the field effect transistor M30, the source of the field effect transistor M31 and one end of the resistor R28 through a microstrip line TL11, the drain of the field effect transistor M30 is grounded, and the other end of the resistor R28 is connected with the drain of the field effect transistor M31 and is used as an output end of the through network;
the grid electrode of the field effect transistor M29 is connected with the grid electrode of the field effect transistor M31 and is used as a Vg port of the through network, and the grid electrode of the field effect transistor M30 is used as a Vh port of the through network;
and the Vg port and the Vh port are both connected with corresponding ports of the serial drive network.
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