CN114709204A - 多裸片封装结构、芯片及方法 - Google Patents

多裸片封装结构、芯片及方法 Download PDF

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CN114709204A
CN114709204A CN202111547464.0A CN202111547464A CN114709204A CN 114709204 A CN114709204 A CN 114709204A CN 202111547464 A CN202111547464 A CN 202111547464A CN 114709204 A CN114709204 A CN 114709204A
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die
flip
chip
substrate
embedded
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蒋航
肖德明
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本申请公开了一种多裸片封装结构、芯片及方法。该多裸片封装结构包括：嵌入裸片，被埋在基板中；倒装裸片，被放置在基板的上方，所述倒装裸片具有朝向基板的第一表面，该第一表面通过导体与嵌入裸片及基板电连接。所述多裸片封装结构降低了成本、提高了性能。

Description

多裸片封装结构、芯片及方法
技术领域
本发明涉及一种半导体封装，更具体地说，本发明涉及一种多裸片封装结构、芯片及方法。
背景技术
近几年来，客户端电子产品的要求在显著提高。微型化和可便携性成为势不可挡的趋势，促使芯片封装更加紧凑。相应地，便携式电子设备在具有更多功能和更好性能的同时，其体积也变得越来越小。因此，现今的功率供应***被要求具有更小的尺寸、更高的功率输出、更多的功能和更高的效率。在这些要求下，有些技术将开关器件如场效应晶体管和控制器集成进单片裸片。但是，通常来说，控制器采用互补金属氧化物半导体工艺(CMOS工艺)，需要18至20层掩膜制作工艺；而开关器件通常采用双扩散金属氧化物半导体工艺(DMOS工艺)，只需要8至9层掩膜制作工艺。因此，这种单裸片由于将开关器件和控制器一起制作，制作成本高。
发明内容
因此本发明的目的在于解决现有技术的上述技术问题，提出一种多裸片封装结构、芯片及方法。
根据本发明的实施例，提出了一种多裸片封装结构，包括：嵌入裸片，被埋在基板中；倒装裸片，被放置在基板的上方，所述倒装裸片具有朝向基板的第一表面，该第一表面通过导体与嵌入裸片及基板电连接。
根据本发明的实施例，还提出了一种多裸片封装芯片，包括：控制引脚，接收控制信号，所述控制引脚电连接至其上形成有控制电路的控制裸片；输入引脚，接收输入电压，该输入引脚电连接至其上形成有上端功率开关的第一裸片；开关引脚，电连接至第一裸片和其上形成有下端功率开关的第二裸片；接地引脚，电连接至第二裸片；其中：第一裸片、第二裸片和控制裸片的其中一个裸片为嵌入裸片，被埋在基板中；另外两个裸片为第一倒装裸片和第二倒装裸片，均被放置在基板上方。
根据本发明的实施例，还提出了一种多裸片封装的方法，包括：将嵌入裸片埋入基板，所述基板具有多层金属层；将倒装裸片放置在基板上方，所述倒装裸片具有朝向基板的顶面；将嵌入裸片、倒装裸片和基板塑封成封装。
根据本发明各方面的上述多裸片封装结构、芯片及方法，降低了成本、提高了性能。
附图说明
图1为根据本发明实施例的多裸片封装结构100的剖面结构示意图；
图2为根据本发明实施例的多裸片封装结构200的剖面结构示意图；
图3示意性地示出了根据本发明一个实施例的图2所示多裸片封装结构200的顶视图；
图4示意性地示出了根据本发明另一个实施例的图2所示多裸片封装结构200的顶视图；
图5为根据本发明实施例的包含两个倒装裸片的多裸片封装结构500的剖面结构示意图；
图6示意性地示出了根据本发明一个实施例的图5所示多裸片封装结构500的顶视图；
图7示意性地示出了根据本发明另一个实施例的图5所示多裸片封装结构500的顶视图；
图8为根据本发明实施例的降压变换电路800的电路结构示意图；
图9根据本发明实施例的包含两个嵌入裸片和两个倒装裸片的多裸片封装结构900的剖面结构示意图；
图10示意性示出了根据本发明实施例的多裸片封装的方法流程图1000。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且附图不一定是按比例绘制的。应当理解，当称元件“耦接到”或“连接到”另一元件时，它可以是直接耦接或耦接到另一元件或者可以存在中间元件。相反，当称元件“直接耦接到”或“直接连接到”另一元件时，不存在中间元件。相同的附图标记指示相同的元件。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
图1为根据本发明实施例的多裸片封装结构100的剖面结构示意图。在图1所示实施例中，所述多裸片封装结构100包括：嵌入裸片101，被埋在基板110中；倒装裸片102，被放置在基板110的上方，所述倒装裸片102具有朝向基板110的第一表面12T；其中倒装裸片102的第一表面通过导体与嵌入裸片101和基板110电连接。
在本发明一个实施例中，集成电路和电焊盘(如焊料凸块)形成在裸片的第一表面。该第一表面通常也被称为上表面或顶面；裸片具有与该第一表面相对的第二表面，该第二表面通常也被称为底面。
在本发明一个实施例中，“倒装裸片”是指裸片的接触区通过焊料凸块直接与引线框架或基板连接的任意裸片；“基板”是指封装级别的材料制成的载板，应用于类似印制电路板PCB中，包括多个金属层；“焊料凸块”是指用来直接电耦接两个接触区的球状或柱状金属小块(如铜柱)，该金属小块多以焊料填充。
在本发明一个实施例中，倒装裸片102和嵌入裸片101之间的导体包括焊料凸块112、金属线(如铜线)119和电接触点(如镭射过孔或焊料凸块)113；倒装裸片102和基板110底面之间的导体包括焊料凸块112和穿孔111。但是，本领域技术人员应当意识到，倒装裸片102和嵌入裸片101之间的金属线可不需要，如下文结合图2具体讨论。
在本发明的一个实施例中，电接触点113作为嵌入裸片101的输入输出端，并可经由穿孔114从基板110的底面引出。
图2为根据本发明实施例的多裸片封装结构200的剖面结构示意图。图2所示多裸片封装结构200与图1所示多裸片封装结构100相似，与图1所示多裸片封装结构100不同的是，在图2所示实施例中，嵌入裸片101至少有部分边缘与倒装裸片在垂直方向(如图2所示的Z方向)上交叠(重叠)，使得倒装裸片102和嵌入裸片101之间的导体无须包含金属线，从而使倒装裸片102和嵌入裸片101之间具有更小的寄生阻抗和最短的垂直焊料凸块。
在本发明的一个实施例中，垂直方向表示垂直于裸片平面的方向，即垂直于裸片第一平面和第二平面的方向。也就是说，垂直方向与裸片101和102正交。
图3示意性地示出了根据本发明一个实施例的图2所示多裸片封装结构200的顶视图。图4示意性地示出了根据本发明另一个实施例的图2所示多裸片封装结构200的顶视图。如图3和图4所示，倒装裸片102和嵌入裸片101被共同包封在一个封装外形(packageoutline)内，且嵌入裸片101和倒装裸片102有部分交叠(如虚线所示)。
在本发明的一个实施例中，多裸片封装结构可以包括不止一个倒装裸片，如多裸片封装结构可包括放置于基板之上的两个或更多个倒装裸片。如图5所示，为根据本发明实施例的包含两个倒装裸片的多裸片封装结构500的剖面结构示意图。具体来说，在图5所示实施例中，多裸片封装结构500包括：嵌入裸片101，被埋在基板110中；第一倒装裸片102和第二倒装裸片103，被放置在基板110的上方，其中第一倒装裸片102和第二倒装裸片103均具有朝向基板110的第一表面(12T、13T)，该第一倒装裸片102的第一表面12T和第二倒装裸片103的第一表面13T均通过导体与嵌入裸片101的第一表面11T和基板110接触。
在图5所示实施例中，第一倒装裸片102和基板110底面之间的导体、第二倒装裸片103和基板110底面之间的导体均包括焊料凸块112和穿孔111。第一倒装裸片102和嵌入裸片101之间的导体、第二倒装裸片103和嵌入裸片101之间的导体与图2一样，均包括焊料凸块112和电接触点113，而未包含有金属线。但是，本领域技术人员应当意识到，该第一倒装裸片102和嵌入裸片101之间的导体、及第二倒装裸片103和嵌入裸片101之间的导体可与图1一样，也包含金属线。
也就是说，在图5所示实施例中，嵌入裸片101的部分边缘与第二倒装裸片102的部分边缘在垂直方向(如图5所示Z方向)上有交叠，且嵌入裸片101的部分边缘与第二倒装裸片103的部分边缘在垂直方向上也有交叠，使得第一倒装裸片102与嵌入裸片101之间的导体、及第二倒装裸片与嵌入裸片101之间的导体无需包含金属线，从而使第一倒装裸片102和第二倒装裸片103与嵌入裸片101之间具有更小的寄生阻抗和最短的垂直焊料凸块。图5所示多裸片封装结构500的顶视图如图6和图7所示。
在本发明一个实施例中，垂直方向为垂直于裸片平面的方向，即垂直于裸片第一表面和第二表面的方向。也就是说，垂直方向正交于裸片101、102和103。
图6示意性地示出了根据本发明一个实施例的图5所示多裸片封装结构500的顶视图。图7示意性地示出了根据本发明另一个实施例的图5所示多裸片封装结构500的顶视图。如图6和图7所示，嵌入裸片101和第一倒装裸片102及第二倒装裸片103被共同包封在一个封装外形内，且嵌入裸片101和第一倒装裸片102及第二倒装裸片103部分交叠(如虚线所示)。
在本发明的一个实施例中，嵌入裸片101和倒装裸片(如第一倒装裸片102和第二倒装裸片103)可包括功率开关器件和用于控制功率开关器件的控制器。例如，嵌入裸片101可包括功率开关器件，倒装裸片可包括对应的控制器；或者倒装裸片可包括功率开关器件，嵌入裸片可包括对应的控制器。在本发明一个具体实施例中，第一倒装裸片102包括降压(buck)变换器中的上端FET(场效应晶体管)、第二倒装裸片103包括降压变换器中的下端FET、嵌入裸片101包括用以控制上端FET和下端FET的控制器。所述降压变换器可应用于多相直流-直流转换***。但是，本领域的技术人员应当意识到，在本发明的其他实施例中，嵌入裸片和倒装裸片可包括其他半导体器件。
图8为根据本发明实施例的降压变换器800的电路结构示意图。在图8所示实施例中，所述降压变换器800包括：多裸片封装芯片800C，所述芯片800C包括：控制引脚PWM，接收控制信号(如从前级电路输入)，该控制引脚PWM电耦接至其上形成有控制电路的控制裸片801；输入引脚Vin，接收输入电压，该输入引脚Vin电耦接至其上形成有上端功率开关的第一FET裸片802；开关引脚SW，电连接至第一FET裸片802和其上形成有下侧功率开关的第二FET裸片803；接地引脚GND，电连接至第二FET裸片803；其中控制裸片、第一FET裸片和第二FET裸片的其中一个裸片作为嵌入裸片，被埋在基板内，另外两个裸片分别作为第一倒装裸片和第二倒装裸片，被放置在基板之上。
在本发明一个实施例中，上端功率开关和下端功率开关由控制电路控制。
在本发明一个实施例中，嵌入裸片的部分边缘与第一倒装裸片的部分边缘及第二倒装裸片的部分边缘交叠。
继续参考图8，第一FET裸片802具有电连接至输入引脚Vin的第一端子1、电连接至开关引脚SW的第二端子2以及电连接至控制裸片801的控制端子。第二FET裸片803具有电连接至开关引脚SW的第一端子3、电连接至接地引脚GND的第二端子4、以及电连接至控制裸片801的控制端子。控制裸片801具有包括电连接至控制引脚PWM的输入端子7、电连接至第一FET裸片802控制端子的第一输出端子5、以及电连接至第二FET裸片803控制端子的第二输出端子6。
在本发明一个实施例中，降压变换电路800进一步包括：电感和电容，电连接至多裸片封装芯片800C的开关引脚SW，以提供输出电压VO。
前述根据本发明多个实施例的多裸片封装结构讨论了一个嵌入裸片和一个或更多个(如两个)倒装裸片共同包封在一个封装外形内。然而，在本发明其他实施例中，多裸片封装结构可以包括不止一个嵌入裸片与不止一个倒装裸片共同包封在一个封装外形内。也就是说，根据本发明的一个实施例，多裸片封装结构可包含任意所需数量的嵌入裸片和任意所需数量的倒装芯片一起包封在一个封装外形内。如图9所示，为根据本发明实施例的包含两个嵌入裸片和两个倒装裸片的多裸片封装结构900的剖面结构示意图。
具体来说，在图9所示实施例中，多裸片封装结构900包括：第一嵌入裸片101和第二嵌入裸片104，被埋在基板110中；第一倒装裸片102和第二倒装裸片103，被放置在基板110的上方，其中第一倒装裸片102和第二倒装裸片103均具有朝向基板110的第一表面(12T、13T)，该第一倒装裸片102的第一表面12T通过导体与第一嵌入裸片101和基板110接触，该第二倒装裸片103的第一表面13T也通过导体与第一嵌入裸片101、第二嵌入裸片104和基板110接触。
在图9所示实施例中，第一倒装裸片102和第一嵌入裸片101之间的导体、第二倒装裸片103和第一嵌入裸片101之间的导体均包括焊料凸块112、金属线119和和电接触点(如镭射通孔或焊料凸块)113。第二倒装裸片103和第二嵌入裸片104之间的导体仅包含焊料凸块112和电接触点113。也就是说，第一嵌入裸片101与第一倒装裸片102和第二倒装裸片103在垂直方向上有平移(即没有交叠)，而第二嵌入裸片104的部分边缘与第二倒装裸片的部分边缘有交叠。但是本领域技术人员应当意识到，第一嵌入裸片101的部分边缘也可以与第一倒装裸片102的部分边缘及第二倒装裸片103的部分边缘在垂直方向上有交叠，且第二倒装裸片104也可以与第二倒装裸片103在垂直方向上有平移。
前述根据本发明多个实施例的多裸片封装结构为小尺寸封装提供了更紧凑的解决方案，并且减小了寄生RLC(电阻、电感和电容)参数，带来了更好的性能。不同于传统技术，前述根据本发明多个实施例的多裸片封装结构可以采用不同的工艺来制作不同裸片(如倒装裸片用一种工艺、嵌入芯片用另一种工艺)，并将这些裸片封装在一起：一部分裸片(如嵌入裸片)被埋在基板里，另一部分裸片被放置在基板上方并通过导体(如焊料凸块)与基板、与嵌入裸片电接触。因此，总成本被降低。此外，在前述本发明的多个实施例中，嵌入裸片与倒装裸片在垂直于裸片平面的方向有交叠，使得封装尺寸更小，这进一步节省了费用并减小了寄生阻抗。
图10示意性示出了根据本发明实施例的多裸片封装的方法流程图1000。如图10所示，所述多裸片封装方法包括：
步骤1001，将嵌入裸片埋入基板，所述基板具有多层金属层。
步骤1002，将倒装裸片放置在基板上方，所述倒装裸片具有朝向基板的顶面。
步骤1003，将嵌入裸片、倒装裸片和基板塑封成封装。
在本发明一个实施例中，嵌入裸片的至少部分边缘与倒装裸片的部分边缘在正交于嵌入裸片平面的垂直方向上有交叠。
在本发明一个实施例中，嵌入裸片与倒装裸片在正交于嵌入裸片平面的垂直方向上有平移。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (10)

1.一种多裸片封装结构，包括：
嵌入裸片，被埋在基板中；
倒装裸片，被放置在基板的上方，所述倒装裸片具有朝向基板的第一表面，该第一表面通过导体与嵌入裸片及基板电连接。
2.如权利要求1所述的多裸片封装结构，其中：
所述嵌入裸片和倒装裸片之间的导体包括焊料凸块、金属线和电连接点；
所述倒装裸片和基板底面之间的导体包括焊料凸块和穿孔。
3.如权利要求1所述的多裸片封装结构，其中所述嵌入裸片的至少部分边缘与倒装裸片的部分边缘在垂直方向有交叠。
4.如权利要求1所述的多裸片封装结构，其中所述倒装裸片为第一倒装裸片，所述多裸片封装结构还包括：
第二倒装裸片，被放置在基板上方，该第二倒装裸片具有朝向基板的第一表面，该第一表面通过导体与嵌入裸片及基板电连接。
5.如权利要求4所述的多裸片封装结构，其中：
所述嵌入裸片的部分边缘与第一倒装裸片的部分边缘在垂直方向有交叠；
所述嵌入裸片的部分边缘与第二倒装裸片的部分边缘在垂直方向有交叠。
6.如权利要求4所述的多裸片封装结构，其中所述嵌入裸片为第一嵌入裸片，所述多裸片封装结构还包括：
第二嵌入裸片，被埋在基板中，所述第二倒装裸片的第一表面与该第二嵌入裸片电接触。
7.一种多裸片封装芯片，包括：
控制引脚，接收控制信号，所述控制引脚电连接至其上形成有控制电路的控制裸片；
输入引脚，接收输入电压，该输入引脚电连接至其上形成有上端功率开关的第一裸片；
开关引脚，电连接至第一裸片和其上形成有下端功率开关的第二裸片；
接地引脚，电连接至第二裸片；其中：
第一裸片、第二裸片和控制裸片的其中一个裸片为嵌入裸片，被埋在基板中；另外两个裸片为第一倒装裸片和第二倒装裸片，均被放置在基板上方。
8.如权利要求7所述的多裸片封装芯片，其中所述嵌入裸片的部分边缘与第一倒装裸片的部分边缘、及第二倒装裸片的部分边缘在垂直方向有交叠。
9.一种多裸片封装的方法，包括：
将嵌入裸片埋入基板，所述基板具有多层金属层；
将倒装裸片放置在基板上方，所述倒装裸片具有朝向基板的顶面；
将嵌入裸片、倒装裸片和基板塑封成封装。
10.如权利要求9所述的多裸片封装的方法，其中所述嵌入裸片的至少部分边缘与倒装裸片的部分边缘在垂直方向有交叠。
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