CN114706800B - High-speed data selection system and method based on FPGA - Google Patents

High-speed data selection system and method based on FPGA Download PDF

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CN114706800B
CN114706800B CN202210402012.1A CN202210402012A CN114706800B CN 114706800 B CN114706800 B CN 114706800B CN 202210402012 A CN202210402012 A CN 202210402012A CN 114706800 B CN114706800 B CN 114706800B
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data
module
data selection
fpga
input
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CN114706800A (en
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王雄儒
赵鑫鑫
姜凯
王帅
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Shandong Inspur Scientific Research Institute Co Ltd
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Shandong Inspur Scientific Research Institute Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Optical Communication System (AREA)
  • Stored Programmes (AREA)

Abstract

The invention discloses a high-speed data selection system and method based on FPGA, belonging to the field of FPGA application, the technical problem to be solved by the invention is that the traditional computer software communication data selection and processing rate is low, and the adopted technical scheme is as follows: the structure of the high-speed data selection board card comprises a high-speed data selection board card, wherein the high-speed data selection board card comprises an FPGA module, peripheral electronic device equipment and a PCB board, the peripheral electronic device equipment comprises an SFP optical module, an EEPROM memory and an RS232 interface, and the SFP optical module is used for converting optical signals input by optical fibers into electric signals and inputting the electric signals into the FPGA module; the EEPROM memory is used for pre-storing data selection information; the FPGA module is used for reading the data selection information prestored in the EEPROM after receiving the SFP optical module input data, and performing data decoding and selection processing; the RS232 interface is used for outputting the data result selected by the FPGA module to the PC end.

Description

High-speed data selection system and method based on FPGA
Technical Field
The invention relates to the field of FPGA application, in particular to a high-speed data selection system and method based on an FPGA.
Background
In recent years, the electronic information technology industry has been actively developed under the common effort of various related industries, and high-speed communication is increasingly applied to the electronic information field. With the rise of industries such as big data, internet of things and the like, huge user base numbers and data traffic also bring great challenges to the communication industry. As an important component of high-speed communications, data selection devices have been attracting attention. Traditional data selection is often realized by computer software, however, the software mode has a narrow nature that is difficult to break through in terms of information data selection speed. Under the background of big data age, because the data selection processing rate is low, massive information data tends to increase the failure rate of a software system, and the use experience of users is seriously affected by the reduction of reliability.
Disclosure of Invention
The technical task of the invention is to provide a high-speed data selection system and method based on an FPGA, which are used for solving the problems of low selection and processing rate of communication data of traditional computer software.
The technical task of the invention is realized in the following way, the high-speed data selection system based on the FPGA comprises a high-speed data selection board card, wherein the high-speed data selection board card comprises an FPGA module, peripheral electronic device equipment and a PCB (printed circuit board), the peripheral electronic device equipment comprises an SFP (small form factor pluggable) optical module, an EEPROM (electrically erasable programmable read-Only memory) and an RS232 interface, and the SFP optical module is used for converting optical signals input by an optical fiber into electric signals and inputting the electric signals into the FPGA module; the EEPROM memory is used for pre-storing data selection information; the FPGA module is used for reading the data selection information prestored in the EEPROM after receiving the SFP optical module input data, and performing data decoding and selection processing; the RS232 interface is used for outputting the data result selected by the FPGA module to the PC end.
Preferably, the peripheral electronic device of the high-speed data selection board further comprises a power interface, a power chip, a clock chip and a resistor-capacitor.
Preferably, the high-speed data selection board card is used for completing collection of optical signals, information interaction with peripheral equipment, power supply of the FPGA module, clock input and IO communication in various forms.
Preferably, the PCB board of the high-speed data selection board is used to provide carriers for FPGA modules and peripheral electronic devices, and provide SFP optical module bases and RS232 interfaces.
More preferably, the FPGA module comprises,
the data reading module is used for judging the type of an input signal and selectively reading preset data selection information stored in the EEPROM according to the corresponding data type;
the condition setting module is used for receiving the data selection information transmitted by the data reading module and setting data selection conditions;
the data selection module is used for receiving the data selection conditions set by the condition setting module, decoding and data selection processing the data information number input into the FIFO module, and comparing and selecting the data required by the user;
the input FIFO module is used for sequentially storing the input data streams;
the output FIFO module is used for receiving and storing the data selection result sent by the data selection module;
and the UART sending module is used for sequentially sending the data selection results stored in the output FIFO module to the PC end.
More preferably, the working process of the system is as follows:
(1) The data input optical fiber is connected to the SFP optical module, the RS232 data output end of the high-speed data selection board card is connected to the CH340 interface of the PC end, and data is waited to be received;
(2) Powering on the development board, programming a bit stream file to the FPGA module through the JTAG interface, and immediately starting normal operation of the high-speed data selection system;
(3) The SFP optical module converts the high-speed optical signals transmitted by the optical fibers into electric signals and transmits the electric signals to the FPGA module;
(4) After receiving the data, the FPGA module judges the data type, reads preset data selection information from the EEPROM, sets reasonable data selection conditions and further starts data screening and processing;
(5) And transmitting the data meeting the selection condition to the PC end through the RS232 interface and the USB data line.
A high-speed data selection method based on FPGA comprises the following steps:
s1, a user inserts an input optical fiber interface into a high-speed data selection board card, and connects an RS232 interface with a PC end by using an RS232-CH340 data line;
s2, turning on a power switch of the high-speed data selection board card, installing Vivado software on a computer system to be tested, and programming a bit file of the FPGA data selection project to a board card FPGA module through a JTAG data line;
s3, starting the upper computer running software installed on the PC end, checking the selection result of the high-speed data selection on the optical fiber input signals through a visual interface, and storing the data or applying the data in the next step according to the requirement by a user.
Preferably, in step S3, the user saves the data as required or applies the data to the next step as required, specifically as follows:
s301, data are converted by an SFP optical module and then input to an FPGA module, and input FIFO is used for storing input data streams;
s302, the data reading module selects and reads preset data selection information stored in the EEPROM according to the type of the input signal;
s303, setting data selection conditions by a condition setting module;
s304, after receiving the selection condition, the data selection module decodes the data signal input into the FIFO module, selects the needed data and sends the needed data to the output FIFO;
s305, the UART sending module sends and outputs the data selection result stored by the FIFO module to the PC end.
The high-speed data selection system and method based on the FPGA have the following advantages:
aiming at the problems of low communication data selection and processing speed of the traditional computer software, the invention reasonably applies the high-speed data processing capability of the FPGA chip, carries out high-speed conversion and decoding on the optical fiber input signals, carries out selection according to the requirements of users, and finally outputs the selection result to the PC end;
the signal acquisition and selection transmission rate of the FPGA chip adopted by the invention is higher, the transmission delay of a high-speed data selection system based on the FPGA is only one percent of that of the traditional software mode, and the data selection period is low to a subtle level;
the high-speed data selection board card converts optical signals transmitted by optical fibers into electric signals, decodes the signals through the FPGA, compares the signals with required data, performs data selection processing, and finally sends data selection results to a PC (personal computer) end;
and fourthly, the invention realizes the high-speed selection of the signals and improves the reliability of the data transmission selection process through a series of operations such as conversion, decoding, selection processing and the like of the optical fiber signals of the hardware board.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a block diagram of a high-speed data selection system based on an FPGA;
fig. 2 is a block diagram of the FPGA module.
Detailed Description
The FPGA-based high-speed data selection system and method of the present invention are described in detail below with reference to the accompanying drawings and specific embodiments.
Examples:
as shown in fig. 1, the present embodiment provides a high-speed data selection system based on an FPGA, where the structure of the high-speed data selection system includes a high-speed data selection board, where the high-speed data selection board includes an FPGA module, peripheral electronic device equipment, and a PCB board, and the peripheral electronic device equipment includes an SFP optical module, an EEPROM memory, and an RS232 interface, where the SFP optical module is used to convert an optical signal input by an optical fiber into an electrical signal and input the electrical signal to the FPGA module; the EEPROM memory is used for pre-storing data selection information; the FPGA module is used for reading the data selection information prestored in the EEPROM after receiving the SFP optical module input data, and performing data decoding and selection processing; the RS232 interface is used for outputting the data result selected by the FPGA module to the PC end.
The peripheral electronic device apparatus of the high-speed data selection board in this embodiment further includes a power interface, a power chip, a clock chip, and a resistor-capacitor.
The high-speed data selection board card in the embodiment is used for completing collection of optical signals, information interaction with peripheral equipment, power supply of an FPGA module, clock input and IO communication in various forms.
The PCB of the high-speed data selection board card in the embodiment is used for providing carriers for the FPGA module and peripheral electronic devices, and providing an SFP optical module base and an RS232 interface.
As shown in fig. 2, the FPGA module in this embodiment includes,
the data reading module is used for judging the type of an input signal and selectively reading preset data selection information stored in the EEPROM according to the corresponding data type;
the condition setting module is used for receiving the data selection information transmitted by the data reading module and setting data selection conditions;
the data selection module is used for receiving the data selection conditions set by the condition setting module, decoding and data selection processing the data information number input into the FIFO module, and comparing and selecting the data required by the user;
the input FIFO module is used for sequentially storing the input data streams;
the output FIFO module is used for receiving and storing the data selection result sent by the data selection module;
and the UART sending module is used for sequentially sending the data selection results stored in the output FIFO module to the PC end.
The working process of the system is specifically as follows:
(1) The data input optical fiber is connected to the SFP optical module, the RS232 data output end of the high-speed data selection board card is connected to the CH340 interface of the PC end, and data is waited to be received;
(2) Powering on the development board, programming a bit stream file to the FPGA module through the JTAG interface, and immediately starting normal operation of the high-speed data selection system;
(3) The SFP optical module converts the high-speed optical signals transmitted by the optical fibers into electric signals and transmits the electric signals to the FPGA module;
(4) After receiving the data, the FPGA module judges the data type, reads preset data selection information from the EEPROM, sets reasonable data selection conditions and further starts data screening and processing;
(5) And transmitting the data meeting the selection condition to the PC end through the RS232 interface and the USB data line.
Example 2:
as shown in fig. 1, the present embodiment provides a high-speed data selection method based on FPGA, which specifically includes the following steps:
s1, a user inserts an input optical fiber interface into a high-speed data selection board card, and connects an RS232 interface with a PC end by using an RS232-CH340 data line;
s2, turning on a power switch of the high-speed data selection board card, installing Vivado software on a computer system to be tested, and programming a bit file of the FPGA data selection project to a board card FPGA module through a JTAG data line;
s3, starting the upper computer running software installed on the PC end, checking the selection result of the high-speed data selection on the optical fiber input signals through a visual interface, and storing the data or applying the data in the next step according to the requirement by a user.
As shown in fig. 2, in step S3 in this embodiment, the user saves the data as required or applies the data to the next step as required specifically as follows:
s301, data are converted by an SFP optical module and then input to an FPGA module, and input FIFO is used for storing input data streams;
s302, the data reading module selects and reads preset data selection information stored in the EEPROM according to the type of the input signal;
s303, setting data selection conditions by a condition setting module;
s304, after receiving the selection condition, the data selection module decodes the data signal input into the FIFO module, selects the needed data and sends the needed data to the output FIFO;
s305, the UART sending module sends and outputs the data selection result stored by the FIFO module to the PC end.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (5)

1. The high-speed data selection system based on the FPGA is characterized by comprising a high-speed data selection board card, wherein the high-speed data selection board card comprises an FPGA module, peripheral electronic device equipment and a PCB (printed circuit board), the peripheral electronic device equipment comprises an SFP (small form-factor pluggable) optical module, an EEPROM (electrically erasable programmable read-Only memory) and an RS232 interface, and the SFP optical module is used for converting optical signals input by optical fibers into electric signals and inputting the electric signals into the FPGA module; the EEPROM memory is used for pre-storing data selection information; the FPGA module is used for reading the data selection information prestored in the EEPROM after receiving the SFP optical module input data, and performing data decoding and selection processing; the RS232 interface is used for outputting the selection data result of the FPGA module to the PC end;
the FPGA module comprises a plurality of modules,
the data reading module is used for judging the type of an input signal and selectively reading preset data selection information stored in the EEPROM according to the corresponding data type;
the condition setting module is used for receiving the data selection information transmitted by the data reading module and setting data selection conditions;
the data selection module is used for receiving the data selection conditions set by the condition setting module, decoding and data selection processing the data information number input into the FIFO module, and comparing and selecting the data required by the user;
the input FIFO module is used for sequentially storing the input data streams;
the output FIFO module is used for receiving and storing the data selection result sent by the data selection module;
the UART sending module is used for sequentially sending the data selection results stored by the output FIFO module to the PC end;
the working process of the system is specifically as follows:
(1) The data input optical fiber is connected to the SFP optical module, the RS232 data output end of the high-speed data selection board card is connected to the CH340 interface of the PC end, and data is waited to be received;
(2) Powering on the development board, programming a bit stream file to the FPGA module through the JTAG interface, and immediately starting normal operation of the high-speed data selection system;
(3) The SFP optical module converts the high-speed optical signals transmitted by the optical fibers into electric signals and transmits the electric signals to the FPGA module;
(4) After receiving the data, the FPGA module judges the data type, reads preset data selection information from the EEPROM, sets reasonable data selection conditions and further starts data screening and processing;
(5) And transmitting the data meeting the selection condition to the PC end through the RS232 interface and the USB data line.
2. The FPGA-based high-speed data selection system of claim 1, wherein the peripheral electronics of the high-speed data selection board further comprises a power interface, a power chip, a clock chip, and a resistor-capacitor.
3. The FPGA-based high-speed data selection system of claim 1, wherein the high-speed data selection board card is used for completing collection of optical signals, information interaction with peripheral devices, power supply of an FPGA module, clock input and various forms of IO communication.
4. The FPGA-based high-speed data selection system of claim 1, wherein the PCB board of the high-speed data selection board is configured to provide a carrier for the FPGA module and peripheral electronics, and provide an SFP optical module base and an RS232 interface.
5. The high-speed data selection method based on the FPGA is characterized by comprising the following specific steps of:
s1, a user inserts an input optical fiber interface into a high-speed data selection board card, and connects an RS232 interface with a PC end by using an RS232-CH340 data line;
s2, turning on a power switch of the high-speed data selection board card, installing Vivado software on a computer system to be tested, and programming a bit file of the FPGA data selection project to a board card FPGA module through a JTAG data line;
s3, starting the upper computer running software installed on the PC end, checking the selection result of the high-speed data selection on the optical fiber input signals through a visual interface, and storing the data or applying the data to the next step according to the needs by a user; the method comprises the following steps:
s301, data are converted by an SFP optical module and then input to an FPGA module, and input FIFO is used for storing input data streams;
s302, the data reading module selects and reads preset data selection information stored in the EEPROM according to the type of the input signal;
s303, setting data selection conditions by a condition setting module;
s304, after receiving the selection condition, the data selection module decodes the data signal input into the FIFO module, selects the needed data and sends the needed data to the output FIFO;
s305, the UART sending module sends and outputs the data selection result stored by the FIFO module to the PC end.
CN202210402012.1A 2022-04-18 2022-04-18 High-speed data selection system and method based on FPGA Active CN114706800B (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108415870A (en) * 2018-05-10 2018-08-17 安徽雷索信息科技有限公司 A kind of multi-channel high-speed data diostribution device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108415870A (en) * 2018-05-10 2018-08-17 安徽雷索信息科技有限公司 A kind of multi-channel high-speed data diostribution device

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