CN114697168A - Hundred mega Ethernet digital baseband signal processing method and signal processing module - Google Patents

Hundred mega Ethernet digital baseband signal processing method and signal processing module Download PDF

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CN114697168A
CN114697168A CN202210612372.4A CN202210612372A CN114697168A CN 114697168 A CN114697168 A CN 114697168A CN 202210612372 A CN202210612372 A CN 202210612372A CN 114697168 A CN114697168 A CN 114697168A
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agc
dfe
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CN114697168B (en
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刘德良
欧阳翔
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Nanjing Qinheng Microelectronics Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H04L25/0307—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure using blind adaptation

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Abstract

The invention discloses a method for processing a hundred-mega Ethernet digital baseband signal and a signal processing module, comprising the following steps: presetting a first iteration time threshold and a second iteration time threshold; carrying out amplitude adjustment and ADC sampling on the channel signal; performing DFE self-adaptive equalization on the sampled signal, and starting DFE self-adaptive equalization only and not starting CDR phase tracking when the iteration number of the self-adaptive equalization does not reach a first iteration number threshold; when the iteration number of the self-adaptive equalization reaches a first iteration number threshold value, the DFE self-adaptive equalization is continued, and CDR phase tracking is started; in the DFE adaptive equalization process, different methods are selected to adjust the coefficients of the feedforward filter and the post-feedforward filter in the DFE according to the iteration number. The invention can solve the problem of hundred mega Ethernet ISI, has high convergence rate, high precision and stable system, and can not influence each other among modules.

Description

Hundred mega Ethernet digital baseband signal processing method and signal processing module
Technical Field
The invention relates to the technical field of hundred-mega Ethernet communication, in particular to a hundred-mega Ethernet digital baseband signal processing method and a signal processing module.
Background
The 100Base-Tx adopts a baud rate of 125M to transmit a 100Mbps signal, and a receiving end needs to recover a channel signal and restore the signal to an original signal. In the twisted pair transmission channel adopted by 100Base-Tx, the signal has more serious high-frequency attenuation, which causes more serious intersymbol interference (ISI) problem, so that the adaptive equalization needs to be completed at this stage.
In the Ethernet, a Decision Feedback Equalization (DFE) algorithm is generally adopted to eliminate the influence of ISI, but in 100Base-Tx, a MLT-3 three-level transmission mode is adopted, and if the processing is not good, the DFE algorithm is easy to generate a phenomenon of non-convergence, so that the normal transmission of signals is influenced.
Disclosure of Invention
The purpose of the invention is as follows: in order to solve the problems that in the prior art, the balance is not easy to converge in the process of hundred-mega Ethernet communication and the inter-code crosstalk cannot be solved, the invention provides a hundred-mega Ethernet digital baseband signal processing method and a signal processing module.
The technical scheme is as follows: a hundred mega Ethernet digital baseband signal processing method comprises the following steps:
presetting a first iteration time threshold and a second iteration time threshold;
receiving a channel signal, and carrying out amplitude adjustment and ADC (analog to digital converter) sampling on the channel signal;
carrying out DFE self-adaptive equalization on the sampled signal, and only starting the DFE self-adaptive equalization and not starting CDR phase tracking when the iteration number of the self-adaptive equalization does not reach a first iteration number threshold; when the iteration number of the self-adaptive equalization reaches a first iteration number threshold value, the DFE self-adaptive equalization is continued, and CDR phase tracking is started;
in the self-adaptive equalization process of the DFE, selecting a corresponding method according to the iteration times to adjust coefficients of a feedforward filter and a post-feedback filter in the DFE, and when the iteration times of the self-adaptive equalization are less than a second iteration time threshold, adjusting by adopting a blind equalization algorithm suitable for MLT-3; and when the iteration number of the self-adaptive equalization reaches a second iteration number threshold value, adjusting by adopting a coefficient-variable equalization algorithm.
Further, the blind equalization algorithm applicable to MLT-3 specifically includes:
setting the coefficients of a feedforward filter to
Figure 600643DEST_PATH_IMAGE001
The coefficients of the postamble filter are
Figure 704734DEST_PATH_IMAGE002
WhereinL 0AndL 1respectively representing the order of the feedforward and feedback filters, by setting the signal entering the decision device to
Figure 484472DEST_PATH_IMAGE003
The output signal of the decision device is
Figure 817364DEST_PATH_IMAGE004
，
Defining intermediate parameters
Figure 818687DEST_PATH_IMAGE005
，
Figure 578833DEST_PATH_IMAGE006
；
Figure 35746DEST_PATH_IMAGE007
；
The coefficients of the feedforward filter are adjusted to:
Figure 234646DEST_PATH_IMAGE008
；
the coefficients of the post-feedback filter are adjusted as follows:
Figure 841208DEST_PATH_IMAGE009
；
wherein the content of the first and second substances,
Figure 21523DEST_PATH_IMAGE010
is an adjustment step size of a blind equalization algorithm suitable for MLT-3;
Figure 775852DEST_PATH_IMAGE011
is relative to
Figure 450547DEST_PATH_IMAGE012
HysteresislThe signal of one sampling interval is sampled,
Figure 973932DEST_PATH_IMAGE012
an input signal for adaptive equalization of a DFE.
Further, the variable coefficient equalization algorithm specifically includes:
setting the coefficients of a feedforward filter to
Figure 590727DEST_PATH_IMAGE013
The coefficients of the postamble filter are
Figure 832353DEST_PATH_IMAGE014
WhereinL 0AndL 1respectively representing the order of the feedforward and feedback filters, by setting the signal entering the decision device to
Figure 45159DEST_PATH_IMAGE015
The output signal of the decision device is
Figure 688630DEST_PATH_IMAGE004
The decision error is
Figure 210747DEST_PATH_IMAGE016
；
The coefficients of the feedforward filter are adjusted to:
Figure 939669DEST_PATH_IMAGE017
；
the coefficients of the post-chopper filter are adjusted as follows:
Figure 956167DEST_PATH_IMAGE018
;
wherein the content of the first and second substances,
Figure 644024DEST_PATH_IMAGE019
the adjustment step length of the equalization algorithm is variable coefficient;
Figure 415671DEST_PATH_IMAGE020
is relative to
Figure 366310DEST_PATH_IMAGE021
HysteresislThe signal of one sampling interval is sampled,
Figure 186498DEST_PATH_IMAGE012
an input signal for adaptive equalization of a DFE.
Further, in the coefficient-varying equalization algorithm, a third iteration time threshold is preset, and when the adaptive iteration time does not reach the third iteration time thresholdWhen the value is equal to the preset value,
Figure 538982DEST_PATH_IMAGE022
(ii) a When the number of adaptive iterations reaches the third iteration number threshold,
Figure 668481DEST_PATH_IMAGE023
(ii) a Wherein the content of the first and second substances,
Figure 106416DEST_PATH_IMAGE024
。
further, amplitude adjustment and ADC sampling are performed on the channel signal, which specifically includes:
detecting whether a channel signal is received or not, amplifying the received channel signal through a programmable gain amplifier, then carrying out ADC (analog to digital converter) sampling on the signal with the adjusted amplitude, and respectively inputting the obtained sampling signal into an analog AGC (automatic gain control) and a digital AGC (automatic gain control), wherein the analog AGC adopts a peak AGC algorithm to adjust the gain of the programmable gain amplifier to ensure that the ADC output is effective; the digital AGC adjusts the amplitude of the sampling signal by adopting a successive approximation method to enable the average amplitude to be close to a preset threshold value.
Further, the detection of the channel signal adopts a moving average method, specifically:
let the sampling signal output by ADC sampling with 125MHz clock frequency be
Figure 464716DEST_PATH_IMAGE026
The corresponding absolute magnitude value is expressed as
Figure 937285DEST_PATH_IMAGE028
Then the output of the sliding filter can be expressed as:
Figure 237686DEST_PATH_IMAGE029
wherein
Figure 162916DEST_PATH_IMAGE030
Is a moving average factor when
Figure 324907DEST_PATH_IMAGE031
Time-pieceIt is assumed that the signal is received at the receiving end,Th 0is the signal detection threshold.
Further, the peak AGC algorithm specifically includes:
(a1) preset step length regulating thresholdq 0Andq 1，
Figure 386404DEST_PATH_IMAGE032
presetting two gain adjustment step lengths
Figure 857706DEST_PATH_IMAGE033
，
Figure 270232DEST_PATH_IMAGE034
(ii) a Gain to programmable gain amplifier
Figure 235914DEST_PATH_IMAGE035
Adjusting the value
Figure 417497DEST_PATH_IMAGE036
The initial setting is carried out and,
Figure 785332DEST_PATH_IMAGE037
number of iterationsi=0；
(a2) Setting the actual gain of the programmable gain amplifier to
Figure 685154DEST_PATH_IMAGE038
Waiting for the validation;
(a3) storing the sampling points output by the ADC to the window W while exceeding the amplitudeTh 0Counting the number of sampling points stored in the window W toM 0When it exceedsTh 0Total number of sampling points ofC i ；
（a4）
Figure 188948DEST_PATH_IMAGE039
；
Figure 490617DEST_PATH_IMAGE040
；
Figure 38141DEST_PATH_IMAGE041
;
(a5) Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows:
Figure 425260DEST_PATH_IMAGE042
in the gain adjustment range of the programmable gain amplifier
Figure 795062DEST_PATH_IMAGE043
Inner and
Figure 623341DEST_PATH_IMAGE044
if the circulation condition is satisfied, then
Figure 108811DEST_PATH_IMAGE045
Continuously and iteratively executing the steps (a 2) - (a 5); if the loop condition is not satisfied, the analog AGC adjustment is finished.
Further, the method for the digital AGC to adopt successive approximation specifically includes:
(b1) let the absolute amplitude of the digital AGC output signal bev n (ii) a The preset gain adjustment step length is
Figure 655330DEST_PATH_IMAGE046
，
Figure 15773DEST_PATH_IMAGE047
Presetting AGC output signal threshold asTh 1(ii) a Gain to programmable gain amplifierg ini Adjusting the value
Figure 964137DEST_PATH_IMAGE048
The initial setting is carried out and,
Figure 932093DEST_PATH_IMAGE049
number of iterationsi=0；
(b2) Setting the actual gain of the programmable gain amplifier to
Figure 218106DEST_PATH_IMAGE050
Waiting for the validation;
(b3) calculating an average amplitude value of a signal
Figure 929710DEST_PATH_IMAGE051
，M 1The number of samples used to calculate the average signal amplitude value;
（b4）
Figure 732581DEST_PATH_IMAGE052
;
Figure 58389DEST_PATH_IMAGE053
;
（b5）
Figure 641817DEST_PATH_IMAGE054
(ii) a Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows:
Figure 829216DEST_PATH_IMAGE055
if the circulation condition is satisfied, then
Figure 1440DEST_PATH_IMAGE056
Continuously and iteratively executing the steps (b 2) - (b 5); if the loop condition is not satisfied, the digital AGC adjustment is finished.
A hundred mega Ethernet digital baseband signal processing module adopts the method, and comprises a sampling amplifying unit, a decision feedback equalizing unit and a CDR phase tracking unit; the input end of the sampling amplification unit inputs a channel signal, and the output end of the sampling amplification unit is connected with the input end of the decision feedback equalization unit; the output end of the decision feedback equalization unit outputs the processed signal and is connected with the input end of the CDR phase tracking unit; the output end of the CDR phase tracking unit is connected with the sampling amplification unit.
Furthermore, the sampling amplifying unit comprises a programmable gain amplifier, an ADC sampling conversion unit, an analog AGC unit and a digital AGC unit; the input end of the programmable gain amplifier is connected with a channel signal, the output end of the programmable gain amplifier is connected with the ADC sampling conversion unit, the output end of the ADC sampling conversion unit is connected with the digital AGC unit and the analog AGC unit, the output end of the analog AGC unit is connected with the programmable gain amplifier, and the output end of the digital AGC unit is connected with the decision feedback equalization unit.
Compared with the prior art, the invention provides a hundred-mega Ethernet digital baseband signal processing method and a signal processing module, which have the following beneficial effects:
(1) the DFE part adopts a staged equalization algorithm, a blind equalization algorithm adaptive to MLT-3 is adopted for cold start when equalization is started, equalization errors are pulled to a reasonable interval, and then optimized equalization convergence performance is obtained by adopting a conventional equalization algorithm with variable coefficients, so that the whole adaptive equalization process can be converged more steadily, better precision can be achieved, and the problem of instability can be avoided.
(2) The two aspects of the self-adaptive equalization and the clock timing recovery are coordinated, and the start of the CDR is set to be delayed compared with the DFE properly, so that the mutual influence between the DFE and the CDR is reduced to the minimum, and the signal recovery effect is improved.
(3) The input signal to the DFE is adjusted to a suitable amplitude level using a dual AGC approach combining analog and digital AGC. Analog AGC is targeted for AGC convergence at a proportion where the peak value of the ADC output signal does not exceed the maximum value of the ADC, so that as many significant bits of the ADC output are possible while accommodating baseline wander (BLW) issues for 100Base-Tx signals. The digital AGC takes the average value of the signal amplitude as an AGC convergence target, and provides guarantee for convergence of a subsequent DFE algorithm through a steady successive approximation type AGC method on the premise of guaranteeing the convergence speed, so that the DFE cannot have the problem of non-convergence in the coefficient self-adaptive adjustment process. Therefore, the signal sampling and amplifying process can provide guarantee for the convergence of a subsequent DFE algorithm on the premise of guaranteeing the convergence speed, and further avoid the problem that the DFE is not converged in the coefficient self-adaptive adjustment process.
(4) The baud rate processing mode is adopted to carry out baseband processing of a digital domain on the signal, namely when ADC (analog to digital converter) sampling is carried out on the received analog signal, the frequency of a sampling clock is 125MHz, and low-power-consumption signal processing can be realized.
Drawings
Fig. 1 is a schematic structural diagram of a hundred mega ethernet digital baseband signal processing module;
FIG. 2 is a schematic diagram of a CDR phase tracking unit;
FIG. 3 illustrates a convergence process of equalization errors in an actual measurement experiment;
FIG. 4 is a timing offset accumulation process in an actual measurement experiment;
fig. 5 is an indication of clock phase adjustment in the actual measurement experiment.
Detailed Description
The invention is further explained below with reference to the figures and the specific embodiments.
A hundred mega ethernet digital baseband signal processing module, as shown in fig. 1, includes a sampling amplifying unit, a decision feedback equalizing unit (DFE) and a CDR phase tracking unit; the input end of the sampling amplification unit inputs a channel signal, and the output end of the sampling amplification unit is connected with the input end of the decision feedback equalization unit; the output end of the decision feedback equalization unit outputs the processed signal and is connected with the input end of the CDR phase tracking unit; the output end of the CDR phase tracking unit is connected with the sampling amplification unit.
The sampling amplification unit comprises a Programmable Gain Amplifier (PGA), an ADC sampling conversion unit, an analog AGC unit and a digital AGC unit; the input end of the programmable gain amplifier is connected with the channel signal, the output end of the programmable gain amplifier is connected with the ADC sampling conversion unit, the output end of the ADC sampling conversion unit is connected with the digital AGC unit (AGC 0) and the analog AGC unit (AGC 1), the output end of the analog AGC unit is connected with the programmable gain amplifier, and the output end of the digital AGC unit is connected with the decision feedback equalization unit.
The decision feedback equalization unit comprises a feedforward filter (FFF), a post-feedback filter (FBF) and a decision device. The CDR phase tracking unit is used for providing a recovery phase for the ADC sampling conversion unit.
The hundred-mega Ethernet digital baseband signal processing module is realized by adopting the following hundred-mega Ethernet digital baseband signal processing method, and comprises the following steps:
firstly, a first iteration time threshold and a second iteration time threshold are preset.
Receiving channel signals, and carrying out amplitude adjustment and ADC (analog to digital converter) sampling on the channel signals, wherein the method specifically comprises the following steps:
whether the channel signal is received or not is detected, and AGC can be started after the channel signal is accurately detected. Amplifying the received channel signal by a programmable gain amplifier, then carrying out ADC sampling on the signal with the adjusted amplitude, and respectively inputting the obtained sampling signal into an analog AGC and a digital AGC, wherein the analog AGC adopts a peak AGC algorithm to adjust the gain of the programmable gain amplifier to ensure that the ADC outputs effective digits as much as possible under the condition of ensuring that the ADC input signal does not overflow; after the gain of the PGA is adjusted in place through the analog AGC, the digital domain gain is adjusted through the AGC1, and because the system adopts a continuous signal transmission mode and always transmits an idle signal before both sides formally confirm, the digital AGC adopts a successive approximation method to adjust the amplitude of a sampling signal, so that the average amplitude is close to a preset threshold value.
The detection method for detecting whether the channel signal is received is a moving average method, and specifically includes:
let the sampling signal output by ADC sampling with 125MHz clock frequency ber n The corresponding absolute magnitude value is expressed as
Figure 311198DEST_PATH_IMAGE057
Then the output of the sliding filter can be expressed as:
Figure 319606DEST_PATH_IMAGE058
wherein
Figure 373012DEST_PATH_IMAGE059
Is a moving average factor when
Figure 399743DEST_PATH_IMAGE060
At the time, it is considered that the signal is received at the receiving end,Th 0is the signal detection threshold.
1. The goal of the peaking AGC algorithm is to threshold the amplitude of the ADC output signalTh 0The method specifically comprises the following steps:
(a1) preset step length regulating thresholdq 0Andq 1，
Figure 880403DEST_PATH_IMAGE061
presetting two gain adjustment step lengths
Figure 110527DEST_PATH_IMAGE062
，
Figure 967625DEST_PATH_IMAGE063
(ii) a Gain to programmable gain amplifier
Figure 851792DEST_PATH_IMAGE064
Adjusting the value
Figure 503353DEST_PATH_IMAGE065
The initial setting is carried out and,
Figure 486352DEST_PATH_IMAGE066
number of iterationsi= 0; as the 100Base-TX adopts more than 5 types of network lines for transmission, the maximum transmission distance specified by the protocol is more than 100 meters. The signal transmission loss caused by the line is typically below 10dB,
Figure 881562DEST_PATH_IMAGE067
the setting is suitably about 10 dB. Simultaneously setting a number of stored samples toM 0The window W of (a).
(a2) Setting the actual gain of the programmable gain amplifier to
Figure 617305DEST_PATH_IMAGE068
Waiting for effective timet AGC0 I.e. the gain transformation effective time of the PGA;
(a3) storing the sampling points output by the ADC to the window W while exceeding the amplitudeTh 0Counting the sampling points, and counting the number of the sampling points stored in the window WM 0When it exceedsTh 0Total number of sampling points ofC i ；
（a4）
Figure 705347DEST_PATH_IMAGE069
；
Figure 910063DEST_PATH_IMAGE070
；
Figure 108963DEST_PATH_IMAGE071
;
(a5) Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows:
Figure 699214DEST_PATH_IMAGE072
in the gain adjustment range of the programmable gain amplifier
Figure 958157DEST_PATH_IMAGE073
Inner and
Figure 650169DEST_PATH_IMAGE074
if the circulation condition is satisfied, then
Figure 387181DEST_PATH_IMAGE075
Continuously and iteratively executing the steps (a 2) - (a 5); if the loop condition is not satisfied, the analog AGC adjustment is finished.
2. The digital AGC adopts a successive approximation method, and the aim is to ensure that the average amplitude value of the output signal of the digital AGC is closest to a thresholdTh 1The method specifically comprises the following steps:
(b1) setting the digital AGC output signal asr n ’Corresponding to an absolute amplitude ofv n (ii) a The preset gain adjustment step length is
Figure 97517DEST_PATH_IMAGE046
,
Figure 527361DEST_PATH_IMAGE076
In the first placeiThe adjustment value of the digital AGC gain is
Figure 441091DEST_PATH_IMAGE077
(ii) a Presetting AGC output signal threshold asTh 1(ii) a Gain to programmable gain amplifierg ini Adjusting the value
Figure 981793DEST_PATH_IMAGE078
The initial setting is carried out and,
Figure 625264DEST_PATH_IMAGE079
(usually even), number of iterationsi=0；
(b2) Setting the actual gain of the programmable gain amplifier to
Figure 162030DEST_PATH_IMAGE080
Waiting for effective timet AGC1I.e. the gain transformation effective time of the PGA;
(b3) calculating an average amplitude value of a signal
Figure 890951DEST_PATH_IMAGE081
，M 1The number of samples used to calculate the average signal amplitude value;
（b4）
Figure 907449DEST_PATH_IMAGE082
;
Figure 405426DEST_PATH_IMAGE083
;
（b5）
Figure 98445DEST_PATH_IMAGE084
(ii) a Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows:
Figure 314663DEST_PATH_IMAGE085
if the circulation condition is satisfied, then
Figure 134851DEST_PATH_IMAGE086
Continuously and iteratively executing the steps (b 2) - (b 5); if the loop condition is not satisfied, the digital AGC adjustment is finished.
Thirdly, after the AGC signal is adjusted to a proper amplitude level through the steps, the signal recovery stage can be entered formally.
At this stage, the tasks of both adaptive equalization and clock timing recovery need to be completed. In the twisted pair transmission channel employed in 100Base-Tx, there is more severe high frequency attenuation, which will result in more severe inter-symbol interference (ISI) problems. There is therefore a need to overcome this effect by adaptive equalization. In addition, the transceiving clocks have the problem of inconsistent frequency and phase, so the receiving end needs to acquire clock synchronization of the transceiving end through clock tracking. And as the receiving end reduces the power consumption, a clock of 125MHz is adopted for signal sampling. Therefore, the receiving end needs to use the baud rate cdr (clock and data recovery) algorithm for clock tracking.
However, since the CDR and DFE are tightly coupled. Therefore, the DFE start-up phase is not suitable for CDR start-up due to large equalization error. Thus, the CDR needs to be formally initiated after the DFE is iterated for a period of time, such as when the number of iterations reaches a first iteration threshold. When the iteration number of the self-adaptive equalization does not reach a first iteration number threshold, only starting the DFE self-adaptive equalization and not starting the CDR phase tracking; when the iteration number of the self-adaptive equalization reaches a first iteration number threshold value, the DFE self-adaptive equalization is continued, and CDR phase tracking is started;
in the self-adaptive equalization process of the DFE, selecting a corresponding method according to the iteration times to adjust coefficients of a feedforward filter and a post-feedforward filter in the DFE, and when the iteration times of the self-adaptive equalization is less than a second iteration time threshold, adjusting by adopting a blind equalization algorithm suitable for MLT-3; and when the iteration number of the self-adaptive equalization reaches a second iteration number threshold value, adjusting by adopting a coefficient-variable equalization algorithm.
Let the coefficients of the feedforward filter in the DFE be
Figure 487335DEST_PATH_IMAGE087
The coefficients of the postamble filter are
Figure 616834DEST_PATH_IMAGE088
WhereinL 0AndL 1representing the order of the feedforward and feedback filters, respectively.
The FFF filtered signal is
Figure 54768DEST_PATH_IMAGE089
The FBF-filtered signal is
Figure 413069DEST_PATH_IMAGE090
The signal entering the decision device is
Figure 885638DEST_PATH_IMAGE091
With a decision output of
Figure 920459DEST_PATH_IMAGE092
The decision error is
Figure 845690DEST_PATH_IMAGE093
。
In order to enable robust convergence of the DFE adaptive equalization algorithm, two equalization algorithms are employed as follows:
1. the blind equalization algorithm suitable for the MLT-3 specifically includes:
defining intermediate parameters
Figure 7681DEST_PATH_IMAGE094
，
Figure 334757DEST_PATH_IMAGE095
；
Figure 619108DEST_PATH_IMAGE096
；
The coefficients of the feedforward filter are adjusted to:
Figure 221515DEST_PATH_IMAGE097
；
the coefficients of the post-chopper filter are adjusted as follows:
Figure 921618DEST_PATH_IMAGE098
；
wherein the content of the first and second substances,
Figure 103200DEST_PATH_IMAGE099
is an adjustment step size of a blind equalization algorithm suitable for MLT-3;
Figure 558452DEST_PATH_IMAGE100
is relative to
Figure 645226DEST_PATH_IMAGE101
HysteresislThe signal of the sampling interval is sampled,
Figure 211337DEST_PATH_IMAGE101
the input signal is adaptively equalized for the DFE.
2. The equalization algorithm of the variable coefficient specifically comprises:
the coefficients of the feedforward filter are adjusted to:
Figure 185109DEST_PATH_IMAGE102
；
the coefficients of the post-chopper filter are adjusted as follows:
Figure 811262DEST_PATH_IMAGE103
；
wherein the content of the first and second substances,
Figure 385332DEST_PATH_IMAGE104
the adjustment step length of the equalization algorithm is variable coefficient; is composed of
Figure 489554DEST_PATH_IMAGE105
Is relative to
Figure 583412DEST_PATH_IMAGE106
HysteresislThe signal of one sampling interval is sampled,
Figure 380467DEST_PATH_IMAGE106
adaptively equalizing the input signal for the DFE.
In the variable coefficient equalization algorithm, a third iteration time threshold value can be preset, when the self-adaptive iteration time does not reach the third iteration time threshold value,
Figure 176253DEST_PATH_IMAGE107
(ii) a When the number of adaptive iterations reaches the third iteration number threshold,
Figure 349746DEST_PATH_IMAGE108
(ii) a Wherein the content of the first and second substances,
Figure 298110DEST_PATH_IMAGE109
. So that the equalization error can converge to a smaller position.
Of course, the performance of the DFE algorithm is affected by the CDR algorithm, which are tightly coupled. If the CDR cannot adjust the phase of the clock in place instantaneously, the DFE is also very prone to divergence, resulting in failure of signal recovery. Here, a CDR algorithm based on phase interpolation is used, each clock cycle is divided into P phases, and each symbol period clock generation module advances or retreats by one clock phase according to the indication signal provided by the CDR module. The CDR module consists of phase detection, loop filtering, and offset accumulation, as shown in fig. 2. The phase detection part adopts the following baud rate phase detection algorithm:
Figure 266066DEST_PATH_IMAGE110
the phase-discriminated output error signal will enter the following loop filter:
Figure 552079DEST_PATH_IMAGE111
whereinK p In order to detect the gain of the phase,
Figure 998103DEST_PATH_IMAGE112
a very small value is usually taken for one of the parameters of the loop filter. By adjusting the two parameters, different frequency offset tracking capabilities can be obtained.
Output of loop filter
Figure 66554DEST_PATH_IMAGE113
Will enter an offset accumulation section, the output of which
Figure 205411DEST_PATH_IMAGE114
. When the temperature is higher than the set temperature
Figure 975790DEST_PATH_IMAGE115
When the clock is in the forward phase, the CDR module inputs +1 to indicate the clock to adjust a phase forward; when in use
Figure 225505DEST_PATH_IMAGE117
The CDR block inputs-1, indicating that the clock is adjusted one phase backwards.
In the CDR phase tracking process, phase discrimination and loop filtering are reasonably designed, and the clock synchronization of transmitting and receiving double-transmission is realized by adjusting the phase of the multi-phase clock.
Fig. 3 to 5 show experimentally measured equalization error convergence process (fig. 3), timing offset accumulation process (fig. 4) and clock phase adjustment indication (fig. 5) for a network line length of 150 m. In this experiment, the parameters of the DFE section were set as follows:
Figure 148462DEST_PATH_IMAGE118
. The parameters of the CDR portion are set as follows: number of clock phases
Figure 458221DEST_PATH_IMAGE119
. The actual measurement result shows that the stable transmission of the Ethernet signals can be realized under the condition that the length of the network cable reaches 150 meters.

Claims (10)

1. A hundred mega Ethernet digital baseband signal processing method is characterized by comprising the following steps:
presetting a first iteration time threshold and a second iteration time threshold;
receiving a channel signal, and carrying out amplitude adjustment and ADC (analog to digital converter) sampling on the channel signal;
carrying out DFE self-adaptive equalization on the sampled signal, and only starting the DFE self-adaptive equalization and not starting CDR phase tracking when the iteration number of the self-adaptive equalization does not reach a first iteration number threshold; when the iteration number of the self-adaptive equalization reaches a first iteration number threshold value, the DFE self-adaptive equalization is continued, and CDR phase tracking is started;
in the self-adaptive equalization process of the DFE, selecting a corresponding method according to the iteration times to adjust coefficients of a feedforward filter and a post-feedback filter in the DFE, and when the iteration times of the self-adaptive equalization are less than a second iteration time threshold, adjusting by adopting a blind equalization algorithm suitable for MLT-3; and when the iteration number of the self-adaptive equalization reaches a second iteration number threshold value, adjusting by adopting a coefficient-variable equalization algorithm.
2. The method for processing the digital baseband signal of the hundred mega ethernet according to claim 1, wherein the blind equalization algorithm applied to the MLT-3 specifically comprises:
setting the coefficients of the feedforward filter to
Figure 299275DEST_PATH_IMAGE001
The coefficients of the postamble filter are
Figure 512082DEST_PATH_IMAGE002
WhereinL 0AndL 1respectively representing the order of the feedforward and feedback filters, by setting the signal entering the decision device to
Figure 827657DEST_PATH_IMAGE003
The output signal of the decision device is
Figure 100506DEST_PATH_IMAGE004
，
Defining intermediate parameters
Figure 501532DEST_PATH_IMAGE005
，
Figure 377084DEST_PATH_IMAGE006
；
Figure 561814DEST_PATH_IMAGE007
；
The coefficients of the feedforward filter are adjusted to:
Figure 739985DEST_PATH_IMAGE008
；
the coefficients of the post-chopper filter are adjusted as follows:
Figure 487361DEST_PATH_IMAGE009
；
wherein the content of the first and second substances,
Figure 41971DEST_PATH_IMAGE010
is an adjustment step size of a blind equalization algorithm applicable to MLT-3;
Figure 66559DEST_PATH_IMAGE011
is relative to
Figure 681211DEST_PATH_IMAGE012
HysteresislThe signal of one sampling interval is sampled,
Figure 915883DEST_PATH_IMAGE012
an input signal is adaptively equalized for a DFE.
3. The method according to claim 1 or 2, wherein the variable coefficient equalization algorithm specifically comprises:
setting the coefficients of a feedforward filter to
Figure 756407DEST_PATH_IMAGE013
The coefficients of the postamble filter are
Figure 245288DEST_PATH_IMAGE014
WhereinL 0AndL 1respectively representing the order of the feedforward and feedback filters, and setting the signal entering the decision device as
Figure 499683DEST_PATH_IMAGE015
The output signal of the decision device is
Figure 97017DEST_PATH_IMAGE016
The decision error is
Figure 118063DEST_PATH_IMAGE017
；
The coefficients of the feedforward filter are adjusted to:
Figure 120173DEST_PATH_IMAGE018
；
the coefficients of the post-chopper filter are adjusted as follows:
Figure 76627DEST_PATH_IMAGE019
；
wherein, the first and the second end of the pipe are connected with each other,
Figure 161258DEST_PATH_IMAGE020
for equalising of variable coefficientsAdjusting step length of the algorithm;
Figure 454836DEST_PATH_IMAGE021
is relative to
Figure 308523DEST_PATH_IMAGE022
HysteresislThe signal of one sampling interval is sampled,
Figure 294933DEST_PATH_IMAGE022
an input signal is adaptively equalized for a DFE.
4. The method of claim 3, wherein a third threshold of iteration times is preset in the variable coefficient equalization algorithm, and when the adaptive iteration times does not reach the third threshold of iteration times,
Figure 866860DEST_PATH_IMAGE023
(ii) a When the number of adaptive iterations reaches the third iteration number threshold,
Figure 839495DEST_PATH_IMAGE024
(ii) a Wherein the content of the first and second substances,
Figure 406743DEST_PATH_IMAGE025
。
5. the method for processing the hundred mega ethernet digital baseband signal according to claim 1 or 2, wherein the amplitude adjustment and ADC sampling are performed on the channel signal, which specifically includes:
detecting whether a channel signal is received or not, amplifying the received channel signal through a programmable gain amplifier, then carrying out ADC (analog to digital converter) sampling on the signal with the adjusted amplitude, and respectively inputting the obtained sampling signal into an analog AGC (automatic gain control) and a digital AGC (automatic gain control), wherein the analog AGC adopts a peak AGC algorithm to adjust the gain of the programmable gain amplifier to ensure that the ADC output is effective; the digital AGC adjusts the amplitude of the sampling signal by adopting a successive approximation method to enable the average amplitude to be close to a preset threshold value.
6. The method for processing the digital baseband signal of the hundred mega ethernet according to claim 5, wherein the detection of the channel signal adopts a moving average method, which specifically comprises:
let the sampling signal output by ADC sampling with 125MHz clock frequency be
Figure 705000DEST_PATH_IMAGE027
The corresponding absolute magnitude value is expressed as
Figure 623277DEST_PATH_IMAGE029
Then the output of the sliding filter can be expressed as:
Figure 399604DEST_PATH_IMAGE030
；
wherein
Figure 959373DEST_PATH_IMAGE031
Is a moving average factor when
Figure 553166DEST_PATH_IMAGE032
At time, it is considered that the signal is received at the receiving end,Th 0is the signal detection threshold.
7. The method according to claim 6, wherein the peak AGC algorithm specifically comprises:
(a1) preset step length regulating thresholdq 0Andq 1，
Figure 834106DEST_PATH_IMAGE033
presetting two gain adjustment step lengths
Figure 945281DEST_PATH_IMAGE034
，
Figure 893645DEST_PATH_IMAGE035
(ii) a Gain to programmable gain amplifier
Figure 533705DEST_PATH_IMAGE036
Adjusting the value
Figure 301941DEST_PATH_IMAGE037
The initial setting is carried out and,
Figure 279124DEST_PATH_IMAGE038
number of iterationsi=0；
(a2) Setting the actual gain of the programmable gain amplifier to
Figure 81995DEST_PATH_IMAGE039
Waiting for the validation;
(a3) storing the sampling points output by the ADC to the window W while exceeding the amplitudeTh 0Counting the number of sampling points stored in the window W toM 0When it exceedsTh 0Total number of sampling points ofC i ；
（a4）
Figure 752011DEST_PATH_IMAGE040
；
Figure 7543DEST_PATH_IMAGE041
；
Figure 920574DEST_PATH_IMAGE042
；
(a5) Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows:
Figure 437006DEST_PATH_IMAGE043
in the gain adjustment range of the programmable gain amplifier
Figure 418868DEST_PATH_IMAGE044
Inner and
Figure 896117DEST_PATH_IMAGE045
if the circulation condition is satisfied, then
Figure 480682DEST_PATH_IMAGE046
Continuously and iteratively executing the steps (a 2) - (a 5); if the loop condition is not satisfied, the analog AGC adjustment is finished.
8. The method for processing the digital baseband signal of the hundred mega ethernet according to claim 6, wherein the method for the digital AGC to adopt successive approximation specifically comprises:
(b1) let the absolute amplitude of the digital AGC output signal bev n (ii) a The preset gain adjustment step length is
Figure 992566DEST_PATH_IMAGE047
，
Figure 4384DEST_PATH_IMAGE048
Presetting AGC output signal threshold asTh 1(ii) a Gain to programmable gain amplifierg ini Adjusting the value
Figure 968929DEST_PATH_IMAGE049
The initial setting is carried out and,
Figure 232552DEST_PATH_IMAGE050
number of iterationsi=0；
(b2) Setting the actual gain of the programmable gain amplifier to
Figure 457997DEST_PATH_IMAGE051
Waiting for the validation;
(b3) calculating an average amplitude value of a signal
Figure 781662DEST_PATH_IMAGE052
，M 1The number of samples used to calculate the average signal amplitude value;
（b4）
Figure 358136DEST_PATH_IMAGE053
；
Figure 425450DEST_PATH_IMAGE054
；
（b5）
Figure 377838DEST_PATH_IMAGE055
(ii) a Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows:
Figure 997038DEST_PATH_IMAGE056
if the circulation condition is satisfied, then
Figure 936175DEST_PATH_IMAGE057
Continuously and iteratively executing the steps (b 2) - (b 5); if the loop condition is not satisfied, the digital AGC adjustment is finished.
9. A module for processing a digital baseband signal of a gigabit ethernet, wherein the method for processing a digital baseband signal of a gigabit ethernet according to any one of claims 1 to 8 comprises a sampling amplification unit, a decision feedback equalization unit, and a CDR phase tracking unit; the input end of the sampling amplification unit inputs a channel signal, and the output end of the sampling amplification unit is connected with the input end of the decision feedback equalization unit; the output end of the decision feedback equalization unit outputs the processed signal and is connected with the input end of the CDR phase tracking unit; the output end of the CDR phase tracking unit is connected with the sampling amplification unit.
10. The hundreds of mega ethernet digital baseband signal processing module according to claim 9, wherein the sampling amplifying unit comprises a programmable gain amplifier, an ADC sampling converting unit, an analog AGC unit, and a digital AGC unit; the input end of the programmable gain amplifier is connected with a channel signal, the output end of the programmable gain amplifier is connected with the ADC sampling conversion unit, the output end of the ADC sampling conversion unit is connected with the digital AGC unit and the analog AGC unit, the output end of the analog AGC unit is connected with the programmable gain amplifier, and the output end of the digital AGC unit is connected with the decision feedback equalization unit.
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