CN114695385A - Display panel and manufacturing method thereof - Google Patents
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- CN114695385A CN114695385A CN202210257990.1A CN202210257990A CN114695385A CN 114695385 A CN114695385 A CN 114695385A CN 202210257990 A CN202210257990 A CN 202210257990A CN 114695385 A CN114695385 A CN 114695385A
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- 229910052802 copper Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
The application provides a display panel and a manufacturing method thereof, wherein the display panel comprises: a substrate base plate and a thin film transistor; the thin film transistor includes: the active layer is arranged on the substrate base plate; the first electrode and the second electrode respectively cover partial areas of the active layer and form a gap area exposing the active layer; the insulating layer covers the first electrode, the second electrode and the gap area, and a groove is formed in the gap area; the grid electrode is accommodated in the groove. According to the display panel, the grid electrode is accommodated in the groove of the insulating layer, and the groove is located in the gap area between the first electrode and the second electrode, so that the orthographic projection of the first electrode and the orthographic projection of the second electrode on the substrate base plate are not overlapped with the orthographic projection of the grid electrode on the substrate base plate, the automatic alignment of the grid electrode with the first electrode and the second electrode is realized, the parasitic capacitance of the display panel is reduced, the influence of capacitive coupling on a drive signal of the display panel is reduced, and the display quality of the display panel is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a manufacturing method thereof.
Background
The existing mainstream Display technologies include Liquid Crystal Display (LCD) technology, Organic Light Emitting Diode (OLED) Display technology, and Micro Light Emitting Diode (Micro LED) Display technology, and whatever the Display technology, the driving element is often a Thin-Film Transistor (TFT).
In the manufacturing process of the conventional display panel, pattern alignment between films in the thin film transistor cannot be completely matched due to deformation caused by changes of temperature or stress, for example, when a gate deviates from a channel region of an active layer, the thin film transistor cannot be normally turned on or off under the control of the gate, which seriously affects the device performance. In order to avoid the above problems, it is a common practice at present to increase the area of the gate electrode to have a certain overlap amount between the gate electrode and the source and drain electrodes, and this method can avoid the device performance deterioration caused by a small alignment deviation, but the overlapping arrangement of the gate electrode and the source and drain electrodes introduces parasitic capacitance in the display panel, and the parasitic capacitance affects the driving signal of the display panel, and further affects the display quality. Therefore, how to avoid overlapping of the gate and the source and drain, thereby avoiding introducing parasitic capacitance, is a great problem to be solved by research and development personnel.
Disclosure of Invention
The application provides a display panel and a manufacturing method thereof, which can avoid overlapping of a grid electrode, a source electrode and a drain electrode, reduce parasitic capacitance of the display panel, reduce influence of capacitive coupling on a driving signal of the display panel and improve display quality of the display panel.
In order to achieve the above purpose, the display panel and the manufacturing method thereof of the present application adopt the following technical solutions.
In one aspect, the present application provides a display panel, including: the thin film transistor structure comprises a substrate base plate and a thin film transistor arranged on the substrate base plate; the thin film transistor includes: the semiconductor device comprises an active layer, a first electrode, a second electrode, an insulating layer and a grid electrode, wherein the active layer is arranged on a substrate; the first electrode and the second electrode respectively cover partial areas of the active layer and form a gap area exposing the active layer; the insulating layer covers the first electrode, the second electrode and the gap area, and a groove is formed in the gap area; the grid electrode is accommodated in the groove.
Optionally, the gate is made of a conductive photoresist, and the conductive photoresist is a liquid with leveling property in a first state and a stable solid in a second state.
Optionally, the active layer includes a channel region, a bottom of the groove covers the channel region, and the gate covers a bottom of the groove.
Optionally, the active layer further includes a first electrode region and a second electrode region located at two sides of the channel region, wherein the first electrode includes a first portion and a second portion, the first portion is disposed on the first electrode region, and the second portion is disposed on the substrate base plate; the second electrode comprises a third part and a fourth part, the third part is arranged on the second electrode area, and the fourth part is arranged on the substrate base plate.
Optionally, the thicknesses of the first portion and the third portion are both a first thickness, the thickness of the gate is a second thickness, and the second thickness is smaller than the first thickness.
Optionally, the display panel further includes scan lines and data lines arranged on the substrate in a crossing manner, wherein the scan lines are arranged in different layers with respect to each film layer in the thin film transistor and are electrically connected to the gate electrode; the data line is arranged on the same layer as the first electrode and the second electrode and is electrically connected with one of the first electrode or the second electrode.
Optionally, the display panel further includes a bridging portion located outside the gap region, and the bridging portion and the gate are disposed on the same layer and are electrically connected to the gate and the scan line, respectively.
On the other hand, the application also provides a manufacturing method of the display panel, which comprises the following steps:
forming a patterned active layer on a substrate;
forming a patterned electrode layer, wherein the electrode layer comprises a first electrode and a second electrode, the first electrode and the second electrode respectively cover partial areas of the active layer, and a gap area exposing the active layer is formed between the first electrode and the second electrode;
forming an insulating layer, wherein the insulating layer covers the first electrode, the second electrode and the gap region, and a groove is formed in the gap region;
coating a conductive photoresist with leveling property on the insulating layer, wherein after the coating is finished, at least part of the conductive photoresist above the first electrode and the second electrode flows into a region where the first electrode and the second electrode are not arranged, and the region where the first electrode and the second electrode are not arranged comprises the groove;
and exposing, developing and stripping the conductive photoresist, and converting the conductive photoresist remained in the groove into a grid electrode with a stable form.
Optionally, before exposing, developing and stripping the conductive photoresist, the method further includes the following steps: and removing the conductive photoresist remained above the first electrode and the second electrode by using a plasma ashing process.
Optionally, the method further includes the following steps after forming the gate with the stable shape: and forming a patterned metal layer, wherein the metal layer comprises a scanning line electrically connected with the grid electrode.
According to the display panel, the grid electrode is accommodated in the groove of the insulating layer, and the groove is located in the gap area between the first electrode and the second electrode, so that the orthographic projection of the first electrode and the orthographic projection of the second electrode on the substrate base plate are not overlapped with the orthographic projection of the grid electrode on the substrate base plate, the automatic alignment of the grid electrode with the first electrode and the second electrode is realized, the parasitic capacitance of the display panel is reduced, the influence of capacitive coupling on a drive signal of the display panel is reduced, and the display quality of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a TFT in a prior art display panel;
fig. 2 is a schematic cross-sectional view of a region including a thin film transistor in a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic plan view of a region including a thin film transistor in a display panel according to an embodiment of the present disclosure;
fig. 4 is a schematic view illustrating a manufacturing process of a display panel according to an embodiment of the present disclosure;
fig. 5a and 5b are a schematic cross-sectional view and a schematic plan view of a region of the display panel corresponding to the step S01, the region including the thin film transistor;
fig. 6a and 6b are a schematic cross-sectional view and a schematic plan view of the region of the display panel corresponding to step S02, wherein the region includes the thin film transistor;
fig. 7a and 7b are a schematic cross-sectional view and a schematic plan view of the region of the display panel corresponding to the step S03, wherein the region includes the thin film transistor;
fig. 8a and 8b are a schematic cross-sectional view and a schematic plan view of a region of the display panel corresponding to the step S04, the region including the thin film transistor;
fig. 9a and 9b are a schematic cross-sectional view and a schematic plan view of the region of the display panel corresponding to step S05, wherein the region includes the thin film transistor.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The following disclosure provides many different embodiments or examples for implementing different features of the application. To simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials. The following are detailed below, and it should be noted that the order of description of the following examples is not intended to limit the preferred order of the examples.
Fig. 1 is a schematic cross-sectional view of a thin film transistor in a display panel in the prior art, as shown in fig. 1, the thin film transistor includes a substrate 10 ' and a thin film transistor disposed on the substrate 10 ', the thin film transistor includes a gate 20 ', a gate insulating layer 30 ', an active layer 40 ', and a source drain layer stacked in sequence, wherein the active layer 40 ' includes a channel region 41 ', the source drain layer includes a source 51 ' and a drain 52 ', a width of the gate 20 ' is greater than a width of the channel region 41 ', a front projection of the gate 20 ' on the substrate 10 ' overlaps a front projection of the source 51 ' on the substrate 10 ', and a front projection of the gate 20 ' on the substrate 10 ' overlaps a front projection of the drain 52 ' on the substrate 10 '. In the prior art, in order to avoid that the orthographic projection of the gate 20 'on the active layer 40' in the thin film transistor cannot completely cover the channel region 41 'due to deformation caused by changes of temperature, stress and the like, in design, the width of the gate 20' is made larger than the width of the channel region 41 ', so that the orthographic projection of the gate 20' on the substrate 10 'is partially overlapped with the orthographic projections of the source 51' and the drain 52 'on the substrate 10', thereby introducing parasitic capacitance, so that a driving signal of the display panel is affected, and further, the display quality is affected.
The application provides a display panel, can avoid the overlapping problem of grid and source electrode, drain electrode, avoids introducing parasitic capacitance and causes the influence to display panel's drive signal, improves display quality.
Fig. 2 is a schematic cross-sectional view of a region including a thin film transistor in a display panel according to an embodiment of the present disclosure; fig. 3 is a schematic plan view of a region including a thin film transistor in a display panel according to an embodiment of the present disclosure. Referring to fig. 2 and 3, the present application provides a display panel, which may be any one of a liquid crystal display panel, an organic light emitting diode display panel, and a micro light emitting diode display panel. The display panel includes: a substrate base plate 10 and a thin film transistor disposed on the substrate base plate 10. The thin film transistor includes: an active layer 20, a first electrode 31, a second electrode 32, an insulating layer 40, and a gate electrode 50, wherein the active layer 20 is disposed on the base substrate 10; the first electrode 31 and the second electrode 32 respectively cover partial regions of the active layer 20, and form a gap region exposing the active layer 20; the insulating layer 40 covers the first electrode 31, the second electrode 32 and the gap region, and forms a groove 401 in the gap region; the gate 50 is received in the recess 401. According to the display panel, the grid electrode 50 is arranged in the groove 401 of the insulating layer 40, and the groove 401 is located in the gap area between the first electrode 31 and the second electrode 32, so that orthographic projections of the first electrode 31 and the second electrode 32 on the substrate base plate 10 are not overlapped with orthographic projections of the grid electrode 50 on the substrate base plate 10, automatic alignment of the grid electrode 50 and the first electrode 31 and the second electrode 32 is achieved, parasitic capacitance of the display panel is reduced, influence of capacitive coupling on a driving signal of the display panel is reduced, and display quality of the display panel is improved.
In this embodiment, the substrate 10 is a flexible substrate or a rigid substrate, and the material of the substrate 10 may be glass, plastic, polyimide, or the like.
In this embodiment, the thin film transistor may be any one of a Metal Oxide (Metal Oxide) thin film transistor, an amorphous silicon (a-Si) thin film transistor, and a Low Temperature Polysilicon (LTPS) thin film transistor. Preferably, the thin film transistor is an Indium Gallium Zinc Oxide (IGZO) thin film transistor, and the IGZO thin film transistor is one of metal Oxide thin film transistors.
In this embodiment, the active layer 20 is located on the substrate 10, and other film layers, such as a light-shielding layer and a buffer layer, may be further disposed between the active layer 20 and the substrate 10. The active layer 20 includes a channel region 23 and first and second electrode regions 21 and 22 located at both sides of the channel region 23. Preferably, the active layer 20 is made of a metal oxide semiconductor, and the first electrode region 21 and the second electrode region 22 are not subjected to a conductive process.
In this embodiment, the first electrode 31 covers a partial region of the active layer 20, that is, at least a portion of the first electrode 31 is located on the active layer 20. Specifically, the first electrode 31 includes a first portion 311 and a second portion 312, the first portion 311 and the second portion 312 are disposed adjacent to each other, the first portion 311 is disposed on the active layer 20 and covers the first electrode region 21 of the active layer 20; the second portion 312 is disposed on the substrate base plate 10 and covers the edge of the first electrode region 21.
In this embodiment, the second electrode 32 covers a partial region of the active layer 20, that is, at least a portion of the second electrode 32 is located on the active layer 20. Specifically, the second electrode 32 includes a third portion 321 and a fourth portion 322, the third portion 321 and the fourth portion 322 are disposed adjacent to each other, the third portion 321 is disposed on the active layer 20, and covers the second electrode region 22 of the active layer 20; the fourth portion 322 is disposed on the substrate base plate 10 and covers the edge of the second electrode region 22.
In this embodiment, the first electrode 31 covers the edge of the first electrode region 21, and the second electrode 32 covers the edge of the second electrode region 22, so that the channel region 23 can be protected, and the problem of performance degradation of the device caused by the fact that external ambient light irradiates the channel from the side surface is avoided.
In this embodiment, the first electrode 31 and the second electrode 32 are made of the same material, and may be made of a metal or an alloy or a metal composite film containing at least one of Cu, Al, Mo, Nb, and Ti, and the thickness of each of the first electrode 31 and the second electrode 32 is in a range of 100nm to 1000 nm. Further, the thickness of each of the first electrode 31 and the second electrode 32 is in a range of 400nm to 1000 nm.
In this embodiment, the first electrode 31 is a source electrode, the second electrode 32 is a drain electrode, the first electrode region 21 is a source region, and the second electrode region 22 is a drain region. However, in other embodiments of the present application, the first electrode 31 may also be a drain electrode, the second electrode 32 may be a source electrode, the first electrode region 21 may be a drain region, and the second electrode region 22 may be a source region.
In this embodiment, the first electrode 31 and the second electrode 32 are disposed at the same layer and at an interval, the first electrode 31 and the second electrode 32 may be formed by patterning in a film forming process, a gap region exposing the active layer 20 is formed between the first electrode 31 and the second electrode 32, and an orthographic projection of the gap region on the substrate 10 covers an orthographic projection of the channel region 23 on the substrate 10.
In this embodiment, the insulating layer 40 covers the first electrode 31, the second electrode 32 and the gap region, and a groove 401 is formed in the gap region. In the present application, the first electrode 31 and the second electrode 32 protrude from the active layer 20, so that the insulating layer 40 forms a groove 401 in the gap region, and the bottom of the groove 401 covers the channel region 23.
In this embodiment, the gate 50 is accommodated in the groove 401, so that the orthographic projection of the gate 50 on the substrate 10 is not overlapped with the orthographic projection of the first electrode 31 on the substrate 10 and the orthographic projection of the second electrode 32 on the substrate 10, thereby achieving the automatic alignment of the gate 50 with the first electrode 31 and the second electrode 32, reducing the parasitic capacitance of the display panel, reducing the influence of capacitive coupling on the driving signal of the display panel, and improving the display quality of the display panel.
In this embodiment, the gate 50 covers the bottom of the groove 401, that is, the orthographic projection of the gate 50 on the active layer 20 covers the channel region 23, so that the gate 50 and the channel region 23 can be automatically aligned, and the failure problem that the thin film transistor cannot be normally turned on or turned off due to the deviation of the gate 50 relative to the channel region 23 is avoided.
In this embodiment, the gate 50 is made of a conductive photoresist, and the conductive photoresist may be a transparent conductive photoresist or an opaque conductive photoresist. The conductive photoresist is in a liquid state with leveling property in a first state and is in a stable solid state in a second state. Specifically, the first state is a state when the conductive photoresist is not irradiated with light and/or heated, and the second state is a state after the conductive photoresist is irradiated with light and/or heated. Since the conductive photoresist is in a liquid state with leveling property when not being irradiated with light and/or heated, and the insulating layer 40 forms an uneven structure including the groove 401 by the first electrode 31 and the second electrode 32 protruding from the active layer 20, after the conductive photoresist in the first state is coated on the insulating layer 40, most of the conductive photoresist above the first electrode 31 and the second electrode 32 flows into the groove 401 or other areas where the first electrode 31 and the second electrode 32 are not disposed; after the conductive photoresist in the first state is subjected to illumination and/or heating treatment, the conductive photoresist contained in the groove 401 is converted from the first state to the second state, so that the gate 50 with a stable shape and a conductive function is formed, and the gate 50 is limited by the groove 401, so that the parasitic capacitance problem caused by overlapping of the gate 50, the first electrode 31 and the second electrode 32 in a direction perpendicular to the substrate 10 is avoided.
In this embodiment, the thicknesses of the first portion 311 and the third portion 321 are both a first thickness, the thickness of the gate 50 is a second thickness, the gate 50 is accommodated in the groove 401, and the thickness of the gate 50 is less than or equal to the depth of the groove 401, that is, the second thickness is less than or equal to the first thickness. Preferably, the thickness of the gate electrode 50 is smaller than the depth of the groove 401, and the second thickness is smaller than the first thickness, in this state, the surface of the gate electrode 50 is lower than the surfaces of the insulating layers 40 at two sides thereof, so that the risk of overlapping between the gate electrode 50 and the first and second electrodes 31 and 32 due to the conductive photoresist overflowing the groove 401 can be reduced.
In this embodiment, the display panel further includes a scan line 60 and a data line 33, which are crossed on the substrate 10, wherein the scan line 60 is disposed in a different layer from each film layer (i.e., a gate layer where an active layer, an electrode layer where a first electrode and a second electrode are located, an insulating layer, and a gate electrode are located) in the thin film transistor, and is electrically connected to the gate electrode 50; the data line 33 is disposed in the same layer as the first electrode 31 and the second electrode 32, and is electrically connected to one of the first electrode 31 or the second electrode 32.
In this embodiment, the scan line 60 is disposed on the insulating layer 40, and an orthogonal projection of the scan line 60 on the substrate 10 does not overlap an orthogonal projection of the gate 50 on the substrate 10. The display panel further comprises a bridging portion 51 located outside the gap region, wherein the bridging portion 51 and the gate 50 are arranged on the same layer and are respectively electrically connected with the gate 50 and the scanning line 60. In this embodiment, the strap 51 and the gate electrode 50 are provided in the same layer, so that the strap 51 and the gate electrode 50 can be formed in the same film formation process, but the present application does not limit the formation method of the strap 51, and in other embodiments of the present application, the strap 51 and the scan line 60 may be formed in the same film formation process.
On the other hand, the application also provides a manufacturing method of the display panel. Specifically, referring to fig. 4, 5a, 5b, 6a, 6b, 7a, 7b, 8a, 8b, 9a, and 9b, the method for manufacturing the display panel includes the following steps:
s01: forming a patterned active layer 20 on a substrate 10;
s02: forming a patterned electrode layer, wherein the electrode layer comprises a first electrode 31 and a second electrode 32, the first electrode 31 and the second electrode 32 respectively cover partial regions of the active layer, and a gap region 300 exposing the active layer 20 is formed between the first electrode 31 and the second electrode 32;
s03: forming an insulating layer 40, wherein the insulating layer 40 covers the first electrode 31, the second electrode 32 and the gap region 300, and a groove 401 is formed in the gap region 300;
s04: coating a conductive photoresist 500 with leveling property on the insulating layer 40, wherein after the coating is finished, at least part of the conductive photoresist 500 positioned above the first electrode 31 and the second electrode 32 flows into a region where the first electrode 31 and the second electrode 32 are not arranged, and the region where the first electrode 31 and the second electrode 32 are not arranged comprises the groove 401;
s05: exposing, developing and stripping the conductive photoresist 500, and converting the conductive photoresist 500 remained in the groove 401 into the gate 50 with a stable shape.
In the manufacturing method of the display panel provided by the present application, since the gate electrode 50 is made of the conductive photoresist, and the conductive photoresist is in a liquid state with leveling property when no light treatment is performed, after the liquid conductive photoresist 500 is coated on the uneven insulating layer 40, most of the conductive photoresist 500 above the first electrode 31 and the second electrode 32 spontaneously flows into the groove 401 or other areas where the first electrode 31 and the second electrode 32 are not disposed; after the conductive photoresist 500 is exposed, developed and stripped, the conductive photoresist 500 remaining in the groove 401 is converted from an original liquid state to a solid state with a stable form, so that the gate 50 which is not overlapped with the first electrode 31 and the second electrode 32 is formed in a direction perpendicular to the substrate 10, and the introduction of parasitic capacitance is avoided.
In addition, in the actual manufacturing process, the active layer 20 of the present application does not need to perform a conductor-making process, and when the position of the channel region 23 of the active layer 20 is determined, the gap region 300 between the first electrode 31 and the second electrode 32 is also relatively determined, and when the gap region 300 is determined, the position of the groove 401 of the insulating layer 40 is also determined, and the position of the corresponding gate 50 can also be determined, so that the display panel manufactured by the manufacturing method of the display panel provided by the present application can achieve not only the automatic alignment of the gate 50 with the first electrode 31 and the second electrode 32, but also the automatic alignment of the gate 50 with the channel region 23.
Further, the step S04 further includes: the conductive photoresist 500 remaining over the first electrode 31 and the second electrode 32 is removed using a plasma ashing process. Specifically, after the conductive photoresist 500 coated on the insulating layer 40 is sufficiently leveled, in order to avoid the occurrence of a small amount of conductive photoresist 500 remaining in the areas above the first electrode 31 and the second electrode 32, the present application further includes the following steps before the conductive photoresist 500 is exposed, developed, and stripped: removing the conductive photoresist remained above the first electrode 31 and the second electrode 32 by using a plasma ashing process, thereby reducing the overall thickness of the conductive photoresist 500 and making the thickness of the conductive photoresist 500 in the groove 401 smaller than the depth of the groove 401.
Further, the following step S06 is included after the gate electrode 50 with stable morphology is formed: a patterned metal layer is formed on the insulating layer 40, and the metal layer includes a scan line electrically connected to the gate electrode. The scan line may be electrically connected to the gate electrode 50 through a strap, and the strap may be formed on the same layer as the gate electrode 50 in step S05, and the strap is located outside the groove 401.
In summary, the present application provides a display panel and a method for manufacturing the same, the display panel includes: the thin film transistor structure comprises a substrate base plate and a thin film transistor arranged on the substrate base plate; the thin film transistor includes: the semiconductor device comprises an active layer, a first electrode, a second electrode, an insulating layer and a grid electrode, wherein the active layer is arranged on a substrate; the first electrode and the second electrode respectively cover partial areas of the active layer and form a gap area exposing the active layer; the insulating layer covers the first electrode, the second electrode and the gap area, and a groove is formed in the gap area; the grid electrode is accommodated in the groove. The grid electrode is accommodated in the groove of the insulating layer, and the groove is located in the gap area between the first electrode and the second electrode, so that orthographic projections of the first electrode and the second electrode on the substrate are not overlapped with orthographic projections of the grid electrode on the substrate, automatic alignment of the grid electrode and the first electrode and the second electrode is realized, parasitic capacitance of the display panel is reduced, influence of capacitive coupling on a drive signal of the display panel is reduced, and display quality of the display panel is improved.
The display panel and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principle and the implementation manner of the present application are explained by applying specific examples herein, and the description of the embodiments above is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel, comprising: the thin film transistor structure comprises a substrate base plate and a thin film transistor arranged on the substrate base plate; the thin film transistor includes: the semiconductor device comprises an active layer, a first electrode, a second electrode, an insulating layer and a grid electrode, wherein the active layer is arranged on a substrate; the first electrode and the second electrode respectively cover partial areas of the active layer and form a gap area exposing the active layer; the insulating layer covers the first electrode, the second electrode and the gap area, and a groove is formed in the gap area; the grid electrode is accommodated in the groove.
2. The display panel of claim 1, wherein the gate is made of a conductive photoresist, and the conductive photoresist is a liquid with leveling property in the first state and a stable solid in the second state.
3. The display panel according to claim 2, wherein the active layer comprises a channel region, wherein a bottom of the groove covers the channel region, and wherein the gate electrode covers the bottom of the groove.
4. The display panel of claim 3, wherein the active layer further comprises a first electrode region and a second electrode region on both sides of the channel region, wherein the first electrode comprises a first portion disposed on the first electrode region and a second portion disposed on the substrate; the second electrode comprises a third part and a fourth part, the third part is arranged on the second electrode area, and the fourth part is arranged on the substrate base plate.
5. The display panel according to claim 4, wherein the thickness of each of the first and third portions is a first thickness, and the thickness of the gate electrode is a second thickness, and the second thickness is smaller than the first thickness.
6. The display panel according to claim 1, wherein the display panel further comprises scan lines and data lines crossing each other on the substrate, wherein the scan lines are disposed in different layers from each of the thin film transistors and are electrically connected to the gate electrodes; the data line is arranged on the same layer as the first electrode and the second electrode and is electrically connected with one of the first electrode or the second electrode.
7. The display panel according to claim 6, further comprising a bridging portion located outside the gap region, wherein the bridging portion is disposed on the same layer as the gate electrode and is electrically connected to the gate electrode and the scan line, respectively.
8. A manufacturing method of a display panel is characterized by comprising the following steps:
forming a patterned active layer on a substrate;
forming a patterned electrode layer, wherein the electrode layer comprises a first electrode and a second electrode, the first electrode and the second electrode respectively cover partial areas of the active layer, and a gap area exposing the active layer is formed between the first electrode and the second electrode;
forming an insulating layer, wherein the insulating layer covers the first electrode, the second electrode and the gap region, and a groove is formed in the gap region;
coating a conductive photoresist with leveling property on the insulating layer, wherein after the coating is finished, at least part of the conductive photoresist above the first electrode and the second electrode flows into a region where the first electrode and the second electrode are not arranged, and the region where the first electrode and the second electrode are not arranged comprises the groove;
and exposing, developing and stripping the conductive photoresist, and converting the conductive photoresist remained in the groove into a grid electrode with a stable form.
9. The method for manufacturing a display panel according to claim 8, wherein the steps of exposing, developing and peeling the conductive photoresist further comprise: and removing the conductive photoresist remained above the first electrode and the second electrode by using a plasma ashing process.
10. The method for manufacturing a display panel according to claim 8, further comprising the following steps after forming the gate electrode having the stable morphology: and forming a patterned metal layer, wherein the metal layer comprises a scanning line electrically connected with the grid electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210257990.1A CN114695385A (en) | 2022-03-16 | 2022-03-16 | Display panel and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210257990.1A CN114695385A (en) | 2022-03-16 | 2022-03-16 | Display panel and manufacturing method thereof |
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| CN114695385A true CN114695385A (en) | 2022-07-01 |
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| CN202210257990.1A Pending CN114695385A (en) | 2022-03-16 | 2022-03-16 | Display panel and manufacturing method thereof |
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