CN114679242B - Polarization code for HARQ transmission - Google Patents

Abstract

Embodiments of the present disclosure relate to polarization codes for HARQ transmissions. The present disclosure provides for performing polarization encoding. Performing the polarization encoding may include selecting a length S of a shortened bit number and a length P of a punctured bit number based on the HARQ scheme, encoding a plurality of information bits to generate a base code, interleaving a result of the shortened polarization encoder module to generate a codeword including the base code minus the shortened bit number, minus the punctured bit number, plus an extended bit number of length E, and providing the codeword to the modulation module to generate a result of dividing the codeword by a multiplication of a spatial stream number and the number of bits per modulation, and providing the divided result to a channel to transmit the polarization code to the reception apparatus.

Description

Polarization code for HARQ transmission

RELATED APPLICATIONS

The present application is a divisional application of the invention patent application with international application date of 2016, 9 and 22, international application number PCT/US2016/053026, entering the chinese national stage at 2018, 9 and 10, chinese national application number 201680083369.0, and the invention name of "polarization code for HARQ transmission".

This application is U.S. provisional patent application Ser. No.62/334,772, filed 5/11/2016, and non-provisional application, U.S. provisional patent application Ser. No.62/320,094, filed 4/2016, each of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to polar code (polar code) design, including support for hybrid automatic repeat request (HARQ) transmissions. In particular, the present disclosure relates to polarization encoding and decoding for HARQ transmissions.

Drawings

Fig. 1 is a system diagram illustrating a polarization encoding chain according to one embodiment.

Fig. 2 is a block diagram illustrating rate matching and interleaving in accordance with one embodiment.

Fig. 3 is a diagram illustrating performance according to different parameter settings of a HARQ scheme according to one embodiment.

Fig. 4 is a diagram illustrating a polarization encoding circuit according to one embodiment.

Fig. 5 is a block diagram illustrating a receive processing chain according to one embodiment.

Fig. 6 is a diagram illustrating a polarization decoding circuit according to one embodiment.

Fig. 7 is a diagram illustrating nodes in a polarization decoding circuit according to one embodiment.

Fig. 8 is a block diagram illustrating an electronic device circuit, which may be an eNodeB circuit, a User Equipment (UE) circuit, a network node circuit, or some other type of circuit, according to one embodiment.

Fig. 9 is a block diagram illustrating a method for performing polarization encoding according to one embodiment.

Fig. 10 is a block diagram illustrating a method for performing polarization encoding according to one embodiment.

Fig. 11 is a block diagram illustrating a method for a polar decoder according to one embodiment.

FIG. 12 is a block diagram illustrating components of a device according to one embodiment.

Fig. 13 is a block diagram illustrating components according to some embodiments.

Description of The Preferred Embodiment

Wireless mobile communication technology uses various standards and protocols to generate and/or transmit data between a base station and a wireless communication device. Wireless communication system standards and protocols may include, for example, third generation partnership project (3 GPP) Long Term Evolution (LTE); the Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard, commonly referred to in the industry as Worldwide Interoperability for Microwave Access (WiMAX); and the IEEE 802.11 standard, commonly referred to in the industry as Wireless Local Area Network (WLAN) or Wi-Fi. In a 3GPP Radio Access Network (RAN) in an LTE system, a base station may include an evolved universal terrestrial radio access network (E-UTRAN) node B (also commonly referred to as an evolved node B, an enhanced node B, eNodeB, or eNB) and/or a Radio Network Controller (RNC) in the E-UTRAN that communicates with wireless communication devices called User Equipment (UE). In an LTE network, the E-UTRAN may include multiple eNodeBs and may communicate with multiple UEs. LTE networks include Radio Access Technology (RAT) and core radio network architecture, which may provide high data rates, low latency, packet optimization, and improved system capacity and coverage.

Polar codes are a class of error correction codes that enable the ability to communicate channels without memory. Some examples described herein refer to binary polarization codes, but non-binary polarization codes may also be employed using examples described herein.

The encoder can calculateWherein (1)>Is a vector of binary bits, G _N Is a 2 x 2 matrixTo the power of Kronecker, and +.>Is a codeword. The codeword may comprise a vector of binary bits. N represents the length of the vector. For example, a vector of binary bits and a codeword may each include N binary bits. May be transmitted over a channel such as the Physical Uplink Shared Channel (PUSCH) and/or the Physical Downlink Shared Channel (PDSCH)The communication channel of the class, as well as other examples of communication channels, to transmit the codeword. Can be +.>Is provided to an encoder for encoding.

By inputting a desired number of encoders into U _i Set to data bits (e.g., information bits) and freeze the remaining bit values to predetermined values (e.g., zeros) and encode the result to form an output codeword to achieve various encoding rates. The coding rate may be defined as a ratio of the number of data bits input to the encoder to the number of codeword bits output by the encoder. For example, to obtain half code rate, half U may be used _i Bits are set to data bits (e.g., information bits), and the remaining half U may be set _i The bits freeze to their predetermined value (e.g., zero). Selecting which bit index to freeze, what value to freeze, and which bits to use for data may be fixed prior to transmission and may be known at both the transmitter and receiver.

If a receiver (e.g., a User Equipment (UE)) detects an error in the reception of a data packet, e.g., by performing a Cyclic Redundancy Check (CRC), the UE may request additional transmission of the data packet. A transmitter (e.g., an evolved node B (eNodeB)) may then transmit more coded bits and/or parity bits associated with the data packet to assist the receiver in recovering the original data packet. This may be in the form of repetition of the same codeword (or a portion thereof) transmitted via Chase combining of HARQ transmissions and/or in the form of new information about the original data, typically in the form of additional parity bits, via incremental redundancy IR transmissions (HARQ-IR) of HARQ transmissions, or a combination thereof. Several retransmissions may be performed (e.g. until the receiver UE can decode the data packet correctly).

In HARQ operation, if a first transmission of a data packet fails, the transmitter may repeat the same packet or transport block in a second transmission. Based on the encoding (e.g., redundancy version, assigned modulation and coding scheme, etc.), the parity bits selected for the second transmission may or may not be the same as the parity bits sent in the first transmission.

Can be based on each code bit X _i The information and frozen bits can be decoded by preconditions of independent implementation of the transmission of the channel W. In some examples, such as frequency selective fading channels, higher order modulation, and/or puncturing (puncturing) for HARQ-IR purposes, each code bit X _i May be through different types of channels. The quality of these different types of channels can vary widely.

In some examples, a polar coding chain may be implemented for HARQ transmissions that addresses the issues of coding for higher order modulation, robust performance under varying channel conditions, support for chase combining HARQ transmissions and HARQ-IR transmissions, and/or providing rate matching of flexible polar codeword lengths.

Referring now to the drawings in which like reference numbers represent like elements. For purposes of clarity, the first digit of a reference number indicates the figure number in which the corresponding element is first used. In the following description, numerous specific details are provided for a thorough understanding of the embodiments disclosed herein. One skilled in the relevant art will recognize, however, that the embodiments described herein can be practiced without one or more of the specific details, or with other methods, components, or materials. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 is a system diagram illustrating a polarization encoding chain according to one embodiment. Fig. 1 includes a polarization encoding chain 100, which includes: a shortened polarization encoder module 110, a rate matching and channel interleaver (RM & CI) module 112, a modulation module 114, a channel 116, a demodulation module 118, a de-rate matching and channel interleaver (D-MR & CI) module 120, and a shortened polarization decoder module 122.

The shortened polarization encoder module 110, RM & CI module 112, and modulation module 114 may include encoding schemes that may be performed by a UE and/or an eNodeB. The demodulation module 118, the D-MR & CI module 120, and the shortened polarization decoder module 122 may include decoding schemes that may also be performed by the UE and/or eNodeB.

As used in fig. 1 and described in fig. 1, N is 2 ⁿ Base code output length of (c) is provided. K102 is the number of information bits. S is the shortening number of bits. P is the number of puncturing bits. E is the number of extension and/or repetition bits. N (N) _s Is the number of spatial streams. M is the number of bits per modulation. N (N) _BC 104 (e.g., also referred to as N-S104) is to shorten the base codeword length after the polar encoder, which is equal to N-S. N (N) _CB 106 (e.g., also referred to as N-S-P+E106) is rate matching and channel interleaving (e.g., RM&CI module 112) is equal to N-S-P+E.

The plurality of Log Likelihood Ratios (LLRs) associated with K102 are represented by K103. The plurality of LLRs associated with S is denoted by S. The plurality of LLRs associated with P is denoted by P. The plurality of LLRs associated with E is denoted by E. The LLR associated with M is denoted by M. The plurality of LLRs associated with N-S104 is represented by N-S105. The plurality of LLRs associated with N-S-P+E 106 is represented by N-S-p+e 107. And (N-S-P+E)/(N) _S * M) 108 is formed from (n-s-p+e)/(n) _s * m) 109.

As used herein, K102, N, S, P, E, N _S And M may refer to a plurality of bits and/or a number of bits, k 103, n, s, p, e, n _s And m may refer to a number of received bits, LLRs, and/or numbers of LLRs. For example, K102 may be a bit vector comprising 512 bits. K102 may refer to bits and/or a number of bits in a bit vector (e.g., a bit vector length), such as 512 bits. N-S104 may refer to both the bit vector resulting from removing bit vector S from bit vector N and the number of bits (e.g., bit vector length) in the bit vector resulting from removing bit vector S from bit vector N.

For encoding, K102 may be provided to shortened-polarization encoder 110 to produce N-S104. Providing N-S104 to RM&The CI module 112 generates N-S-P+E 106. The N-S-P+E 106 is provided to a modulation module 114 to generate (N-S-P+E)/(N) _S * M) 108. (N-S-P+E)/(N) _S * M) 108 are provided to channel 116 for transmission.

Channel 116 may be a channel that may be defined as (n-s-p+e)/(n) _s *m)109 are provided to demodulation module 118 to generate n-s-p + e 107. n-D-p+r107 may be provided to the D-RM&The CI module 120 generates n-d104. N-d104 is provided to shortened polarization decoder module 122 to generate k 102. Shortening the polarization encoder module 110, RM &The CI module 112, the modulation module 114, and/or the channel 116 may be provided as part of a transmission (e.g., eNodeB). Channel 116, demodulation module 118, D-RM&The CI module 120 and/or the shortened-polarization decoder module 122 may be provided as part of a receiver (e.g., UE).

Shortening polarization encoder module 110 may access the signal-to-noise ratio (SNR) level and base code output length n=2 for one or more SNR levels ⁿ An optimized polar code structure, where n is a positive integer. That is, given the SNR and code length, shortened polarization encoder module 110 may have a predetermined rule for selecting which bits are used as data and which bits are frozen to support several encoding rates between 0 and 1.

Base codeword length N other than a power of 2 _BC The configuration of (e.g., N-S104) is achieved by shortening the process with minimal performance loss. Shortened polarization encoder 110 may select a shortened length S and use a shortened polarization code length N _BC =n-S104 as the base codeword length to be used in rate matching. The shortening length S may be selected in combination with puncturing and expansion parameters.

For example, the polarization coding chain may be used in conjunction with any modulation scheme, such as QAM, multi-antenna mapping, resource mapping, OFDM, and/or single carrier modulation. The receiver performs the inverse operation of the transmitter. LLR values are calculated at demodulator module 118. The LLR values for the extension bits are added together. The puncture bit LLR is set to zero and then the entire LLR block is deinterleaved by the D-RM & CI module 120. The LLR blocks N-S104 are then decoded via a shortened polar decoder module 122. Any polarization decoding scheme may be utilized in shortened polarization decoder module 122.

Fig. 2 is a block diagram illustrating rate matching and interleaving in accordance with one embodiment. Fig. 2 includes an RM & CI module 212 that includes an interleaving module 230 and a rate matching module 232. N-S204-1 may be provided to interleaving module 230 to generate N-S204-2. N-S204-2 may be provided to rate matching module 232 to generate N-S-p+e 206.

Following the code shortening is an interleaving module 230 in the RM & CI module 212. The RM & CI module 212 may configure the codeword such that each bit in the codeword is statistically subject to the same amount of noise. That is, RM & CI module 212 may configure the codeword such that each bit in the codeword is equally protected. In some examples, RM & CI module 212 may be similar to a bit interleaver or a sub-block interleaver in Bit Interleaved Coded Modulation (BICM) in LTE rate matching.

The proposed embodiments avoid constructing a different polarization code for each possible channel variation pattern. For example, in a frequency selective fading channel in an Orthogonal Frequency Division Multiplexing (OFDM)/Orthogonal Frequency Division Multiple Access (OFDMA) system, channel gains at different subcarriers may be different. For most higher order modulation methods, such as 16 quadrature amplitude modulation (16 QAM) or higher, different bits have different bit channel qualities. Code puncturing may also result in time-varying channels, where the punctured code bits have zero reliability at the receiver.

The interleaving module 230 may be optimized for shortening, puncturing, spreading, and/or fading patterns. Since the shortening, puncturing, and/or spreading patterns can be optimized based on fading or time varying patterns of the channel, the number of optimizations can be very large and/or the optimizations can be intractable. As such, a single interleaving module 230 is used in the embodiments described herein as part of RM & CI module 212.

In some examples, interleaving module 230 may be a random interleaver. Existing interleaving rules (e.g., sub-block interleavers and/or turbo code inner interleavers) may be used in LTE/LTE-a systems.

Rate matching begins with selecting a shortened length of the base code output length (parent polarization code). The rate matching module 232 completes the rate matching process by puncturing and/or expanding the shortened and interleaved codeword N-S204-2. The shortening, puncturing, and/or expanding length are jointly selected to match the specified code rate and HARQ requirements.

Perforating the bits refers to the slaveBits are deleted from the bit vector. Spreading the code refers to retransmitting certain code bits. N, S, P and/or E are positive integers. If P>0, the last P bits of the shortened and interleaved base codeword may be punctured. The last bit may refer to the bit associated with the largest index of the bit vector (e.g., codeword). The last P bits refer to the P bits associated with the largest index of the codeword. If E >0, the first E bits may be extended (e.g., repeated). The first bit of the codeword is a bit associated with the first index of the codeword bit vector. The first E bits refer to the first E bits from the codeword bit vector. If (c) ₀ ,c ₁ ,…,c _N-S-1 ) The bit vector represents the shortened and interleaved base codeword (e.g., N-S204-2), then the output of rate matching module 232 may be (c) ₀ ,c ₁ ,…,c _N-S-P-1 ,c ₀ ,c ₁ ,…,c _E-1 ) Bit vector (e.g., N-S-P+E 206). The N-S-P + E206 may then be provided for HARQ-IR transmission via a circular buffer.

Parameters N, S, P and/or E may be selected. For example, the number of encoded bits before modulation for initial transmission may be N _CB =n-S-p+e=768, and the number of information bits may be k=12. HARQ may indicate that the IR bit number is also N _CB =768. The code rate may be defined as r=k/N _CB . There are many S, P and/or E choices that can satisfy N _CB And K. Provides that satisfy N _CB And many examples of K.

In a first example of this, the first and second embodiments,S＝N-N _CB p=0 and/or e=0. In a second example of the present invention,S＝0，P＝N-N _CB and/or e=0. That is, in some examples, e=0 and/or at least two of S, P and E may be equal to zero. In other examples, for HARQ chase combining, +.>S＝0，P＝0And/or e=n _CB -N. In some examples, a->Representing a rounding up (rounding) function.

Since shortening results in minimal error performance loss, only the first example of shortening is used for initial transmission. In a first example, no bits are punctured or spread. Subsequent transmissions of the first example include a simple repetition of the first transmission. For example, HARQ transmission may be performed using chase combining. As such, the first example may be selected for chase combining HARQ transmissions.

A second example may be selected for HARQ-IR transmission. For the initial transmission, the second example may perform worse than the first example, as shown in fig. 3. However, for subsequent HARQ transmissions, the second example may perform better than the first example, as shown in fig. 3. As such, S, P and/or E may be selected according to the HARQ scheme used to transmit the codeword. Some of these values may be predetermined for a given transport block size and HARQ version, or may be explicitly signaled in a control channel such as the Physical Downlink Control Channel (PDCCH).

Fig. 3 is a diagram illustrating performance according to different parameter settings of a HARQ scheme according to one embodiment. Fig. 3 includes a graph 336 that includes a block error rate (BLER) axis 338 and an SNR340.

Graph 336 shows that the first example initial transmission 342 described with respect to fig. 2 performs better than the second example initial transmission 344. Performance may be determined based on BLER. As such, initial transmission 342 may have a lower BLER than initial transmission 344. The graph 336 also shows that the second transmission 346 of the second example performs better than the second transmission 348 of the first example.

Fig. 4 is a diagram illustrating a polarization encoding circuit 410 according to one embodiment. The polarization encoding circuit 410 may correspond to the shortened polarization encoder 110 of fig. 1. Polarization encoding circuit 410 shows an a-bit vector 450, which corresponds to K102 in fig. 1. The polarization encoding circuit 410 also shows a D bit vector 456, which corresponds to N-S104 in fig. 1. The polarization encoding circuit 410 also shows a B-bit vector 452 and a C-bit vector 454. The a-bit vector 450 may be an input bit vector and the D-bit vector 456 may be a result bit vector. B bit vector 452 and C bit vector 454 are internal bit vectors.

The a-bit vector 450 includes bits (a ₀ ，...，a ₇ ). B bit vector 452 includes bits (B ₀ ，...，b ₇ ). The C-bit vector 454 includes bits (C ₀ ，...，c ₇ ). D bit vector 456 includes bits (D ₀ ，...，d ₇ )。

To generate a codeword of length 8, there may be a total of 32 bits as shown in the polarization encoding circuit 410. For a code of length N, a total of N (log ₂ N+1) bits. The a-bit vector 450 may include the original data bits (e.g., K102 in fig. 1) and the freeze bits that are input to the polarization encoding circuit 410. The D bit vector 456 includes codeword bits (D ₀ ，...，d ₇ ). B bit vector 452 (e.g., (B) ₀ ，...，b ₇ ) And a C-bit vector 454 (e.g., (C) ₀ ，...，c ₇ ) Including the inner part calculated during the encoding process but not normally transmitted or considered as part of the codeword. There is some identity between the bits. For example, a ₇ ＝b ₇ ＝c ₇ ＝d ₇ And b ₂ ＝c ₂ . In the proposed method, a transmitter (e.g., eNodeB) may generate and/or transmit a subset of 32 bits in each retransmission. The transmitter may select different subsets based on different system requirements and/or capabilities.

The stage corresponding to generating the B-bit vector 452 and/or the C-bit vector 454 is referred to as an intermediate stage or a stage associated with an inner bit. The stage corresponding to the D bit vector 456 is referred to as the stage associated with polarization encoded legacy codewords.

The transmitter may generate, provide, and/or transmit a subset of the D-bit vector 456 in each transmission and retransmission to generate, provide, and/or transmit a chase combining HARQ transmission. The retransmission may include internal bits (e.g., a subset of B-bit vector 452 and/or C-bit vector 454) that are not necessarily present in a typical polarized codeword. As such, generating and/or transmitting the inner bits may include generating and/or transmitting a new set of parity bits.

Many examples may support HARQ transmissions by utilizing bits that are typically internal to the polarization encoding circuit 410 and are not typically in the original codeword. For retransmission, the selected subset of bits may include a mix of typical codeword bits and inner bits. This corresponds to, for example, a mix of chase/IR schemes. An example of this is sending in retransmission (b ₀ ，...，b ₇ )。

For a general transmission mode that includes puncturing and spreading for rate matching, unique bits may be placed in the circular buffer. For example, the buffer may be expanded to d ₀ ，...，d ₇ ，c ₀ ，...，c ₆ ，b ₀ ，b _l ，b ₄ ，b ₅ ，a ₀ ，a ₂ ，a ₄ ，a ₆ (again) d ₀ ，...，d ₇ C 0. In some examples, the bits may be placed in the circular buffer in any other order. In each transmission, the transmitter may transmit the next bit in the buffer. These next bits may include multiple bits in a buffer as desired. The buffer may wrap around to the beginning when the last bit in the buffer is reached. The encoding may be systematic or partially systematic. That is, the information block bits or some of the information block bits may appear in the buffer.

The polarization encoding circuit 410 may include a plurality of nodes in which a plurality of operations are performed. For example, the polarization encoding circuit 410 may include a check node 460 and a variable node 462.

Inspection node 460 is shown in fig. 4 as a circle with a plus sign therein. The check node 460 may perform operations such as exclusive or (XOR) operations. Each check node 460 may receive two bits as inputs and may generate an output by applying operations to the two bits. For example, AND bit a ₀ A consistent inspection node may receive a ₀ Bit sum a ₁ Bits are used as inputs. The check node may generate b ₀ And (5) a node. And a ₂ The check node of bit agreement may receive a ₂ Bit sum a ₃ Bits to generate b ₂ Bits. In other examples of check node 460, AND a ₀ Bit sum b ₀ The check node of bit agreement may receive b ₀ Bit sum b ₂ Bits to generate c ₀ Bits. The bits generated by inspection node 460 are unique bits.

Variable node 462 is shown as a point in polarization encoding circuit 410. Variable node 462 may perform a copy operation. For example, with a ₁ A can be replicated by a variable node with consistent bits ₁ Bits to generate b ₁ Bits. Thus, a ₁ Bit equal to b ₁ Bits. That is, a ₁ Bit sum b ₁ None of the bits are unique. The bits generated by variable node 462 are non-unique bits.

Fig. 5 is a block diagram illustrating a receive processing chain 500 according to one embodiment. The receive processing chain 500 includes a decoder module 522, a HARQ memory module 560, a soft combining module 562, and an LLR initializer for an internal bit module 564. The receive processing chain 500 also includes channel LLRs. Decoder module 522, HARQ memory module 560, soft combining module 562, and/or an LLR initializer for inner bit module 564 may be similar to shortened polarization decoder 122 in fig. 1.

The receive processing chain 500 may be implemented as part of a receiver (e.g., UE). Channel LLR module 568 can provide LLRs corresponding to the bits provided by the channel. Channel LLR module 568 may generate LLRs and/or may provide LLRs generated by the channel. The LLR corresponds to the current transmission of the packet.

Soft combining module 562 combines the LLRs of the current packet provided by channel LLR module 568 with the LLRs of the previous transmission of the packet stored in HARQ memory module 560. Since the transmission (e.g., the combined previous and current transmissions) may include LLRs corresponding to codeword bits and inner bits, soft combining module 562 outputs both types of LLRs. That is, soft combining module 562 generates and/or initializes the LLRs for the inner bits via the LLR initializer for inner bit module 564. The inner-bit LLRs are individually input (e.g., logically) to decoder module 522 from the LLRs corresponding to the codeword LLRs so that decoder module 522 may use the inner-bit LLRs to initialize steps in decoding (e.g., list decoding, successive cancellation decoding, etc.).

Fig. 6 is a diagram illustrating a polar decoding circuit 622 according to one embodiment. The polarization decoding circuit 622 may be part of the decoder 522 in fig. 5. The polarization decoding circuit 622 may include a D vector 656, a C vector 654, a B vector 652, and an a vector 650. The polarization decoding circuit 622 may also include a check node 650 and a variable node 662. The polarization decoding circuit 622 may also include a hanging edge (hanging edge) 670.

The polar decoder may be enhanced by incorporating information from the transmission (retransmission) as shown by the hanging edge 670. The polar decoder may be any message passing algorithm; for example, successive elimination decoders, list decoders, and/or belief propagation. Enhancements including hanging edges 670 may be incorporated into any polar decoder.

In the polar decoder circuit 622, each edge may hold a message (e.g., a list of messages, such as in the case of list decoding) in the form of an LLR. The edges are shown in the polar decoder circuit 622 as being connected to the edges of the nodes at both ends and to the hanging edges of the nodes at only one end.

In fig. 6, vectors 650, 652, 654, and 656 represent bits and/or messages. The message may include LLRs and/or bits provided by the channel. Messages associated with vectors 650, 652, 654 and 656 correspond to a-bit vector 450, B-bit vector 452, C-bit vector 456, and D-bit vector 458, respectively, in fig. 4.

As described above, enhanced retransmission involves transmitting parity bits in addition to the polarized codeword, typically inside the original encoder. To use parity bits (e.g., internally unique bits or internal bits) in decoding, variable nodes 662 with additional hanging edges 670 that strictly correspond to internal bit positions (e.g., unique bits) are incorporated into decoder circuit 622. The unique bits may include, for example, bit c in FIG. 4 ₀ Which may correspond to c in fig. 6 ₀ Messages and corresponding hanging edges coupled to decoder circuit 622 via variable nodes 662.

Using hanging edges 670 associated with unique bitsIncluding initializing LLRs and/or messages associated with hanging edge 670. That is, a decoder including decoder circuit 622 may be initialized with the LLRs for the received bits. For example, if a is in FIG. 4 ₀ Frozen to zero, a including the associated LLR ₀ The message may be initialized to infinity or to a very large number in a scheme that associates positive LLRs with binary 0 bits and negative LLRs with binary 1 bits. In some examples, frozen bits on edges of the decoder circuit and/or encoder circuit may produce frozen internal bits. In this way, bits from the encoder may be selected for transmission, frozen bits may be excluded as long as the value of the frozen bits is known and may be certainly recreated at the decoder. If a bit in the graph is not frozen, its hanging edge LLR may be initialized to the sum of the LLRs received for that bit, and if it has never been sent, to zero. For example, the LLR of the hanging edge 670 corresponding to the inner bit on the third transmission may be initialized to the sum of the LLRs received for that bit during the first, second, and third transmissions. The LLRs may be used to determine whether the bit vector received from the channel is the bit vector provided to the channel.

Fig. 7 is a diagram illustrating nodes in a polarization decoding circuit according to one embodiment. Fig. 7 includes nodes 772-1 and 772-2 shown in four different examples. FIG. 7 also includes messages 780-1 and 780-2 and message 784.

Message 780-1 may be provided from node 772-2 to node 772-1. Message 780-2 may also be provided from node 772-1 to node 772-2. In some examples, message 780-1 may be provided from node 772-2 to node 772-1 via node 772-3. Message 780-2 may be provided from node 772-1 to node 772-2 via node 772-3.

Adding a variable node (e.g., node 773) and a hanging edge corresponding to the inner bits may allow any existing messaging schedule in the decoder to be enhanced. The edges in fig. 7 represent the horizontal edges in fig. 6. Nodes 772-1 and 772-2 (e.g., nodes X and Y) may be any two neighboring nodes in fig. 6. The enhanced decoder may include nodes 772-1 and 772-2Added variable node 772-3 and has an associated message 784 (e.g., message l _XY ) Is provided, the respective hanging edge of (a) is provided. In the decoder, after generating message 780-2 (e.g., message m _XY ) After each access to node 772-1, a newly introduced node 772-3 is accessed, which calculates l _XY +m _XY And writes the result to node 772-2. The same operation can be done in the opposite direction. That is, after generating message 780-1 (e.g., message m _XY ) After accessing node 772-2, newly introduced node 772-3 is accessed, which calculates l _XY +m _XY And writes the result to node 772-1.

At the transmitter, a redundancy version indicator may be used to indicate which bits of the buffer are to be transmitted in a given transmission for the data packet. The redundancy version may be explicitly indicated in the control information associated with the information block (or transport block) or may be implicitly bound to a known parameter such as a subframe number or a transport number. For example, the redundancy version indicator may be equal to 1 for the first transmission and/or 2 for the second transmission, and so on. The transmission number may be used for a self-decodable transmission.

Fig. 8 is a block diagram illustrating an electronic device circuit, which may be an eNodeB circuit, a User Equipment (UE) circuit, a network node circuit, or some other type of circuit, according to one embodiment. Fig. 8 illustrates an electronic device 800, which electronic device 800 may be an eNodeB, a UE, or some other type of electronic device, in accordance with various embodiments; or may be incorporated into an eNodeB, a UE, or some other type of electronic device; or may otherwise be part of an eNodeB, a UE, or some other type of electronic device. In particular, electronic device 800 may be logic and/or circuitry that may be implemented, at least in part, in one or more of hardware, software, and/or firmware. In an embodiment, the electronics logic may include radio transmitter/transmitter logic (e.g., first transmitter logic 877) and receiver/receiver logic (e.g., first receiver logic 883) coupled to the control logic 873 and/or the processor 871. In an embodiment, the transmitter/transmitter and/or receiver/receiver logic may be elements or modules of transceiver logic. The first transmitter logic 877 and the first receiver logic 883 may be housed in separate devices. For example, the first transmitter logic 877 may be incorporated into a first device and the first receiver logic 883 incorporated into a second device, or the first transmitter logic 877 and the first receiver logic 883 may be incorporated into separate devices from the devices including any combination of the control logic 873, the memory 879, and/or the processor 871. The electronic device 800 may be coupled with one or more antenna elements 885 of one or more antennas or may include the one or more antenna elements 885. The electronic device 800 and/or components of the electronic device 800 may be configured to perform operations similar to those described elsewhere in this disclosure.

In some embodiments, the electronic device 800 implements a UE, and/or an eNodeB, or a device portion thereof, or the electronic device 800 is incorporated into a UE, and/or an eNodeB, or a device portion thereof, or the electronic device 800 otherwise becomes part of a UE, and/or an eNodeB, or a device portion thereof, the electronic device 800 may generate and/or transmit a polarization code. The processor 871 can be coupled to a first receiver and a first transmitter. The memory 879 may be coupled to the processor 871 with control logic instructions thereon that, when executed, generate and/or transmit polarization codes.

In some embodiments thereof, the electronic device 300 receives data from the UE, generates data, and/or transmits data to the UE to implement a downlink signal including a polarization code, and the processor 871 may be coupled to a receiver and a transmitter. The memory 879 may be coupled to the processor 871 with control logic instructions thereon that, when executed, are capable of configuring V2X communications based on geographic location.

The term "logic" as used herein may be, may be part of, or may include: an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor 871 (shared, dedicated, or group) and/or memory 879 (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In particular, the logic may be implemented at least in part in hardware, software, and/or firmware, or in elements thereof. In some embodiments, the electronic device logic may be implemented by or functions associated with one or more software or firmware modules.

Fig. 9 is a block diagram illustrating a method 985 for performing polarization encoding according to one embodiment. The method 985 includes: selecting (903) a length S of the shortened number of bits and a length P of the punctured number of bits based on the HARQ scheme; encoding (905) the plurality of information bits via a polarization encoder module to generate a base code having a length N minus a shortened number of bits; interleaving (907) the result of the polar encoder module via an interleaver module to generate a codeword comprising a base code minus shortened bits, minus punctured bits, plus extended bits of length E; providing (909) the codeword to a modulation module to generate a result of dividing the codeword by the multiplication of the spatial stream number and the number of bits per modulation; and providing (911) the result of the division to a channel to transmit the polarization code to a receiving device.

The HARQ scheme may include chase combining transmissions and/or HARQ-IR transmissions. The method 985 also includes setting N to 2 (ceil (log 2 (N) _CB ) And E is set to zero, where N _CB Is the length of the codeword. Method 985 further includes setting S to N-N _CB And P is set to zero. Method 985 may also include setting S to zero and P to N-N _CB 。

The method 985 may also include setting N to 2 (floor (log 2 (N) _CB ) Where N is _CB Is the length of the codeword and sets E to N _CB -N. Method 985 may further include setting S to zero and P to zero.

Fig. 10 is a block diagram illustrating a method 1087 for performing polarization encoding according to one embodiment. The method 1087 includes: generating (1021) at least a plurality of B internal bits by performing a plurality of operations on the a data bits; generating (1023) a plurality of D codeword bits by performing a plurality of operations on the B inner bits, wherein the D codeword bits correspond to a first stage of a polarization encoder and the B inner bits correspond to a second stage of the polarization encoder, and wherein the first stage and the second stage are different stages of the polarization encoder; and providing (1025) the subset of the a data bits, the D codeword bits, and the B inner bits to a channel for transmission.

The HARQ transmission may be at least one of a chase combining HARQ transmission and a HARQ-IR transmission. The a data bits may include data bits and freeze bits. The length of the a data bits, the length of the B inner bits, and the length of the D codeword bits may be the same length. Method 1087 further includes generating a subsequent HARQ transmission comprising a subset of the a data bits, the B inner bits, and the D codeword bits.

The HARQ transmission may include a circular buffer of a subset of a data bits, B inner bits, and D codeword bits. The subset of a data bits, B inner bits, and D codeword bits may include at least one of: d codeword bits and B inner bits, a portion of B inner bits and D codeword bits, a portion of D codeword bits and B inner bits, or B inner bits.

Fig. 11 is a block diagram illustrating a method 1189 for a polar decoder, according to one embodiment. The method 1189 includes: initializing (1131) a first plurality of LLRs for a plurality of bits received from a channel associated with the HARQ transmission; initializing (1133) a second plurality of LLRs for the plurality of hanging edges associated with the plurality of bits; performing (1135) a plurality of operations on the first plurality of messages and the second plurality of messages to generate a third plurality of LLRs, wherein the first plurality of messages includes the first plurality of LLRs and the second plurality of messages includes the second plurality of LLRs; and determining (1137) an estimate of the information block comprising the first plurality of bits and the second plurality of bits based on the third LLR.

In some examples, the plurality of operations includes an add operation. Each of the plurality of operations may further include a minimization operation for determining a minimum LLR of the absolute values of the first LLR and the absolute values of the second LLR, a multiplication operation for determining a symbol by multiplying the symbol of the first LLR by the symbol of the second LLR, and providing the minimum LLR with the symbol.

The method 1189 further includes initializing LLRs from the first and second pluralities of LLRs associated with frozen bits from the first and second pluralities of bits to a predefined value, initializing LLRs from the first and second pluralities of LLRs associated with non-frozen bits from the first and second pluralities of bits to a sum of received LLRs associated with the bits, and initializing LLRs from the first and second pluralities of LLRs to zero for non-received bits. The estimation of the information block may comprise which codeword is transmitted over the channel. The second plurality of bits may be associated with inner bits of the polarization code.

FIG. 12 is a block diagram illustrating components of a device according to one embodiment. In some embodiments, the device may include an application circuit 1203, a baseband circuit 1205, a Radio Frequency (RF) circuit 1207, a Front End Module (FEM) circuit 1209, and one or more antennas 1214 coupled to each other as shown at least in fig. 12. Any combination or subset of these components may be included in, for example, a UE device or an eNodeB device.

The application circuitry 1203 may include one or more application processors. As non-limiting examples, the application circuitry 1203 may include one or more single or multi-core processors. The processor(s) may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, etc.). The processor(s) may be operably coupled to and/or may include memory/storage and may be configured to execute instructions stored in the memory/storage to cause various applications and/or operating systems to run on the system.

As a non-limiting example, baseband circuitry 1205 may include one or more single-core or multi-core processors. The baseband circuitry 1205 may include one or more baseband processors and/or control logic. The baseband circuitry 1205 may be configured to process baseband signals received from the receive signal path of the RF circuitry 1207. The baseband circuitry 1205 may also be configured to generate baseband signals for the transmit signal path of the RF circuitry 1207. The baseband circuitry 1205 may interact with the application circuitry 1203 for generating and processing baseband signals and for controlling the operation of the RF circuitry 1207.

As non-limiting examples, the baseband circuitry 1205 may include at least one of a second generation (2G) baseband processor 1211A, a third generation (3G) baseband processor 1211B, a fourth generation (4G) baseband processor 1211C, and other baseband processor(s) 1211D for other existing, developing, or future developed generations (e.g., fifth generation (5G), sixth generation (6G), etc.). The baseband circuitry 1205 (e.g., at least one of the baseband processors 1211A-1211D) may handle various radio control functions that enable communication with one or more radio networks through the RF circuitry 1207. As non-limiting examples, radio control functions may include signal modulation/demodulation, encoding/decoding, radio frequency shifting, other functions, and combinations thereof. In some embodiments, the modulation/demodulation circuitry of baseband circuitry 1205 may be programmed to perform Fast Fourier Transform (FFT), precoding, and constellation mapping/demapping functions, other functions, and combinations thereof. In some embodiments, the encoding/decoding circuitry of baseband circuitry 1205 may be programmed to perform convolution, tail biting convolution, turbo, viterbi, and Low Density Parity Check (LDPC) encoder/decoder functions, other functions, and combinations thereof. Embodiments of the modem and encoder/decoder functions are not limited to these examples and may include other suitable functions.

In some embodiments, baseband circuitry 1205 may include elements of a protocol stack. As non-limiting examples, elements of the Evolved Universal Terrestrial Radio Access Network (EUTRAN) protocol include, for example, physical (PHY), medium Access Control (MAC), radio Link Control (RLC), packet Data Convergence Protocol (PDCP), and/or Radio Resource Control (RRC) elements. A Central Processing Unit (CPU) 1211E of the baseband circuitry 1205 may be programmed to run elements of a protocol stack for PHY, MAC, RLC, PDCP, and/or RRC layer signaling. In some embodiments, baseband circuitry 1205 may include one or more audio Digital Signal Processors (DSPs) 1211F. The audio DSP(s) 1211F may include elements for compression/decompression and echo cancellation. The audio DSP(s) 1211F may also include other suitable processing elements.

The baseband circuitry 1205 may also include memory/storage 1211G. The memory/storage 1211G may include data and/or instructions stored thereon for operation performed by the processor of the baseband circuit 1205. In some embodiments, memory/storage 1211G may include any combination of suitable volatile memory and/or nonvolatile memory. Memory/storage 1211G may also include any combination of various levels of memory/storage including, but not limited to, read-only memory (ROM) with embedded software instructions (e.g., firmware), random access memory (e.g., dynamic Random Access Memory (DRAM)), cache, buffers, and the like. In some embodiments, memory/storage 1211G may be shared among various processors or dedicated to a particular processor.

In some embodiments, the components of baseband circuitry 1205 may be suitably combined in a single chip or a single chipset, or suitably arranged on the same circuit board. In some embodiments, some or all of the constituent components of baseband circuitry 1205 and application circuitry 1203 may be implemented together, e.g., on a system on a chip (SOC).

In some embodiments, baseband circuitry 1205 may provide communication compatible with one or more radio technologies. For example, in some embodiments, baseband circuitry 1205 may support communication with an Evolved Universal Terrestrial Radio Access Network (EUTRAN) and/or other Wireless Metropolitan Area Network (WMAN), a Wireless Local Area Network (WLAN), or a Wireless Personal Area Network (WPAN). In some embodiments, baseband circuitry 1205 is configured to support radio communications for more than one wireless protocol, which may be referred to as multimode baseband circuitry.

The RF circuitry 1207 may enable communication with a wireless network using modulated electromagnetic radiation over a non-solid medium. In various embodiments, RF circuitry 1207 may include switches, filters, amplifiers, and the like to facilitate communications with a wireless network. RF circuitry 1207 may include a receive signal path, which may include circuitry to down-convert RF signals received from FEM circuitry 1209 and provide baseband signals to baseband circuitry 1205. RF circuitry 1207 may also include transmit signal paths, which may include circuitry to upconvert baseband signals provided by baseband circuitry 1205 and provide RF output signals to FEM circuitry 1209 for transmission.

In some embodiments, RF circuitry 1207 may include a receive signal path and a transmit signal path. The receive signal path of the RF circuit 1207 may include a mixer circuit 1213A, an amplifier circuit 1213B, and a filter circuit 1213C. The transmit signal path of RF circuit 1207 may include a filter circuit 1213C and a mixer circuit 1213A. The RF circuit 1207 may also include a synthesizer circuit 1213D configured to synthesize frequencies for use by the mixer circuit 1213A of the receive signal path and the transmit signal path. In some embodiments, the mixer circuit 1213A of the receive signal path may be configured to down-convert the RF signal received from the FEM circuit 1209 based on the synthesized frequency provided by the synthesizer circuit 1213D. The amplifier circuit 1213B may be configured to amplify the down-converted signal.

The filter circuit 1213C may include a Low Pass Filter (LPF) or a Band Pass Filter (BPF) configured to remove unwanted signals from the down-converted signals to generate an output baseband signal. The output baseband signal may be provided to baseband circuitry 1205 for further processing. In some embodiments, the output baseband signal may include a zero frequency baseband signal, but this is not required. In some embodiments, mixer circuit 1213A of the receive signal path may include a passive mixer, although the scope of the embodiments is not limited in this respect.

In some embodiments, the mixer circuit 1213A of the transmit signal path may be configured to upconvert the input baseband signal based on the synthesized frequency provided by the synthesizer circuit 1213D to generate an RF output signal for the FEM circuit 1209. The baseband signal may be provided by baseband circuitry 1205 and may be filtered by filter circuitry 1213C. The filter circuit 1213C may include a Low Pass Filter (LPF), although the scope of the embodiments is not limited in this respect.

In some embodiments, the mixer circuit 1213A of the receive signal path and the mixer circuit 1213A of the transmit signal path may include two or more mixers, and may be arranged for quadrature down-conversion or up-conversion, respectively. In some embodiments, the mixer circuit 1213A of the receive signal path and the mixer circuit 1213A of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., hartley image rejection). In some embodiments, the mixer circuit 1213A of the receive signal path and the mixer circuit 1213A of the transmit signal path may be arranged for direct down-conversion and/or direct up-conversion, respectively. In some embodiments, the mixer circuit 1213A of the receive signal path and the mixer circuit 1213A of the transmit signal path may be configured for superheterodyne operation.

In some embodiments, the output baseband signal and the input baseband signal may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternative embodiments, the output baseband signal and the input baseband signal may be digital baseband signals. In such embodiments, RF circuitry 1207 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry, and baseband circuitry 1205 may include a digital baseband interface for communicating with RF circuitry 1207.

In some dual mode embodiments, separate radio IC circuits may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.

In some embodiments, synthesizer circuit 1213D may include one or more of a fractional-N synthesizer or a fractional-N/n+1 synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, the synthesizer circuit 1213D may include a delta-sigma synthesizer, a frequency multiplier, or a synthesizer including a phase locked loop with a frequency divider, other synthesizers, and combinations thereof.

The synthesizer circuit 1213D may be configured to synthesize an output frequency based on the frequency input and the divider control input for use by the mixer circuit 1213A of the RF circuit 1207. In some embodiments, the synthesizer circuit 1213D may be a fractional N/n+1 synthesizer.

In some embodiments, the frequency input may be provided by a Voltage Controlled Oscillator (VCO), but this is not required. The divider control input may be provided by baseband circuitry 1205 or application circuitry 1203 depending on the desired output frequency. In some embodiments, the divider control input (e.g., N) may be determined from a look-up table based on the channel indicated by application circuit 1203.

The synthesizer circuit 1213D of the RF circuit 1207 may include a frequency divider, a Delay Locked Loop (DLL), a multiplexer, and a phase accumulator. In some embodiments, the frequency divider may comprise a dual mode frequency divider (DMD) and the phase accumulator may comprise a Digital Phase Accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by N or n+1 (e.g., based on a carry) to provide a fractional division ratio. In some example embodiments, a DLL may include a set of cascaded tunable delay elements, a phase detector, a charge pump, and a D-type flip-flop. In such embodiments, the delay elements may be configured to decompose the VCO period into up to Nd equal phase packets, where Nd is the number of delay elements in the delay line. In this way, the DLL can provide negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

In some embodiments, the synthesizer circuit 1213D may be configured to generate a carrier frequency as the output frequency. In some embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency, etc.), and used in conjunction with the quadrature generator and divider circuit to generate a plurality of signals at the carrier frequency having a plurality of phases that are different from one another. In some embodiments, the output frequency may be an LO frequency (fLO). In some embodiments, the RF circuit 1207 may include an IQ/polarity converter.

FEM circuitry 1209 may include a receive signal path, which may include circuitry configured to operate on RF signals received from one or more antennas 1214, amplify the received signals, and provide an amplified version of the received signals to RF circuitry 1207 for further processing. FEM circuitry 1209 may also include a transmit signal path, which may include circuitry configured to amplify signals provided by RF circuitry 1207 for transmission by at least one of the one or more antennas 1214.

In some embodiments, FEM circuitry 1209 may include TX/RX switches configured to switch between transmit mode and receive mode operation. FEM circuitry 1209 may include a receive signal path and a transmit signal path. The receive signal path of FEM circuitry 1209 may include a Low Noise Amplifier (LNA) to amplify the received RF signal and provide an amplified received RF signal as an output (e.g., to RF circuitry 1207). The transmit signal path of FEM circuitry 1209 may include a Power Amplifier (PA) configured to amplify an input RF signal (e.g., provided by RF circuitry 1207), and may include one or more filters configured to generate an RF signal for subsequent transmission (e.g., through one or more of the one or more antennas 1214).

In some embodiments, the apparatus may include additional elements, such as memory/storage, a display, a camera, one or more sensors, an input/output (I/O) interface, other elements, or a combination thereof.

In some embodiments, a device may be configured to perform one or more of the processes, techniques, and/or methods described herein, or portions thereof.

Fig. 13 is a block diagram illustrating components according to some embodiments. In particular, FIG. 13 shows a diagram of a hardware resource 1300, the hardware resource 1300 comprising one or more processors (or processor cores) 1310, one or more memory/storage devices 1320, and one or more communication resources 1330, all communicatively coupled via a bus 1340.

The processor 1310 (e.g., a Central Processing Unit (CPU), a Reduced Instruction Set Computing (RISC) processor, a Complex Instruction Set Computing (CISC) processor, a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP) (e.g., a baseband processor), an Application Specific Integrated Circuit (ASIC), a Radio Frequency Integrated Circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, processor 1312 and processor 1314. Memory/storage 1320 may include main memory, disk memory, or any suitable combination thereof.

Communication resource 1330 may be packagedIncluding an interconnection and/or network interface component or other suitable device for communicating with one or more peripheral devices 1304 and/or one or more databases 1311 over the network 1308. For example, the communication resources 1330 can include wired communication components (e.g., for coupling through a Universal Serial Bus (USB)), cellular communication components, near Field Communication (NFC) components,Components (e.g.)>Low power consumption)/(f)>Components, and other communication components.

The instructions 1350 may include software, programs, applications, applets, apps, or other executable code for causing the at least one processor 1310 to perform any one or more of the methods discussed herein. The instructions 1350 may reside, completely or partially, within the at least one processor 1310 (e.g., within a cache memory of the processor), the memory/storage device 1320, or any suitable combination thereof. Further, any portion of the instructions 1350 may be transferred from any combination of the peripherals 1304 and/or databases 1311 to the hardware resources 1300. Thus, the memory of the processor 1310, the memory/storage 1320, the peripherals 1304, and the database 1311 are examples of computer readable and machine readable media.

Example embodiment

Example 1 is an apparatus for performing polarization encoding. The apparatus includes an electronic memory for storing a plurality of data bits for use in a first stage of a polarization encoder different from a second stage of the polarization encoder. The apparatus comprises one or more baseband processing units designed to generate at least a plurality of inner bits in a first stage of a polarization encoder by performing a plurality of operations on data bits, wherein the inner bits are internal to the polarization encoder. The apparatus includes one or more baseband processing units designed to generate a plurality of codeword bits in a second stage of a polarization encoder by performing a plurality of operations on internal bits, wherein the codeword bits correspond to the second stage of the polarization encoder and the internal bits correspond to the first stage of the polarization encoder. The apparatus includes one or more baseband processing units designed to provide a subset of data bits, codeword bits, and inner bits to a channel of a physical layer for hybrid automatic repeat request (HARQ) transmission.

Example 2 is the apparatus of example 1, wherein the apparatus is a User Equipment (UE), and wherein the channel is at least one of an uplink channel and a side link channel.

Example 3 is the apparatus of example 1, wherein the apparatus is an evolved user node (eNodeB), and wherein the channel is at least one of a downlink channel.

Example 4 is the apparatus of example 1, wherein the transmission is at least one of a chase combining HARQ transmission and a HARQ incremental redundancy (HARQ-IR) transmission.

Example 5 is the apparatus of example 1, wherein the data bits for the first stage of the polar encoder comprise bits set to a predetermined value.

Example 6 is the apparatus of example 1, wherein the length of the data bits, the length of the inner bits, and the length of the codeword bits are the same length.

Example 7 is the apparatus of example 1, wherein the one or more processing units are further designed to generate a subsequent HARQ transmission comprising a subsequent subset of data bits, inner bits, and codeword bits, the subsequent subset being different from the subset of data bits, inner bits, and codeword bits.

Example 8 is the apparatus of example 1, wherein the HARQ transmission comprises a circular buffer of data bits, inner bits, and a subset of codeword bits.

Example 9 is the apparatus of example 1, wherein the subset of data bits, inner bits, and codeword bits comprises one of: codeword bits and inner bits, a portion of inner bits and codeword bits, and an inner bit.

Example 10 is a computer-readable storage medium. The computer-readable storage medium has instructions stored thereon that, when implemented by a computing device, cause the computing device to initialize a first plurality of Log Likelihood Ratios (LLRs) of a plurality of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request (HARQ) transmission. The computer-readable storage medium has instructions stored thereon that, when implemented by a computing device, cause the computing device to initialize a second plurality of LLRs for a plurality of hanging edges of a polar decoder associated with a plurality of bits. The computer-readable storage medium has instructions stored thereon that, when implemented by a computing device, cause the computing device to perform a plurality of operations on the first plurality of LLRs and the second plurality of LLRs to generate a third plurality of LLRs. The computer-readable storage medium has instructions stored thereon that, when implemented by a computing device, cause the computing device to determine an estimate of an information block comprising a first plurality of bits and a second plurality of bits based on a third plurality of LLRs, wherein the first plurality of bits and the second plurality of bits comprise data bits.

Example 11 is the computer-readable storage medium of example 10, wherein the User Equipment (UE) or evolved node B (eNodeB) comprises the computer-readable storage medium.

Example 12 is the computer-readable storage medium of example 10, wherein the plurality of operations includes an add operation.

Example 13 is the computer-readable storage medium of example 10, wherein each of the plurality of operations comprises: the method includes determining a minimum of absolute values of the first LLR and absolute values of the second LLR, determining a multiplication of the symbols by multiplying the symbols of the first LLR by the symbols of the second LLR, and providing the minimum LLR with the symbols.

Example 14 is the computer-readable storage medium of example 10, wherein the instructions designed to initialize the first plurality of LLRs and initialize the second plurality of LLRs further comprise: instructions to initialize LLRs from the first plurality of LLRs and the second plurality of LLRs associated with frozen bits from the first plurality of bits and the second plurality of bits to predefined values. The computer-readable storage medium of example 10, wherein the instructions designed to initialize the first plurality of LLRs and initialize the second plurality of LLRs further comprise: an instruction to initialize each LLR of the first and second plurality of LLRs associated with a non-frozen bit from the plurality of bits to a sum of received LLRs for a corresponding one of the non-frozen bits, and to initialize LLRs from the first and second plurality of LLRs to zero for non-received bits.

Example 15 is the computer-readable storage medium of example 10, wherein the estimate of the information block includes which codeword was transmitted over a channel.

Example 16 is the computer-readable storage medium of example 10, wherein zero or more of the plurality of bits are associated with polarization-encoded inner bits.

Example 17 is an apparatus for performing polarization encoding. The apparatus includes an electronic memory for storing a plurality of information bits to be encoded by the polar encoder module, the plurality of information bits having a length of K. The apparatus includes one or more processing units configured to select a length S of a shortening bit number and a length P of a puncturing bit number based on a hybrid automatic repeat request (HARQ) scheme, and encode a plurality of information bits via a polarization encoder module to generate a base codeword having a length N minus the shortening bit number. The apparatus includes one or more processing units configured to interleave the results of the polar encoder module via an interleaver module to generate a codeword comprising a base codeword minus shortened bits, minus punctured bits, plus extended bits of length E. The apparatus includes one or more processing units configured to provide the codeword to a modulation module to generate a result of dividing the codeword by a multiplication of a spatial stream number and a number of bits per modulation, and provide the result of the division to a channel of a physical layer to transmit the polarization code to a receiving device.

Example 18 is the apparatus of example 17, wherein the apparatus is one of a User Equipment (UE) or an evolved node B (eNodeB).

Example 19 is the apparatus of example 17, wherein the HARQ scheme comprises chase combining transmissions.

Example 20 is the apparatus of example 17, wherein the HARQ scheme comprises HARQ incremental redundancy (HARQ-IR) transmissions.

Example 21 is the apparatus of example 17, wherein the one or more processing units are further designed to set N toIs 2 (ceil (log 2 (N) _CB ) Where N is _CB Is the length of the codeword and sets E to zero.

Example 22 is the apparatus of example 17, wherein the one or more processing units are further designed to set S to N-N _CB And P is set to zero.

Example 23 is the apparatus of example 17, wherein the one or more processing units are further designed to set S to zero and P to N-N _CB 。

Example 24 is the apparatus of example 17, wherein the one or more processing units are further designed to set N to 2 (floor (log 2 (N) _CB ) Where N is _CB Is the length of the codeword and sets E to N _CB -N。

Example 25 is the apparatus of example 17, wherein the one or more processing units are further designed to set S to zero and P to zero.

Example 26 is a method, comprising: at least a plurality of inner bits are generated in a first stage of the polarization encoder by performing a plurality of operations on a plurality of data bits used in a first stage of the polarization encoder that is different from a second stage of the polarization encoder, wherein the inner bits are inside the polarization encoder. The method further comprises the steps of: a plurality of codeword bits are generated in a second stage of the polarization encoder by performing a plurality of operations on the inner bits, wherein the codeword bits correspond to the second stage of the polarization encoder and the inner bits correspond to the first stage of the polarization encoder. The method further comprises the steps of: for hybrid automatic repeat request (HARQ) transmissions, a subset of the data bits, codeword bits, and inner bits are provided to a channel of a physical layer.

Example 27 is the method of example 26, wherein providing includes providing, by an apparatus of a User Equipment (UE), a channel of a physical layer with a subset of data bits, codeword bits, and inner bits, and wherein the channel is at least one of an uplink channel and a side chain channel.

Example 28 is the method of example 26, wherein providing includes providing, by an apparatus of an evolved user node (eNodeB), a channel comprising a subset of data bits, codeword bits, and inner bits to a physical layer, and wherein the channel is at least one of a downlink channel.

Example 29 is the method of example 26, wherein the HARQ transmission is at least one of a chase combining HARQ transmission and a HARQ incremental redundancy (HARQ-IR) transmission.

Example 30 is the method of example 26, wherein the data bits for the first stage of the polar encoder comprise bits set to a predetermined value.

Example 31 is the method of example 26, wherein the length of the data bits, the length of the inner bits, and the length of the codeword bits are the same length.

Example 32 is the method of example 26, further comprising generating a subsequent HARQ transmission comprising a subsequent subset of data bits, inner bits, and codeword bits, the subsequent subset different from the subset of data bits, inner bits, and codeword bits.

Example 33 is the method of example 26, wherein the HARQ transmission includes a circular buffer of data bits, inner bits, and a subset of codeword bits.

Example 34 is the method of example 26, wherein the subset of data bits, inner bits, and codeword bits comprises one of: codeword bits and inner bits, a portion of inner bits and codeword bits, and an inner bit.

Example 35 is a method, comprising: a first plurality of log-likelihood ratios (LLRs) of a plurality of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request (HARQ) transmission are initialized. The method further comprises the steps of: a second plurality of LLRs for a plurality of hanging edges of the polar decoder associated with the plurality of bits is initialized. The method further comprises the steps of: a plurality of operations is performed on the first plurality of LLRs and the second plurality of LLRs to generate a third plurality of LLRs. The method further comprises the steps of: an estimate of an information block comprising a first plurality of bits and a second plurality of bits is determined based on the third plurality of LLRs, wherein the first plurality of bits and the second plurality of bits comprise data bits.

Example 36 is the method of example 35, wherein initializing the plurality of LLRs, initializing the second plurality of LLRs, performing the plurality of operations, and determining the estimate of the information block is performed by a User Equipment (UE) or an evolved node B (eNodeB).

Example 37 is the method of example 35, wherein the plurality of operations includes an add operation.

Example 38 is the method of example 35, wherein each of the plurality of operations comprises: a minimization operation of a minimum LLR of the absolute values of the first LLR and the absolute values of the second LLR is determined. The plurality of operations includes determining a multiplication operation of a symbol by multiplying a symbol of a first LLR by a symbol of a second LLR and providing a minimum LLR having the symbol.

Example 39 is the method of example 35, wherein initializing the first plurality of LLRs and initializing the second plurality of LLRs further comprises: instructions to initialize LLRs from the first plurality of LLRs and the second plurality of LLRs associated with frozen bits from the first plurality of bits and the second plurality of bits to predefined values. Initializing the first plurality of LLRs and initializing the second plurality of LLRs further comprises: each LLR of the first and second plurality of LLRs associated with a non-frozen bit from the plurality of bits is initialized to a sum of received LLRs for a corresponding one of the non-frozen bits, and LLRs from the first and second plurality of LLRs are initialized to zero for non-received bits.

Example 40 is the method of example 35, wherein the estimation of the information block includes which codeword is transmitted over a channel.

Example 41 is the method of example 35, wherein zero or more of the plurality of bits are associated with polarization encoded inner bits.

Example 42 is a method. The method includes an electronic memory for storing a plurality of information bits to be encoded by the polar encoder module, the plurality of information bits having a length of K. The method further comprises one or more processing units designed to select a length S of the shortening bits and a length P of the puncturing bits based on a hybrid automatic repeat request (HARQ) scheme. The method further includes one or more processing units configured to encode the plurality of information bits via the polar encoder module to generate a base code having a length N minus the shortened number of bits. The method further includes one or more processing units configured to interleave the results of the polar encoder module via the interleaver module to generate a codeword comprising a base codeword minus shortened bits, minus punctured bits, plus an extended bit of length E. The method further comprises one or more processing units designed to provide the codeword to the modulation module to generate a result of dividing the codeword by a multiplication of the spatial stream number and the number of bits per modulation, and to provide the result of the division to a channel of the physical layer to transmit the polarization code to the receiving device.

Example 43 is the method of example 42, wherein the HARQ scheme comprises chase combining transmissions.

Example 44 is the method of example 42, wherein the HARQ scheme comprises HARQ incremental redundancy (HARQ-IR) transmissions.

Example 45 is the method of example 42, further comprising setting N to 2 (ceil (log 2 (N) _CB ) Where N is _CB Is the length of the codeword and sets E to zero.

Embodiment 46 is the method of embodiment 42, further comprising setting S to N-N _CB And P is set to zero.

Example 47 is the method of example 42, further comprising setting S to zero and P to N-N _CB 。

Example 48 is the method of example 42, further comprising setting N to be 2 (floor (log 2 (N) _CB ) Where N is _CB Is the length of the codeword and sets E to N _CB -N。

Example 49 is the method of example 42, further comprising setting S to zero and setting P to zero.

Example 50 is at least one computer-readable storage medium having stored thereon computer-readable instructions that, when executed, implement the method of any of examples 26-44.

Embodiment 51 is an apparatus comprising means for performing the method of any one of examples 26-44.

Embodiment 52 is an apparatus to perform the method of any one of examples 26-44.

The various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, non-transitory computer-readable storage medium, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques. In the case of program code execution on programmable computers, the computing device can include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. The volatile and nonvolatile memory and/or storage elements may be RAM, EPROM, flash memory drive, optical drive, magnetic hard drive, or another medium for storing electronic data. The eNodeB (or other base station) and the UE (or other mobile station) may also include a transceiver component, a counter component, a processing component, and/or a clock component or timer component. One or more programs that may implement or utilize the various techniques described herein may use an Application Programming Interface (API), reusable controls, or the like. Such programs may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations.

It should be understood that many of the functional units described in this specification can be implemented as one or more components, which are terms used to more emphasize their implementation independence. For example, a component may be implemented as a hardware circuit comprising custom Very Large Scale Integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors (e.g., logic chips), transistors, or other discrete components. Components may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.

Components may also be implemented in software for execution by various types of processors. For example, an identified component of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. However, the executables of an identified component need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the component and achieve the stated purpose for the component.

Indeed, a component of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified or illustrated herein within components, and may be embodied in any suitable form or organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices. The components may be passive or active, including agents operable to perform desired functions.

Reference throughout this specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment. Thus, the appearances of the phrase "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment.

As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be considered that each member of the list is individually identified as a separate and unique member. Thus, any individual member of such list should not be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. Further, various embodiments and examples, as well as alternatives to their various components, may be referred to herein. It should be understood that such embodiments, examples, and alternatives are not to be considered as physically equivalent to each other, but are to be considered as separate and independent representations of the embodiments.

Although the foregoing has been described in some detail for purposes of clarity, it will be apparent that certain changes and modifications may be practiced without departing from the principles thereof. It should be noted that there are many alternative ways of implementing the processes and apparatuses described herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims (9)

1. A method of polarization decoding, comprising:

initializing a first plurality of log-likelihood ratios LLRs for a plurality of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request, HARQ, transmission;

initializing a second plurality of LLRs for a plurality of hanging edges of the polar decoder associated with the plurality of bits;

performing a plurality of operations on the first plurality of LLRs and the second plurality of LLRs to generate a third plurality of LLRs; and

an estimate of an information block comprising a first plurality of bits and a second plurality of bits, the first plurality of bits and the second plurality of bits comprising data bits, is determined based on the third plurality of LLRs.

2. The method of claim 1, wherein initializing the first plurality of LLRs, initializing the second plurality of LLRs, performing the plurality of operations, and determining an estimate of the information block is performed by a User Equipment (UE) or an evolved node B (eNodeB).

3. The method of claim 1, wherein the plurality of operations comprises an add operation.

4. The method of claim 1, wherein each of the plurality of operations comprises:

a minimization operation for determining a minimum LLR of the absolute values of the first LLR and the absolute values of the second LLR;

A multiplication operation for determining a symbol by multiplying a symbol of the first LLR by a symbol of the second LLR; and

the minimum LLR with the symbol is provided.

5. The method of claim 1, wherein initializing the first plurality of LLRs and initializing the second plurality of LLRs further comprises:

initializing LLRs from the first plurality of LLRs and the second plurality of LLRs associated with frozen bits from the first plurality of bits and the second plurality of bits to predefined values;

initializing each LLR of the first and second plurality of LLRs associated with a non-frozen bit from the plurality of bits to a sum of received LLRs for a corresponding one of the non-frozen bits; and is also provided with

For bits that are not received, LLRs from the first plurality of LLRs and the second plurality of LLRs are initialized to zero.

6. The method of claim 1, 2, 3, 4 or 5, wherein the estimation of an information block comprises which codeword is transmitted over the channel.

7. The method of claim 1, 2, 3, 4, or 5, wherein zero or more bits of the plurality of bits are associated with polarization-encoded inner bits.

8. An apparatus for performing the method of any one of claims 1-7.

9. At least one computer readable storage medium having stored thereon computer readable instructions which when executed implement the method of any of claims 1-7.