CN114678371B - IO device structure and preparation method thereof - Google Patents
IO device structure and preparation method thereof Download PDFInfo
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- CN114678371B CN114678371B CN202210596098.6A CN202210596098A CN114678371B CN 114678371 B CN114678371 B CN 114678371B CN 202210596098 A CN202210596098 A CN 202210596098A CN 114678371 B CN114678371 B CN 114678371B
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/47—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
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Abstract
The invention provides an IO device structure and a preparation method thereof, wherein the IO device structure comprises a first conduction type substrate, a second conduction type deep well region, two first grooves with preset distance intervals, a second groove, an isolation layer, a grid structure, a first conduction type doping region and a second conduction type doping region, wherein the deep well region is positioned in the substrate; the first trench is positioned in the deep well region; at least two second grooves which are separated by a preset distance are positioned between the two first grooves; the isolation layer fills the first trench and the second trench; the grid structure is positioned on the upper surface of the substrate between two adjacent second substrates and comprises a tunneling layer, a floating grid layer, a first dielectric layer, a grid layer and an isolation side wall; the first conductive type doping area and the second conductive type doping area are respectively positioned on the upper surface layer of the substrate between the adjacent grid structure and the second groove and between the first groove and the second groove. According to the invention, the thin tunneling layer is arranged in the gate structure, so that the power consumption of the device is reduced, and the reading operation speed of the device is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to an IO device structure and a preparation method thereof.
Background
Generally, Core devices (Core devices) and input/output devices (IO devices, also called IO devices) are used in design of Embedded Flash (EMB Flash for short), some EMB Flash does not have high requirements for IO devices, and in order to save cost, a high-voltage device is used instead of an IO device, so that 5 photolithography masks can be saved, namely an N-well photolithography mask, a P-well photolithography mask, a dual-gate photolithography mask, an N-type low-doping photolithography mask and a P-type doping photolithography mask. However, the use of high voltage devices instead of IO devices is slow (about 50 ns) and consumes a lot of power (about 200 μ a/MHz).
Therefore, an IO device structure for increasing the read operation speed and reducing the power consumption is urgently needed.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide an IO device structure and a method for manufacturing the IO device structure, which are used to solve the problems of slow read operation speed and large power consumption of the prior art in which a high voltage device replaces an IO device.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing an IO device, including the following steps:
providing a first conductive type substrate, and forming a second conductive type deep well region on the substrate;
forming two first trenches with upward openings and arranged at intervals in the deep well region to obtain an IO device region located between the two first trenches and core device regions located on two sides of the IO device region, wherein the IO device region is isolated from the core device regions by the first trenches;
forming at least two second trenches with upward openings and arranged at intervals with the first trenches between the two first trenches, and forming isolation layers in the first trenches and the second trenches;
forming a laminated structure comprising a tunneling layer, a first conductive type floating gate layer, a first dielectric layer and a gate electrode layer on the upper surface of the substrate between two adjacent second grooves, forming an isolation side wall covering the side wall of the laminated structure on the side wall of the laminated structure to obtain a gate electrode structure, wherein the gate electrode structure is spaced from the second grooves by a preset distance, and the gate electrode layer is electrically connected with the floating gate layer;
and forming first conductive type doped regions on the upper surface layer of the IO device region between the second groove and the gate structure on two sides of the gate structure, and forming second conductive type doped regions on the upper surface layer of the IO device region between the adjacent first groove and the second groove.
Optionally, the first trench is formed simultaneously with the second trench.
Optionally, at least one high voltage device is formed in the core device region.
Optionally, after forming the second trench, before forming the tunneling layer, the method further includes forming a second dielectric layer on the upper surface of the substrate and performing at least one second conductive type doping in the substrate.
Optionally, after the doping of the second conductivity type in the substrate, before the forming of the tunneling layer, a step of removing the second dielectric layer on the upper surface of the IO device region is further included.
Optionally, after forming the first dielectric layer, before forming the gate layer, a step of forming a via penetrating through the first dielectric layer in the first dielectric layer is further included, and the gate layer is further filled in the via to be in electrical contact with the floating gate layer.
The present invention also provides an IO device, including:
a first conductive type substrate;
a second conductivity type deep well region in the substrate;
the two first grooves are arranged in the deep well region at a preset distance interval, and divide the substrate into an IO device region arranged between the two first grooves and core device regions arranged on two sides of the IO device region;
the second grooves are positioned between the two first grooves and are spaced from the first grooves by a preset distance;
an isolation layer filling the first trench and the second trench;
the grid structure is positioned on the upper surface of the substrate between two adjacent second grooves and is spaced from the second grooves at two sides by a preset distance, the grid structure comprises a laminated structure consisting of a tunneling layer, a floating grid layer, a first dielectric layer and a grid layer which are sequentially stacked upwards and an isolation side wall covering the side wall of the laminated structure, and the grid layer is electrically connected with the floating grid layer;
the gate structure comprises a gate structure, a gate device region, a gate structure, a first conductive type doped region and a second conductive type doped region, wherein the first conductive type doped region is located on an upper surface of the IO device region between the gate structure and the second groove, and the second conductive type doped region is located on an upper surface of the IO device region between the first groove and the second groove.
Optionally, a thickness range of the tunneling layer is 80A-100A, and a thickness range of the first dielectric layer is 120A-180A.
Optionally, a via hole penetrating at least the first dielectric layer is further disposed in the first dielectric layer, and the gate layer is filled in the via hole to be in electrical contact with the floating gate layer.
Optionally, the doping concentration of the second conductivity type doped region is higher than the doping concentration of the deep well region.
As described above, according to the IO device structure and the manufacturing method thereof of the present invention, after the IO device region and the core device region are formed in the substrate, a second dielectric layer is formed on the upper surface of the substrate, and at least one second conductive type ion implantation step is performed on the substrate, so as to adjust and control the threshold voltage of the IO device formed in the core device region and the core device formed in the IO device region; and removing the second dielectric layer of the IO device region, forming a tunneling layer which is arranged between the second grooves and has a preset distance with the second grooves on the upper surface of the IO device region, wherein the thickness of the tunneling layer is thinner, so that the reading operation speed of the IO device is improved, and the power consumption of the IO device is obviously reduced. In addition, the IO device preparation process steps are compatible with the core device preparation process steps, so that the process steps are simplified, the cost is reduced, and the method has high industrial utilization value.
Drawings
Fig. 1 shows a process flow diagram of a method for manufacturing an IO device according to the present invention.
Fig. 2 is a schematic cross-sectional view illustrating a first conductive type deep well region formed by the IO device manufacturing method of the present invention.
Fig. 3 is a schematic cross-sectional view illustrating a cross-sectional structure of an IO device after forming an isolation layer according to a method of the present invention.
Fig. 4 is a schematic cross-sectional view of a stacked structure formed by the IO device manufacturing method according to the present invention.
Fig. 5 is a schematic cross-sectional view illustrating a gate structure formed by the IO device manufacturing method of the present invention.
Fig. 6 is a schematic cross-sectional structure diagram of an IO device manufactured by the IO device manufacturing method of the present invention.
Element number description: the semiconductor device comprises a substrate 1, a deep well region 11, a first trench 111, a device region 12 IO, a second trench 121, an isolation layer 13, a gate structure 14, a tunneling layer 141, a floating gate layer 142, a first dielectric layer 143, a through hole 1431, a gate layer 144, an isolation spacer 145, a doped region 15 of a first conductivity type, and a doped region 16 of a second conductivity type.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The embodiment provides a method for manufacturing an IO device, as shown in fig. 1, which is a process flow diagram of the method for manufacturing an IO device, and includes the following steps:
s1: providing a first conduction type substrate, and forming a second conduction type deep well region on the substrate;
s2: forming two first trenches with upward openings and arranged at intervals in the deep well region to obtain an IO device region located between the two first trenches and core device regions located on two sides of the IO device region, wherein the IO device region and the core device regions are isolated by the first trenches;
s3: forming two second trenches with upward openings and arranged at intervals with the first trenches between the two first trenches, and forming isolation layers in the first trenches and the second trenches;
s4: forming a laminated structure comprising a tunneling layer, a first conductive type floating gate layer, a first dielectric layer and a gate electrode layer on the upper surface of the substrate between two adjacent second grooves, forming an isolation side wall covering the side wall of the laminated structure on the side wall of the laminated structure to obtain a gate electrode structure, wherein the gate electrode structure is separated from the second grooves by a preset distance, and the gate electrode layer is electrically connected with the floating gate layer;
s5: and forming first conductive type doped regions which are positioned between the second grooves and the grid structure and positioned on the upper surface layer of the IO device region on two sides of the grid structure, and forming second conductive type doped regions on the upper surface layer of the IO device region between the adjacent first grooves and the second grooves.
Referring to fig. 2, the step S1 is executed: a first conductive type substrate 1 is provided, and a second conductive type deep well region 11 is formed on the substrate 1.
Specifically, the first conductive type includes one of an N type or a P type, the second conductive type includes one of an N type or a P type, and the first conductive type is opposite to the second conductive type.
Specifically, the material of the substrate 1 includes silicon or other suitable semiconductor material. In this embodiment, the substrate 1 is P-type silicon.
In particular, the size of the substrate 1 may be set according to practical situations, and is not limited here.
Specifically, the forming of the deep well region further includes the following steps: forming a first photoresist layer on the upper surface of the substrate, and patterning the first photoresist layer; the deep well region 11 is formed on the basis of the patterned first photoresist layer.
Specifically, the method for forming the deep well region 11 includes ion implantation or other suitable methods. In this embodiment, an ion implantation method is adopted to form a doped region of the deep well region 11 in the substrate 1, and an annealing step is further included after the substrate 1 is doped with the second conductivity type, so as to perform a well-pushing operation on the doped region, and then form the deep well region 11.
Referring back to fig. 3, the steps S2 and S3 are executed: forming two first trenches 111 with upward openings and arranged at intervals in the deep well region 11 to obtain an IO device region 12 located between the two first trenches 111 and a core device region (not shown) located at two sides of the IO device region 12, wherein the IO device region 12 and the core device region are isolated by the first trenches 111; two second trenches 121 with upward openings and spaced apart from the first trenches 111 are formed between the two first trenches 111, and an isolation layer 13 is formed in the first trenches 111 and the second trenches 121.
As an example, the first trench 111 is formed in synchronization with the second trench 121.
Specifically, the step of forming the first trench 111 and the second trench 121 includes: forming a second photoresist layer on the upper surface of the substrate 1, and patterning the second photoresist layer; the first trench 111 and the second trench 121 are formed based on the patterned second photoresist layer.
Specifically, the method for forming the first trench 111 and the second trench 121 includes wet etching, dry etching, or other suitable methods.
Specifically, the first trench 111 is formed to obtain the IO device region 12, and the IO device region 12 is separated from the core device region.
As an example, at least one high voltage device is formed in the core device region.
Specifically, the IO device prepared in the IO device region 12 and the core device prepared in the core device region are prepared simultaneously.
Specifically, the second trench 121 is formed to obtain an active region of an IO device in the IO device region 12.
Specifically, the material of the isolation layer 13 includes silicon dioxide, silicon nitride, or other suitable high dielectric material.
Specifically, the method for forming the isolation layer 13 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. In this embodiment, the isolation layer 13 is formed by chemical vapor deposition.
Specifically, the upper surface of the isolation layer 13 is flush with the upper surface of the substrate 1.
Referring to fig. 4 to 5, the step S4 is executed: a stacked structure including a tunneling layer 141, a first conductive type floating gate layer 142, a first dielectric layer 143, and a gate layer 144 is formed on the upper surface of the substrate 1 between two adjacent second trenches 121, and an isolation sidewall 145 covering the sidewall of the stacked structure is formed on the sidewall of the stacked structure to obtain a gate structure 14, the gate structure 14 is spaced from the second trenches 121 by a predetermined distance, and the gate layer 144 is electrically connected to the floating gate layer 142.
As an example, after forming the second trench 121 and before forming the tunneling layer 141, the method further includes forming a second dielectric layer (not shown) on the upper surface of the substrate 1 and doping the substrate with the second conductive type at least one time.
Specifically, the method for forming the second dielectric layer includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, after the second dielectric layer is formed and before the tunneling layer 141 is formed, at least one second conductive type doping is performed in the substrate 1 to adjust and control the threshold voltage of the high-voltage device and the threshold voltage of the IO device.
In particular, the method for doping the substrate 1 with the second conductivity type includes ion implantation or other suitable methods.
Specifically, the doping concentration and the doping depth of the second conductivity type to the substrate 1 may be adjusted according to the requirement of the threshold voltage of the device, and are not limited herein.
As an example, after doping the second conductive type in the substrate 1, a step of removing the second dielectric layer on the upper surface of the IO device region 12 is further included before forming the tunneling layer 141.
Specifically, the removing the second dielectric layer on the upper surface of the IO device region 12 includes the following steps: forming a third photoresist layer on the upper surface of the substrate, and patterning the third photoresist layer to expose the upper surface of the IO device region 12; removing the second dielectric layer based on the patterned third photoresist layer.
Specifically, the method for removing the second dielectric layer includes wet etching or other suitable methods. In this embodiment, the second dielectric layer is removed by using an HF solution (one of wet etching).
Specifically, as shown in fig. 4 and 5, which are a schematic cross-sectional structure diagram after forming a stacked structure and a schematic cross-sectional structure diagram after forming the gate structure 14, respectively, the method for forming the gate structure 14 includes the following steps: sequentially forming a tunneling material layer, a floating gate material layer, a first dielectric material layer and a gate conductive layer on the second dielectric layer and the upper surface of the IO device region 12; forming a fourth photoresist layer on the upper surface of the gate conducting layer, and patterning the fourth photoresist layer; removing the excess tunneling material layer, the floating gate material layer, the first dielectric material layer and the gate conductive layer above the IO device region 12 based on the patterned fourth photoresist layer to obtain a stacked structure including the tunneling layer 141, the floating gate layer 142, the first dielectric layer 143 including the via 1431 and the gate layer 144; forming an isolation material layer covering the exposed surface of the stacked structure, removing the isolation material layer on the upper surface of the stacked structure, exposing the gate layer 144 to obtain the isolation sidewall 145, and then obtaining the gate structure 14 including the tunneling layer 141, the floating gate layer 142, the first dielectric layer 143, the gate layer 144, and the isolation sidewall 145.
Specifically, the formed second dielectric layer and the tunneling layer 141 on the upper surface of the second dielectric layer are commonly used as a high voltage resistant dielectric layer of a high voltage device in the core device region.
Specifically, the method for forming the tunneling material layer includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods.
Specifically, the tunneling material layer is made of silicon oxide or other suitable dielectric materials.
Specifically, the method for forming the floating gate material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
Specifically, the material of the floating gate material layer includes first conductivity type polysilicon, and may be other suitable materials.
Specifically, the thickness of the floating gate material layer formed may be selected according to actual conditions, and is not limited herein.
Specifically, the method for forming the first dielectric material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
Specifically, the material of the first dielectric material layer includes one of silicon oxide and silicon nitride, and may be other suitable dielectric materials.
As an example, after forming the first dielectric layer 143, before forming the gate layer 144, a step of forming a via 1431 penetrating the first dielectric layer 143 in the first dielectric layer 143 is further included, and the gate layer 144 is further filled in the via 1431 to be electrically contacted with the floating gate layer 142.
Specifically, the step of forming the through hole 1431 includes the following steps: forming a fifth photoresist layer on the upper surface of the first dielectric material layer, and patterning the fifth photoresist layer; based on the patterned fifth photoresist layer, the through hole 1431 penetrating at least the first dielectric material layer is formed in the first dielectric material layer.
Specifically, when the via 1431 penetrates through the first dielectric material layer and extends into the floating gate material layer, the extending depth of the via 1431 in the floating gate material layer can be selected according to practical situations under the condition that the via 1431 does not penetrate through the floating gate material layer, and is not limited herein.
Specifically, the method for forming the through hole 1431 includes one of wet etching and dry etching, and may be another suitable method.
Specifically, the gate conductive layer fills the via 1431 and covers the upper surface of the first dielectric material layer, so that the gate layer 144 is electrically connected to the floating gate layer 142.
Specifically, in the case of ensuring that the gate conductive layer can be filled into the through hole 1431 and electrically connected to the floating gate layer 142, the cross-sectional size of the through hole 1431 may be selected according to practical situations, and is not limited herein.
Specifically, the gate conductive layer is made of a first conductive type polysilicon, and may be made of other suitable conductive materials.
Specifically, the method for removing the excessive tunneling material layer, the floating gate material layer, the first dielectric material layer and the gate conductive layer on the upper surface of the IO device region 12 includes wet etching or other suitable methods.
Specifically, the method for forming the isolation material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
Specifically, the material of the isolation material layer includes silicon oxide, silicon nitride, or other suitable dielectric materials.
Referring back to fig. 6, the step S5 is executed: first conductive type doped regions 15 located on the upper surface layer of the IO device region 12 between the second trench 121 and the gate structure 14 are formed on two sides of the gate structure 14, and second conductive type doped regions 16 are formed on the upper surface layer of the IO device region 12 between the adjacent first trench 111 and the second trench 121.
Specifically, the method for forming the first conductive-type doped region 15 includes ion implantation or other suitable methods. In this embodiment, the first conductive type doped region 15 is formed by using the isolation sidewall 145 as a mask and using an ion implantation method.
Specifically, the method for forming the second conductive type doped region 16 includes ion implantation or other suitable methods.
Specifically, the first conductive type doped region 15 and the second conductive type doped region 16 are heavily doped.
Specifically, after the first conductive-type doped region 15 and the second conductive-type doped region 16 are formed, a well region electrode electrically connected to the second conductive-type doped region 16, a source electrically connected to the first conductive-type doped region 15 on one side of the gate structure 14, a drain electrically connected to the opposite side of the source on one side of the gate structure 14, and a gate electrically connected to the gate layer 144 are further formed.
Specifically, the formed well region electrode is combined with the gate to control the opening of the conductive channel of the IO device region under the gate structure 14, and then the operation of the IO device is controlled by the cooperation of the source and the drain.
Specifically, the IO device is formed in the IO device region 12 and the core device is formed in the core device region simultaneously, and the process steps are compatible, so that the process steps are simplified, and the manufacturing cost of the device is reduced.
In the method for manufacturing an IO device according to this embodiment, the substrate 1 is separated into the IO device region 12 and the core device region by the first trench 111 and the isolation layer 13, a second dielectric layer is formed on the upper surface of the substrate 1, and at least one second conductive type ion implantation is performed to adjust and control the threshold voltage of the core device formed in the core device region and the IO device formed in the IO device region 12; removing the second dielectric layer of the IO device region 12, forming the gate structure 14 between the second trenches 121 and spaced from the second trenches 121 by a predetermined distance, where the gate structure 14 includes a stack structure of the tunneling layer 141, the floating gate layer 142, the first dielectric layer 143, and the gate layer 144 stacked on the upper surface of the substrate 1 in sequence, and the isolation sidewall 145 covering the sidewall of the stack structure, so that the gate structure 14 of the IO device is compatible with a forming process of the core device, a forming process is simplified, and a manufacturing cost is saved.
Example two
The present embodiment provides an IO device structure, as shown in fig. 6, which is a schematic cross-sectional structure diagram of the IO device structure, including: the semiconductor device comprises a first conduction type substrate 1, a second conduction type deep well region 11, a first trench 111, a second trench 121, an isolation layer 13, a gate structure 14, a first conduction type doped region 15 and a second conduction type doped region 16, wherein the deep well region 11 is located in the substrate 1; two first trenches 111 spaced by a preset distance are located in the deep well region 11, and the substrate 1 is divided into an IO device region 12 located between the two first trenches 111 and core device regions located at two sides of the IO device region 12 by the first trenches 111; at least two second grooves 121 spaced apart by a predetermined distance are located between the two first grooves 111, and a predetermined distance is spaced between the second grooves 121 and the first grooves 111; the isolation layer 13 fills the first trench 111 and the second trench 121; the gate structure 14 is located on the upper surface of the substrate 1 between two adjacent second trenches 121 and is spaced from the second trenches 121 at two sides by a preset distance, the gate structure 14 includes a stacked structure composed of a tunneling layer 141, a floating gate layer 142, a first dielectric layer 143 and a gate layer 144, which are stacked in sequence upward, and an isolation sidewall 145 covering sidewalls of the stacked structure, and the gate layer 144 is electrically connected to the floating gate layer 142; the first conductive type doped region 15 is located on an upper surface of the IO device region between the gate structure 14 and the second trench 121, and the second conductive type doped region 16 is located on an upper surface of the IO device region between the first trench 111 and the second trench 121.
Specifically, the depth of the deep well region 11 may be selected according to practical situations, and is not limited herein.
Specifically, the area of the deep well region 11 may be set according to practical situations, and is not limited here.
Specifically, the depth of the first trench 111 extending to the substrate 1 and the size of the opening of the first trench 111 may be determined according to practical situations, and are not limited herein.
Specifically, the depth of the second trench 121 extending to the substrate 1 and the opening size of the second trench 121 may be determined according to practical situations, and are not limited herein.
Specifically, the spacing distance between the adjacent first grooves 111 and the adjacent second grooves 121 may be set according to practical situations, and is not limited herein.
Specifically, the spacing distance between two adjacent second grooves 121 may be set according to practical situations, and is not limited here.
As an example, the thickness range of the tunneling layer 141 is 80A-100A to reduce the read power consumption of the IO device. In this embodiment, the thickness of the tunneling layer 141 is 90 a.
As an example, the first dielectric layer 143 has a thickness in a range of 120A-180A to correspond to a structure of the high voltage device, reducing process steps to fabricate the IO device and the core device simultaneously. In this embodiment, the thickness of the first dielectric layer 143 is 150 a
Specifically, a via 1431 penetrating at least the first dielectric layer 143 is further provided in the first dielectric layer 143, and the gate layer 144 is filled in the via 1431 to be in electrical contact with the floating gate layer, that is, the conductive material of the gate layer 144 is filled in the via 1431, so that the floating gate layer 142 is electrically connected to the gate layer 144.
Specifically, the thickness of the isolation sidewall 145 may be set according to actual conditions, and is not limited here.
Specifically, the spacing distance between the gate structure 14 and the second trench 121 on both sides of the gate structure 14 may be set according to practical situations, and is not limited herein.
As an example, the doping concentration of the second conductivity type doping region 16 is higher than the doping concentration of the deep well region 11 so that the second conductivity type doping region 16 forms an ohmic contact with a well region electrode electrically connected to the second conductivity type doping region 16, and the power consumption of the device is reduced.
Specifically, the second-conductivity-type-doped 16 region and the gate layer 144 are electrically connected to corresponding electrodes, respectively, and then control the opening and closing of the conductive channel in the deep well region 11 together.
Specifically, the first conductive type doped region 15 is heavily doped, and ohmic contact is formed between the first conductive type doped region 15 and a metal electrode electrically connected with the first conductive type doped region 15, so that power consumption of the device is reduced.
Specifically, the first conductive type doped regions 15 on two sides of the gate structure 14 are a source region and a drain region of the IO device, respectively.
Specifically, by adopting the tunneling layer 141 with the thickness in the above range, the current driving capability of the IO device is improved, the reading power consumption of the IO device is significantly reduced from about 200 μ a/MHz to less than 150 μ a/MHz, and the reading speed of the IO device is also improved from about 50 ns to less than 35 ns.
The IO device structure of this embodiment, through right IO device structural design, IO device structure with the technology of high voltage device is compatible in the core device, has simplified preparation technology, and adopts thinly tunnel layer 141 is as the withstand voltage gate dielectric layer of device, is showing the consumption that has reduced the device, has promoted the read operation speed of device.
In summary, in the IO device structure and the method for manufacturing the IO device structure of the present invention, by designing the structure of the IO device, the first conductive deep well region is formed on the substrate, the substrate is divided into the core device region and the IO device region located in the deep well region by the first trench, the second dielectric layer is formed on the substrate, and at least one second conductive ion implantation step is performed on the substrate to adjust the threshold voltage of the core device and the IO device, remove the second dielectric layer on the upper surface of the IO device region, and sequentially form the gate structure including the thin tunneling layer, the floating gate layer, the first dielectric layer, the gate layer, and the isolation sidewall, so that the steps of the IO device manufacturing process are compatible with the steps of the IO device manufacturing process of the core device matched with the IO device, thereby simplifying the manufacturing process and reducing the manufacturing cost; in addition, the thin tunneling layer replaces the high-voltage second dielectric layer, so that the power consumption of the IO device is reduced, and the reading operation speed of the IO device is increased. Therefore, the present invention effectively overcomes various disadvantages of the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. The preparation method of the IO device is characterized by comprising the following steps of:
providing a first conductive type substrate, and forming a second conductive type deep well region on the substrate;
forming two first trenches with upward openings and arranged at intervals in the deep well region to obtain an IO device region located between the two first trenches and core device regions located on two sides of the IO device region, wherein the IO device region and the core device regions are isolated by the first trenches;
forming at least two second trenches with upward openings and arranged at intervals with the first trenches between the two first trenches, and forming isolation layers in the first trenches and the second trenches;
forming a second dielectric layer on the upper surface of the substrate, performing at least one time of second conductivity type doping on the upper surface of the substrate to regulate and control the threshold voltage of a high-voltage device and the threshold voltage of an IO device, and removing the second dielectric layer on the upper surface of the IO device area, wherein the second dielectric layer is used for the high-voltage dielectric layer of the high-voltage device;
forming a stacked structure including a tunneling layer, a first conductive type floating gate layer, a first dielectric layer, and a gate layer on an upper surface of the substrate between two adjacent second trenches, and forming isolation sidewalls on sidewalls of the stacked structure to cover sidewalls of the stacked structure to obtain a gate structure, wherein the gate structure is spaced from the second trenches by a predetermined distance, the gate layer is electrically connected to the floating gate layer, and a thickness range of the tunneling layer is 80 a to 100 a;
and forming first conductive type doped regions which are positioned between the second grooves and the grid structure and positioned on the upper surface layer of the IO device region on two sides of the grid structure, and forming second conductive type doped regions on the upper surface layer of the IO device region between the adjacent first grooves and the second grooves.
2. The method for manufacturing an IO device according to claim 1, wherein: the first trench is formed in synchronization with the second trench.
3. The method for manufacturing an IO device according to claim 1, wherein: and forming at least one high-voltage device in the core device area.
4. The method for manufacturing an IO device according to claim 1, wherein: after the first dielectric layer is formed and before the gate layer is formed, a step of forming a through hole penetrating through the first dielectric layer in the first dielectric layer is further included, and the gate layer is further filled in the through hole to be in electrical contact with the floating gate layer.
5. An IO device structure, characterized in that the IO device structure is prepared by the method for preparing an IO device according to any one of claims 1 to 4, and the method comprises:
a first conductive type substrate;
a second conductivity type deep well region in the substrate;
the two first grooves are spaced at a preset distance and are positioned in the deep well region, and the substrate is divided into an IO device region positioned between the two first grooves and core device regions positioned on two sides of the IO device region;
the second grooves are positioned between the two first grooves and are spaced from the first grooves by a preset distance;
an isolation layer filling the first trench and the second trench;
the grid structure is positioned on the upper surface of the substrate between two adjacent second grooves and is spaced from the second grooves at two sides by a preset distance, the grid structure comprises a laminated structure consisting of a tunneling layer, a floating grid layer, a first dielectric layer and a grid layer which are sequentially stacked upwards and an isolation side wall covering the side wall of the laminated structure, and the grid layer is electrically connected with the floating grid layer;
the gate structure comprises a gate structure, a gate device region, a gate structure, a first conductive type doped region and a second conductive type doped region, wherein the first conductive type doped region is located on an upper surface of the IO device region between the gate structure and the second groove, and the second conductive type doped region is located on an upper surface of the IO device region between the first groove and the second groove.
6. The IO device structure of claim 5, wherein: the thickness range of the first dielectric layer is 120A-180A.
7. The IO device structure of claim 5, wherein: the first dielectric layer is also provided with a through hole at least penetrating through the first dielectric layer, and the grid layer is filled in the through hole to be electrically contacted with the floating grid layer.
8. The IO device structure of claim 5, wherein: the doping concentration of the second conduction type doping area is higher than that of the deep well area.
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