CN114678282B

CN114678282B - Bonding compensation method and device, chip rewiring method and bonding structure

Info

Publication number: CN114678282B
Application number: CN202210586382.5A
Authority: CN
Inventors: 田应超; 刘天建; 宋林杰; 王逸群; 任小宁
Original assignee: Hubei 3d Semiconductor Integrated Innovation Center Co ltd; Hubei Jiangcheng Laboratory
Current assignee: Hubei 3d Semiconductor Integrated Innovation Center Co ltd; Hubei Jiangcheng Laboratory
Priority date: 2022-05-27
Filing date: 2022-05-27
Publication date: 2022-08-02
Anticipated expiration: 2042-05-27
Also published as: CN114678282A; WO2023226350A1

Abstract

The embodiment of the application provides a bonding compensation method and device, a chip rewiring method and a bonding structure. The compensation method comprises the following steps: providing at least one wafer, wherein a plurality of chips are bonded on the wafer; determining the target position of each chip according to the actual bonding position and the preset bonding position of each chip on the wafer; wherein the offset parameter between the target position and the predetermined bonding position of each of the chips is the same; for each of the chips on the wafer: determining a setting position of at least one first rewiring layer to be formed on the chip according to the actual bonding position and the target position; wherein a setup position of a top first rerouting layer of the at least one first rerouting layer is the same as the target position.

Description

Bonding compensation method and device, chip rewiring method and bonding structure

Technical Field

The embodiment of the application relates to the technical field of semiconductor manufacturing, in particular to a bonding compensation method and device, a chip rewiring method and a bonding structure.

Background

In the technical field of semiconductor manufacturing, with the continuous promotion of new process nodes, the transistor volume is smaller, various physical limits restrict the further development of the transistor, and the extension of the Moore's law is slowed down. At present, three-dimensional integration of semiconductor devices can be realized by bonding two or more semiconductor structures with the same or different functions, and metal interconnection between objects to be bonded can be greatly shortened while the performance of a chip is improved, so that heat generation, power consumption and delay are reduced.

Bonding processes may be distinguished by the bonding targets, including wafer to wafer (wafer) bonding, die to wafer (or so-called die) bonding, and die to die (die to die) bonding.

Disclosure of Invention

In view of the above, the present disclosure provides a bonding compensation method and apparatus, a chip rewiring method, and a bonding structure.

In order to achieve the purpose, the technical scheme of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a bonding compensation method, where the compensation method includes:

providing at least one wafer, wherein a plurality of chips are bonded on the wafer;

determining the target position of each chip according to the actual bonding position and the preset bonding position of each chip on the wafer; wherein the offset parameter between the target position and the predetermined bonding position of each of the chips is the same;

for each of the chips on the wafer: determining a setting position of at least one first rewiring layer to be formed on the chip according to the actual bonding position and the target position; wherein a setup position of a top first rerouting layer of the at least one first rerouting layer is the same as the target position.

In some embodiments, said determining a setting position of at least one first redistribution layer to be formed on the chip according to the actual bonding position and the target position includes:

determining a setting position of a first redistribution layer to be formed on the chip according to the actual bonding position and the target position, wherein the setting position of the first redistribution layer on the chip is located between the actual bonding position of the chip and the target position of the chip;

and repeating the steps until the setting position of the first rewiring layer at the top layer is the same as the target position.

In some embodiments, the determining the target position of each of the chips according to the actual bonding position and the predetermined bonding position of each of the chips on the wafer includes:

determining an offset parameter between the actual bonding position and the preset bonding position of each chip according to the actual bonding position and the preset bonding position of each chip on the wafer;

and determining the target position of each chip according to the offset parameter between the actual bonding position and the preset bonding position of each chip.

In some embodiments, the compensation method further comprises:

and determining the setting position of at least one third redistribution layer to be formed on the wafer according to the setting position of the top first redistribution layer.

In some embodiments, the compensation method further comprises:

for each of the chips on the wafer: determining the setting position of at least one second rewiring layer to be formed on the top first rewiring layer according to the setting position of the top first rewiring layer and the preset bonding position; and the setting position of the top second rewiring layer in the at least one second rewiring layer is the same as the preset bonding position.

In some embodiments, the compensation method further comprises:

and determining the setting position of at least one third rewiring layer to be formed on the wafer according to the setting position of the top second rewiring layer.

In some embodiments, the offset parameters include an offset angle and an offset value.

In a second aspect, an embodiment of the present application provides a bonding compensation apparatus, including:

the calibration module is used for determining the target position of each chip according to the actual bonding position and the preset bonding position of each chip on the wafer; wherein a plurality of the chips are bonded on the wafer; the offset parameters between the target position and the preset bonding position of each chip are the same;

the wiring module is used for determining the setting position of at least one first rewiring layer to be formed on each chip on the wafer according to the actual bonding position and the target position; wherein a setup position of a top first rerouting layer of the at least one first rerouting layer is the same as the target position.

In a third aspect, an embodiment of the present application provides a chip rewiring method, where the wiring method includes:

the setting position of at least one first rewiring layer to be formed on the chip is determined through the bonding compensation method in the technical scheme.

In some embodiments, the routing method further comprises:

for each of the at least one first redistribution layer: determining an offset parameter between the setting position of the first redistribution layer and the actual bonding position of the corresponding chip according to the setting position of the first redistribution layer and the actual bonding position of the corresponding chip;

compensating for an alignment accuracy of a lithography process forming the first redistribution layer according to an offset parameter between the set position of the first redistribution layer and the actual bonding position of the corresponding chip.

In a fourth aspect, an embodiment of the present application provides a bonding structure, including:

at least one wafer bonded with a plurality of chips; the actual bonding position of each chip is different from the preset bonding position, and the offset parameter between the actual bonding position and the preset bonding position of each chip is different;

at least one first redistribution layer disposed on each of the chips; and the offset parameter between the setting position of the top first redistribution layer in the at least one first redistribution layer of each chip and the preset bonding position is the same.

In some embodiments, the bonding structure further comprises:

at least one third redistribution layer disposed on the top first redistribution layer.

In some embodiments, the bonding structure further comprises:

and the setting position of the top second rewiring layer in the at least one second rewiring layer is the same as the preset bonding position.

In some embodiments, the bonding structure further comprises:

and at least one third rewiring layer arranged on the top second rewiring layer.

The embodiment of the application provides a bonding compensation method and device, a chip rewiring method and a bonding structure. The compensation method comprises the following steps: providing at least one wafer, wherein a plurality of chips are bonded on the wafer; determining the target position of each chip according to the actual bonding position and the preset bonding position of each chip on the wafer; wherein the offset parameter between the target position and the predetermined bonding position of each of the chips is the same; for each of the chips on the wafer: determining a setting position of at least one first rewiring layer to be formed on the chip according to the actual bonding position and the target position; wherein a setup position of a top first rerouting layer of the at least one first rerouting layer is the same as the target position. The wafer provided by the embodiment of the application is bonded with a plurality of chips, and the actual bonding position of each chip is different from the preset bonding position in offset parameters, namely the actual bonding position of each chip presents different deviations relative to the preset bonding position; and determining a target position of each chip according to the actual bonding position and the preset bonding position of each chip, and determining a setting position of at least one first redistribution layer to be formed on each chip according to the actual bonding position and the target position, so that the setting position of a top first redistribution layer in the at least one first redistribution layer is the same as the target position, namely the offset parameter between the setting position of the top first redistribution layer corresponding to each chip and the preset bonding position is the same.

In this way, in the case that the deviation parameters between the actual bonding position and the predetermined bonding position of each chip bonded on the same wafer are different, the deviation parameters between the setting position of the top redistribution layer on each chip bonded on the same wafer and the predetermined bonding position are the same, that is, the deviation of the setting position of the top first redistribution layer on each chip bonded on the same wafer with respect to the predetermined bonding position is the same, by adjusting the setting position of at least one first redistribution layer to be formed on each chip. According to the embodiment of the application, the setting position of the first rewiring layer is adjusted to compensate the deviation from the preset bonding position to the actual bonding position in the bonding process from the chip to the wafer, so that the rewiring method of the chip is optimized, and the performance of the bonding structure from the chip to the wafer is improved.

Drawings

Fig. 1 is a schematic flowchart of a bonding compensation method according to an embodiment of the present application;

FIG. 2A is a partial top view of a bonding structure during bond compensation according to an embodiment of the present disclosure;

FIG. 2B is a partial top view of a bonding structure during bond compensation provided by an embodiment of the present application;

FIG. 2C is a partial top view of a bonding structure during bond compensation provided by an embodiment of the present application;

FIG. 2D is a partial top view of a bonding structure during bond compensation as provided by an embodiment of the present application;

FIG. 3A is a first cross-sectional view of a bonding structure during bond compensation as provided in an embodiment of the present application;

FIG. 3B is a second cross-sectional view of a bonding structure during bond compensation provided by an embodiment of the present application;

FIG. 3C is a cross-sectional view of a bonding structure during bond compensation provided by an embodiment of the present application;

FIG. 3D is a cross-sectional view of a fourth bonding configuration during bond compensation provided by an embodiment of the present application;

FIG. 3E is a cross-sectional view of a bonding structure during bond compensation as provided by an embodiment of the present application;

FIG. 3F is a sixth cross-sectional view of a bonding configuration during bond compensation as provided by an embodiment of the present application;

fig. 3G is a cross-sectional view of a bonding structure during bonding compensation provided by an embodiment of the present application;

FIG. 3H is an eighth cross-sectional view of a bonding configuration during bond compensation provided by an embodiment of the present application;

FIG. 3I is a cross-sectional view nine of a bonding structure during bond compensation as provided by an embodiment of the present application;

FIG. 3J is a cross-sectional view ten of a bonding configuration during bond compensation as provided by an embodiment of the present application;

FIG. 3K is an eleventh cross-sectional view of a bonding configuration during bond compensation provided by an embodiment of the present application;

FIG. 3L is a cross-sectional view twelve of a bond structure during bond compensation as provided by an embodiment of the present application;

FIG. 3M is a thirteen cross-sectional view of a bonding configuration during bond compensation as provided by an embodiment of the present application;

FIG. 3N is a fourteenth cross-sectional view of a bonding structure during bond compensation provided by an embodiment of the present application;

FIG. 3O is a cross-sectional view fifteen of a bonding structure during bond compensation as provided by an embodiment of the present application;

FIG. 3P is a cross-sectional view sixteen of a bonding structure during bond compensation as provided by an embodiment of the present application;

the figure includes: 210. a wafer; 221. a first chip; 222. a second chip; 223. a third chip; 224. a fourth chip; 225. a fifth chip; 231. a first actual bonding position; 232. a second actual bonding location; 233. a third actual bonding location; 234. a fourth actual bonding location; 235. a fifth actual bonding location; 241. a first predetermined bonding location; 242. a second predetermined bonding location; 243. a third predetermined bonding location; 244. a fourth predetermined bonding location; 245. a fifth predetermined bonding location; 251. a first target position; 252. a second target position; 253. a third target position; 254. a fourth target position; 255. a fifth target position; 261. a first conductive contact; 262. a second conductive contact; 263. a third conductive contact; 264. a fourth conductive contact; 265. a fifth conductive contact; 271. a setting position of a top first rewiring layer on the first chip; 272. setting a top first rewiring layer on the second chip; 273. a setting position of a top first rewiring layer on a third chip; 274. a setting position of a top first rewiring layer on a fourth chip; 275. a setting position of a top first rewiring layer on a fifth chip; 310. a wafer; 321. a first chip; 322. a second chip; 361. a first dielectric layer; 362. a second dielectric layer; 363. a third dielectric layer; 371. a first mask layer; 371', a patterned first mask layer; 372. a second mask layer; 372' of a patterned second mask layer; 373. a third mask layer; 373' and a patterned third mask layer; 381. a first opening; 382. a second opening; 383. a third opening; 391. a first rewiring layer of the first chip; 392. a first rewiring layer of the second chip; 393. and a third rewiring layer.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the embodiments of the present application and the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.

Spatial relational terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

Hybrid Bonding (Hybrid Bonding) is an emerging Bonding technology in the field of semiconductor manufacturing technology, which gradually transfers the Bonding process from Back End (Back End) to Front End (Front End) wafer fabrication, and has many advantages compared to Bump Bonding (Bump Bonding) of Back End package, such as simple process, smaller size, and higher Input/Output (I/O) density. Hybrid bonding is more suitable for fabricating High-power-consumption, High-Bandwidth chips, such as High Bandwidth Memory (HBM), Neural-Network Processing Unit (NPU), Artificial Intelligence (AI) chips, and the like.

After the chips are mixed and bonded to the wafer, the 2.5D small chips (chips) can be continuously wired or stacked on the upper surface of the chips to form 3D small chips, so as to realize three-dimensional integration of the semiconductor device. A chiplet may also be referred to herein as a module chip, and multiple module chips and base chips are packaged together by interconnection technology between the chips. Generally, a plurality of chips may be bonded to corresponding positions on a wafer, there may be a deviation between actual bonding positions and predetermined bonding positions of the chips, and the deviations of the actual bonding positions of the respective chips bonded on the same wafer with respect to the predetermined bonding positions are different.

However, in the photolithography process, the alignment accuracy is generally compensated in a basic unit of an exposure area (shot), in which a plurality of chips may be included in one exposure area. That is, in the photolithography process, alignment accuracy compensation is simultaneously performed for a plurality of chips different in deviation of an actual bonding position from a predetermined bonding position within an exposure area. Here, performing precision compensation in units of exposure regions cannot simultaneously satisfy rewiring requirements of all chips, which further causes a problem of precision compensation in the photolithography process.

Referring to fig. 1, fig. 1 is a schematic flow chart of a bonding compensation method according to an embodiment of the present application. As shown in fig. 1, an embodiment of the present application provides a bonding compensation method, where the compensation method includes:

step S101, providing at least one wafer, wherein a plurality of chips are bonded on the wafer;

step S102, determining the target position of each chip according to the actual bonding position and the preset bonding position of each chip on the wafer; wherein the offset parameter between the target position and the predetermined bonding position of each of the chips is the same;

step S103, for each chip on the wafer: determining a setting position of at least one first rewiring layer to be formed on the chip according to the actual bonding position and the target position; wherein a setup position of a top first rerouting layer of the at least one first rerouting layer is the same as the target position.

In the embodiment of the present application, under the condition that the offset parameters between the actual bonding position and the predetermined bonding position of each chip bonded on the same wafer are different, the offset parameters between the setting position of the top first redistribution layer on each chip bonded on the same wafer and the predetermined bonding position are the same by adjusting the setting position of the first redistribution layer to be formed on each chip. According to the embodiment of the application, the setting position of the first rewiring layer is adjusted to compensate the deviation from the preset bonding position to the actual bonding position in the bonding process from the chip to the wafer, so that the rewiring method of the chip is optimized, and the performance of the bonding structure from the chip to the wafer is improved.

In the embodiment of the application, offset parameters are provided between the actual bonding position and the preset bonding position of each chip bonded on the same wafer; the target position and the predetermined bonding position of each chip bonded on the same wafer also have an offset parameter, and the set position of the top first redistribution layer in the at least one first redistribution layer to be formed on each chip is the same as the target position, so that the offset parameter between the target position and the predetermined bonding position of each chip is the same as the offset parameter between the set position of the top first redistribution layer on each chip and the predetermined bonding position.

Here, the offset parameter is defined to represent a positional relationship between the actual bonding position and the predetermined bonding position of each chip, the target position and the predetermined bonding position of each chip, and the set position and the target position of the top first rewiring layer on each chip.

A partial top view of a bonding structure during bonding compensation provided by the embodiment of the present application will be described in detail with reference to fig. 2A to 2D.

As shown in fig. 2A, a first chip 221, a second chip 222, a third chip 223, a fourth chip 224, and a fifth chip 225 are sequentially bonded to the wafer 210. The solid line boxes in fig. 2A show that the actual bonding positions of the first chip, the second chip, the third chip, the fourth chip, and the fifth chip are the first actual bonding position 231, the second actual bonding position 232, the third actual bonding position 233, the fourth actual bonding position 234, and the fifth actual bonding position 235, respectively. The dashed boxes in fig. 2A show that the predetermined bonding positions of the first, second, third, fourth and fifth chips are the first 241, second 242, third 243, fourth 244 and fifth 245 predetermined bonding positions, respectively.

Here, the types of chips bonded on the same wafer may be the same or different. For example, the plurality of chips may each be a memory chip, a control chip, or other type of chip.

It should be noted that fig. 2A only shows a partial top view of the structure in which the chips are bonded to the wafer, that is, fig. 2A shows five chips being bonded to the wafer. However, in an actual bonding process, the number of chips is much larger than that shown in fig. 2A. The number of chips bonded to the wafer is not particularly limited in the embodiments of the present application.

Here, a plurality of chips are sequentially bonded to corresponding positions on the wafer, there may be a deviation between actual bonding positions and predetermined bonding positions of the chips, and offset parameters between the actual bonding positions and the predetermined bonding positions of the plurality of chips bonded on the same wafer are different.

It should be noted that any point on the wafer may be selected as an origin, and a two-dimensional coordinate system is established on a plane where the wafer is located, where the two-dimensional coordinate system includes an X axis and a Y axis that are perpendicular to each other. For example, if the wafer is a circle, the center of the circle may be selected as the origin of the two-dimensional coordinate system. For example, if the wafer has a square shape, the intersection of the diagonals of the square shape may be selected as the origin of the two-dimensional coordinate system, or the vertex of the square shape may be selected as the origin of the two-dimensional coordinate system. In the embodiment of the application, the offset parameter is a distance between two coordinate points corresponding to the two positions, and therefore, the position of the origin of the two-dimensional coordinate system does not affect the offset parameter. More specifically, the position of the origin of the two-dimensional coordinate system does not affect the offset parameter between the actual bonding position and the predetermined bonding position, nor the offset parameter between the target position and the predetermined bonding position.

Specifically, the first chip is taken as an example for explanation. Suppose the actual bonding position of the first chip is (X) ₂₃₁ ，Y ₂₃₁ ) The predetermined bonding position of the first chip is (X) ₂₄₁ ，Y ₂₄₁ ) Then the offset parameter between the actual bonding position and the predetermined bonding position of the first chip is Δ X ₃₄ ，∆Y ₃₄ ) Therein is Δ X ₃₄ =X ₂₃₁ −X ₂₄₁ ，∆Y ₃₄ =Y ₂₃₁ −Y ₂₄₁ 。

Δ X is to be specified ₃₄ And Δ Y ₃₄ Indicating the distances of the coordinate point corresponding to the actual bonding position of the first chip and the coordinate point corresponding to the preset bonding position on the X axis and the Y axis respectively, and ₃₄ and Δ Y ₃₄ The numerical result of (c) has positive and negative, where positive and negative indicate direction. For example, Δ X of the first chip ₃₄ A positive value indicates that the coordinates of the actual bonding position of the first chip on the X-axis are located in the positive direction of its intended bonding position along the X-axis. Or, for example, Δ X of the first chip ₃₄ A negative value indicates that the coordinate of the actual bonding position of the first chip on the X-axis is located in a negative direction along the X-axis of its intended bonding position.

Here, the offset parameter between the actual bonding position and the predetermined bonding position of each chip is different. For example, on the same wafer, the coordinates of the actual bonding position of the first chip on the XY plane and the coordinates of the predetermined bonding position on the XY plane differ only by the X-axis coordinate value or the Y-axis coordinate value, i.e., X is ₂₃₁ Is equal to X ₂₄₁ And Y is ₂₃₁ And Y ₂₄₁ Different, or X ₂₃₁ And X ₂₄₁ Is different and Y ₂₃₁ Is equal to Y ₂₄₁ (ii) a And the coordinate of the actual bonding position of the second chip on the XY plane is different from the coordinate of the predetermined bonding position on the XY plane in terms of X-axis coordinate value and Y-axis coordinate value, that is, X is ₂₃₁ And X ₂₄₁ Is different and Y ₂₃₁ And Y ₂₄₁ Different. Actual bonding positions of a plurality of chips bonded on the same wafer exhibit irregular deviations from predetermined bonding positions.

As shown in fig. 2B, the target positions of the first chip, the second chip, the third chip, the fourth chip, and the fifth chip are a first target position 251, a second target position 252, a third target position 253, a fourth target position 254, and a fifth target position 255, respectively.

Here, the target position of each chip is different from the predetermined bonding position, but the offset parameter between the target position of each chip and the predetermined bonding position is the same. In the embodiment of the present application, the fact that the offset parameters between the target position and the predetermined bonding position of each chip are the same means that the offset angle and the offset value between the target position and the predetermined bonding position of each chip are the same.

Specifically, the first chip is taken as an example for explanation. Assume that the target position of the first chip is (X) ₂₅₁ ，Y ₂₅₁ ) The predetermined bonding position of the first chip is (X) ₂₄₁ ，Y ₂₄₁ ) Then the offset parameter between the target position of the first chip and the predetermined bonding position is Δ X ₅₄ ，∆Y ₅₄ ) Therein is Δ X ₅₄ =X ₂₅₁ −X ₂₄₁ ，∆Y ₅₄ =Y ₂₅₁ −Y ₂₄₁ 。

Δ X is to be specified ₅₄ And Δ Y ₅₄ Indicating the distances between the coordinate point corresponding to the target position of the first chip and the coordinate point corresponding to the preset bonding position on the X axis and the Y axis respectively, and ₅₄ and Δ Y ₅₄ The numerical result of (c) has positive and negative, where positive and negative indicate direction. For example, Δ X of the first chip ₅₄ A positive value is obtained, thenCoordinates on the X-axis representing the target position of the first chip are located in a positive direction along the X-axis of its predetermined bonding position. Or, for example, Δ X of the first chip ₅₄ A negative value indicates that the target position of the first chip is located in a negative direction along the X-axis with respect to its intended bonding position.

Here, the offset parameter between the target position and the predetermined bonding position of each chip is the same. For example, the coordinates of the target positions of all the chips bonded on the same wafer on the XY plane and the coordinates of the predetermined bonding positions on the XY plane are different only by the X-axis coordinate value or the Y-axis coordinate value, i.e., the coordinate values of the target positions of all the chips on the X axis and the coordinate values of the predetermined bonding positions on the X axis are the same and the coordinate values of the target positions of all the chips on the Y axis and the coordinate values of the predetermined bonding positions on the Y axis are different, or the coordinate values of the target positions of all the chips on the X axis and the coordinate values of the predetermined bonding positions on the X axis and the coordinate values of the target positions of all the chips on the Y axis and the coordinate values of the predetermined bonding positions on the Y axis are the same. For another example, the coordinates of the target positions of all the chips bonded on the same wafer on the XY plane and the X-axis coordinate values and the Y-axis coordinate values of the coordinates of the predetermined bonding positions on the XY plane are different, that is, the coordinate values of the target positions of all the chips on the X axis and the coordinate values of the predetermined bonding positions on the X axis are different and the coordinate values of the target positions of all the chips on the Y axis and the coordinate values of the predetermined bonding positions on the Y axis are different.

In the embodiment of the application, an offset parameter is provided between the actual bonding position and the predetermined bonding position of each chip, an offset parameter is also provided between the target position and the predetermined bonding position of each chip, and an offset parameter is also provided between the setting position of the top first redistribution layer on each chip and the predetermined bonding position. The actual bonding positions and the predetermined bonding positions of the respective chips, and the offset parameters between the target positions and the predetermined bonding positions of the respective chips will be described as examples.

Here, the offset parameter between the actual bonding position and the predetermined bonding position of the chip may be understood as a difference value between a coordinate point corresponding to the actual bonding position of the chip and a coordinate point corresponding to the predetermined bonding position, that is, a vector pointing from the coordinate point corresponding to the predetermined bonding position of the chip to the coordinate point corresponding to the actual bonding position, where the vector and the X axis and the Y axis both form a certain included angle, where the included angle is an offset angle. And decomposing the vectors along the X axis and the Y axis respectively to obtain the distances of the coordinate point corresponding to the actual bonding position of the chip and the coordinate point corresponding to the preset bonding position on the X axis and the Y axis respectively, wherein the distances are offset values.

Here, the offset parameter between the target position of the chip and the predetermined bonding position may be understood as a difference value between a coordinate point corresponding to the target position of the chip and a coordinate point corresponding to the predetermined bonding position, that is, a vector pointing from the coordinate point corresponding to the predetermined bonding position of the chip to the coordinate point corresponding to the target position, where the vector forms a certain included angle with both the X axis and the Y axis, where the included angle is an offset angle. And decomposing the vectors along the X axis and the Y axis respectively to obtain the distances of the coordinate point corresponding to the target position of the chip and the coordinate point corresponding to the preset bonding position on the X axis and the Y axis respectively, wherein the distances are offset values.

Specifically, the first chip is taken as an example for explanation. The offset parameter between the target position of the first chip and the preset bonding position is (Δ X) ₅₄ ，∆Y ₅₄ ) Therein is Δ X ₅₄ =X ₂₅₁ −X ₂₄₁ ，∆Y ₅₄ =Y ₂₅₁ −Y ₂₄₁ . Herein, if Δ X ₅₄ =0，∆Y ₅₄ Positive, then the coordinates of the target location of the first chip on the Y-axis are in the positive direction along the Y-axis of its intended bonding location; if Δ X ₅₄ =0，∆Y ₅₄ A negative value, the coordinates of the target position of the first chip on the Y-axis are located in a negative direction along the Y-axis of its predetermined bonding position; if an ₅₄ Is a positive value of ₅₄ =0, then the coordinates of the target position of the first chip on the X-axis are located in the positive direction along the X-axis of its predetermined bonding position; if Δ X ₅₄ Is a negative value of ₅₄ =0, then firstThe coordinates of the target position of the chip on the X-axis are located in the negative direction along the X-axis of its intended bonding position.

In the embodiment of the present application, the setting position of the top first redistribution layer on each chip is the same as the target position of each chip, in other words, the offset parameter between the setting position of the top first redistribution layer on each chip and the predetermined bonding position of each chip is the same.

It should be noted that, in an actual process, considering that there is a process error, it is difficult to achieve absolutely the same offset parameter between the setting position of the top first redistribution layer of each chip and the predetermined bonding position of each chip, and the offset parameter between the setting position of the top first redistribution layer of each chip and the predetermined bonding position of each chip is substantially the same. Here, the substantially same means that the offset parameter between the set position of the top first redistribution layer of each chip and the predetermined bonding position of each chip is the same, or the difference between the set position of the top first redistribution layer of each chip and the predetermined bonding position of each chip is a process error and is negligible.

In one embodiment, a difference between the set position of the top first redistribution layer of any two chips and the predetermined bonding position of each chip is smaller than a preset angle, and a difference between the set position of the top first redistribution layer of any two chips and the predetermined bonding position of each chip is smaller than a preset value. Here, the preset angle may be determined as 1/3 for the angle complement limit, i.e., 1/3 for the maximum value of the angle complement; the preset value can also be determined as 1/3 of the complement limit of the overlay precision (OVL), that is, the preset value is determined as 1/3 of the maximum value of the overlay precision. Wherein the angle compensation limit can be determined according to the used process capacity and is within the range of 10 ⁻⁸ Degree to 10 ⁻² Degree; the maximum value of the overlay accuracy can be determined according to the process accuracy used, ranging from 5nm to 10 μm.

Here, the target position of each chip is determined using the offset parameters, i.e., the offset angle and the offset value, between the actual bonding position and the predetermined bonding position of each chip so that the offset parameters between the target position and the predetermined bonding position of each chip are the same. The target position of each chip has various choices to satisfy the condition that the offset parameter between the target position of each chip and the preset bonding position is the same. For example, the coordinate values of the target positions of the chips on the X axis may all be the same as the coordinate values of the predetermined bonding positions on the X axis, and the coordinates of the target positions of the chips on the Y axis may all be located in the positive direction along the Y axis of the predetermined bonding positions thereof. For another example, the coordinate values of the target positions of the chips on the X-axis may all be the same as the coordinate values of the predetermined bonding positions on the X-axis, and the coordinates of the target positions of the chips on the Y-axis may all be located in the negative direction along the Y-axis of the predetermined bonding positions thereof. At this time, the path lengths of the chips moved from the actual bonding positions to the target positions can be obtained by fitting through computer software and summed, so that the path length sum corresponding to different target positions can be obtained, and the target position corresponding to the minimum path length sum can be selected, so that the number of layers for setting the first rewiring layer is reduced as much as possible, and the process flow is simplified.

In the embodiment of the application, the setting position of at least one first rewiring layer to be formed on a chip is determined according to the actual bonding position and the target position of the chip; wherein a set position of a top first rerouting layer of the at least one first rerouting layer is the same as the target position.

and repeating the steps until the setting position of the top first rewiring layer is the same as the target position.

Here, a first rewiring layer may be formed on the chip at a same set position as the target position. Of course, it is also possible to form a plurality of first redistribution layers on the chip, the setting position of the first redistribution layer of the first layer being located between the actual bonding position of the chip and the target position of the chip, and the setting position of the first redistribution layer of the second layer being located between the setting position of the first redistribution layer of the first layer and the target position of the chip, until the setting position of the top first redistribution layer finally formed is the same as the target position of the chip. That is, in the process of forming at least one first rewiring layer, the setting position of the first rewiring layer is moved from the actual bonding position of the chip to the target position of the chip. More specifically, the orthographic projection of the setting position of the first redistribution layer on the wafer is located between the actual bonding position of the chip and the target position of the chip, and the orthographic projection of the setting position of the first redistribution layer on the wafer is located between the orthographic projection of the setting position of the first redistribution layer on the wafer and the target position of the chip until the finally formed orthographic projection of the setting position of the first redistribution layer on the top layer on the wafer is the same as the target position of the chip.

In a preferred embodiment of the present application, the offset parameter between the target position of the chip and the predetermined bonding position is the same. In a more preferred embodiment of the present application, the target position of the chip is the same as the predetermined bonding position, i.e. both the offset angle and the offset value between the target position of the chip and the predetermined bonding position are 0.

Fig. 2C shows a setup position 271 of the top-level first redistribution layer on the first chip, and an orthographic projection of the setup position 271 of the top-level first redistribution layer on the first chip on the wafer may be regarded as a first target position, and an offset parameter is provided between the setup position of the top-level first redistribution layer on the first chip and a first predetermined bonding position (a dashed box in fig. 2C). Here, in fig. 2C, only the setting position of the first redistribution layer on the first chip is adjusted so that the setting position of the top first redistribution layer is the same as the target position of the first chip, and then the setting positions of the first redistribution layers on the second chip, the third chip, the fourth chip, and the fifth chip may be adjusted in sequence. Here, the actual bonding position of the first chip is unchanged, by forming at least one first redistribution layer on the first chip, further by the top first redistribution layer in the at least one first redistribution layer, it is equivalent to compensating the first chip from the first actual bonding position 231 shown in fig. 2B to the setting position 271 (i.e., the target position of the first chip) of the top first redistribution layer on the first chip shown in fig. 2C. Fig. 2C shows the position of the first conductive contact 261 on the first chip by perspective view of the top-level first redistribution layer on the first chip, and fig. 2C does not show the first actual bonding position of the first chip in order to more clearly illustrate the location of the top-level first redistribution layer on the first chip and the first predetermined bonding position.

Still referring to fig. 2C, the first chip, the second chip, the third chip, the fourth chip, and the fifth chip include a first conductive contact 261, a second conductive contact 262, a third conductive contact 263, a fourth conductive contact 264, and a fifth conductive contact 265, respectively. The dashed circle in fig. 2C shows the conductive contacts that are the chips. Here, the first chip, the second chip, the third chip, the fourth chip and the fifth chip each include four conductive contacts. However, in an actual bonding process, the number of conductive contacts on the chip is greater than the number of conductive contacts shown in fig. 2C. The number of conductive contacts on the chip is not particularly limited in the embodiments of the present application.

Here, the at least one first redistribution layer may be formed on the chip such that a set position of a top first redistribution layer in the at least one first redistribution layer is the same as the target position. It should be noted that determining the number of first redistribution layers requires considering the positions of the conductive contacts, and if the offset parameter between the actual bonding position of the chip and the target position is too large, setting only one first redistribution layer may result in poor electrical contact between the first redistribution layer and each chip, and in this case, multiple first redistribution layers need to be set to achieve good electrical contact between each chip and the first redistribution layer, and between the multiple first redistribution layers.

Fig. 2D shows that the set position 272 of the top-level first redistribution layer on the second chip, the set position 273 of the top-level first redistribution layer on the third chip, the set position 274 of the top-level first redistribution layer on the fourth chip, and the set position 275 of the top-level first redistribution layer on the fifth chip may be regarded as a second target position, a third target position, a fourth target position, and a fifth target position, respectively, and then the offset parameter between the set position 272 of the top-level first redistribution layer on the second chip and the second predetermined bonding position (dashed square in fig. 2D), the offset parameter between the set position 273 of the top-level first redistribution layer on the third chip and the third predetermined bonding position (dashed square in fig. 2D), the offset parameter between the set position 274 of the top-level first redistribution layer on the fourth chip and the fourth predetermined bonding position (dashed square in fig. 2D), and the set positions 275 and 275 of the top-level first redistribution layer on the fifth chip and the fifth chip The offset parameters between the fifth predetermined bonding locations (dashed boxes in fig. 2D) are all the same. Here, by forming at least one first rewiring layer in sequence on the second chip, the third chip, the fourth chip, and the fifth chip, and further by the top-layer first rewiring layer in the at least one first rewiring layer, it is equivalent to compensating the second chip, the third chip, the fourth chip, and the fifth chip from the second actual bonding position 232, the third actual bonding position 233, the fourth actual bonding position 234, and the fifth actual bonding position 235 shown in fig. 2C to the top-layer first rewiring layer setting position 272 on the second chip (i.e., the target position of the second chip), the top-layer first rewiring layer setting position 273 on the third chip (i.e., the target position of the third chip), the top-layer first rewiring layer setting position 274 on the fourth chip (i.e., the target position of the fourth chip), and the top-layer first rewiring layer setting position 275 on the fifth chip (i.e., the target position of the fifth chip). Fig. 2D shows the positions of the conductive contacts on each chip by perspective view of the top first redistribution layer on each chip, and fig. 2D does not show the actual bonding positions of each chip in order to more clearly illustrate the arrangement positions of the top first redistribution layer on each chip and the predetermined bonding positions of each chip.

Here, the first rewiring layer of the first layer may be sequentially formed for each chip on the wafer, and then the first rewiring layer of the second layer may be sequentially formed for each chip on the wafer until the first rewiring layer of the top layer is sequentially formed for each chip on the wafer. In other words, only one first redistribution layer on one chip is formed at a time. Of course, the actual bonding positions, the predetermined bonding positions and the target positions of all the chips on the same wafer may also be obtained in advance, the offset parameters between the actual bonding positions and the predetermined bonding positions of the chips are analyzed, the offset parameters between the target positions and the actual bonding positions of the chips are analyzed, the chips with the same or similar offset parameters between the target positions and the actual bonding positions are selected, and a first rewiring layer on the chips is formed at the same time. For example, a first re-wiring layer may be formed on the first chip and the second chip at the same time. Thus, the time for forming the first rewiring layer on the chip can be greatly shortened.

In some embodiments, the compensation method further comprises:

Here, the setting position of the at least one first redistribution layer to be formed on the chips is determined based on the actual bonding position and the target position, that is, the offset parameter between the setting position of the top first redistribution layer on each chip on the same wafer and the predetermined bonding position is made the same by forming the at least one first redistribution layer to compensate for the deviation between the actual bonding position and the predetermined bonding position of each chip.

Here, the setting position of at least one third redistribution layer to be formed on the wafer is determined according to the setting position of the top first redistribution layer. At this time, the offset parameter between the set position of the top first rewiring layer and the predetermined bonding position is the same, and the set position of the third rewiring layer is determined based on the set position of the top first rewiring layer. In some embodiments, a third redistribution layer is located above the top first redistribution layer in a direction perpendicular to a plane of the wafer, and the third redistribution layer is capable of at least electrically connecting the top first redistribution layers. In other embodiments, the third redistribution layer is located above the top first redistribution layer in the direction perpendicular to the plane of the wafer, and the area of the orthographic projection of the third redistribution layer on the wafer is not particularly limited, for example, the area of the orthographic projection of the third redistribution layer on the wafer may be equal to the area of the exposure region, or the area of the orthographic projection of the third redistribution layer on the wafer may be equal to the area of the wafer.

An embodiment of the present application further provides a bonding structure, where the bonding structure includes:

In some embodiments, the bonding structure further comprises:

and the third rewiring layer is arranged on the first rewiring layer on the top layer.

Here, in the case where the offset parameter between the actual bonding position and the predetermined bonding position of each chip bonded on the same wafer is different, the offset parameter between the set position of the top first redistribution layer on each chip bonded on the same wafer and the predetermined bonding position is made the same by adjusting the set position of the first redistribution layer to be formed on each chip. In this way, the adjustment of the setting position of the first rewiring layer can be utilized to compensate the deviation from the preset bonding position to the actual bonding position in the chip-to-wafer bonding process.

In some embodiments, the compensation method further comprises:

Here, in the case where the offset parameter between the setup position of the top first redistribution layer on each chip on the wafer and the predetermined bonding position is the same, the setup position of the top second redistribution layer in the at least one second redistribution layer is made the same as the predetermined bonding position by further adjusting the setup position of the second redistribution layer. Therefore, the first rewiring layer and the second rewiring layer can completely compensate deviation generated in the bonding process of the chip and the wafer, and the rewiring method of the chip is further optimized. Further, since the offset parameter between the set position of the top-level first rewiring layer and the predetermined bonding position is the same already by the adjustment of the set position of the first rewiring layer, it is possible to form the second rewiring layer on the top-level first rewiring layer of each chip at the same time with the exposure area (including a plurality of chips) as a basic unit. Thus, the time for forming the second rewiring layer on the top-level first rewiring layer can be greatly shortened.

In the bonding compensation method provided in the embodiment of the present application, if a first redistribution layer is set, a setting position of the first redistribution layer is the same as a target position, that is, an offset parameter between the setting position of the first redistribution layer and a predetermined bonding position is the same; a second rewiring layer may be provided at the first rewiring layer at the same position as the predetermined bonding position. That is to say, the embodiment of the present application can compensate for the deviation generated in the process of bonding the chip to the wafer by adjusting the setting position of the first rewiring layer, thereby optimizing the rewiring method of the chip. Further, since the offset parameter between the set position of the top first rewiring layer and the predetermined bonding position has been the same by the adjustment of the set position of the first rewiring layer. Therefore, the second redistribution layer can be formed on the top first redistribution layer of each chip simultaneously on the basis of forming the first redistribution layer. Therefore, the offset parameter between the setting position of the first rewiring layer at the top layer on each chip and the preset bonding position of each chip is the same, the setting position of the second rewiring layer at the top layer on each chip is the same as the preset bonding position of each chip, and the exposure area can be used as a basic unit, so that at least one third rewiring layer can be formed on the second rewiring layer at the top layer or the first rewiring layer at the top layer subsequently.

In the preferred embodiment of the present application, a first redistribution layer may be provided on each chip. The first rewiring layer is provided at the same position as the predetermined bonding position, and the second rewiring layer is not required to be provided.

The embodiment of the present application further provides a bonding structure, where the bonding structure further includes:

In some embodiments, the bonding structure further comprises:

Here, in a case where the offset parameter between the setting position of the top first redistribution layer of each chip bonded on the same wafer and the predetermined bonding position is the same, the setting position of the top second redistribution layer on each chip bonded on the same wafer is made to be the same as the predetermined bonding position by adjusting the setting position of the second redistribution layer to be formed on each chip, and the exposure area may be used as a basic unit to facilitate the subsequent formation of at least one third redistribution layer on the top second redistribution layer. And the adjustment of the setting position of the second re-wiring layer can be utilized to completely compensate the error generated in the bonding process of the chip to the wafer.

The embodiment of the application also provides a chip rewiring method, which comprises the following steps:

In some embodiments, the routing method further comprises:

A cross-sectional view of the bonding structure during the bonding compensation process provided by the embodiment of the present application will be described in detail below with reference to fig. 3A to 3P. For convenience of explanation, a first redistribution layer is formed on each chip bonded on the same wafer, and the offset parameter between the arrangement position of the first redistribution layer of each chip and the predetermined bonding position is the same.

As shown in fig. 3A, a first chip 321 and a second chip 322 are bonded on the wafer 310.

Here, a plurality of chips may be bonded on the wafer. For convenience of explanation, only two chips bonded on a wafer will be explained below.

As shown in fig. 3B, a first dielectric material is deposited on the wafer 310 to form a first dielectric layer 361.

Here, the method of depositing to form the first dielectric layer includes, but is not limited to, a physical vapor deposition method, a chemical vapor deposition method, and an atomic layer deposition method.

As shown in fig. 3C, the first dielectric layer 361 is planarized such that the upper surface of the first dielectric layer 361 is flush with the upper surfaces of the first chip 321 and the second chip 322.

Here, the first dielectric layer is formed to fill the gap between the chips on the wafer. It should be noted that a plurality of chips, called an island-shaped wafer, are bonded on a wafer, and a first dielectric layer is formed on the wafer, so that an upper surface of the first dielectric layer is flush with an upper surface of each chip on the wafer.

As shown in fig. 3D, a second dielectric material is deposited on the upper surfaces of first dielectric layer 361, first chip 321, and second chip 322 to form a second dielectric layer 362.

Here, the material of the second dielectric layer may be the same as or different from the material of the first dielectric layer, i.e., the second dielectric material and the first dielectric material may be the same as or different from each other. In one embodiment, the material of the second dielectric layer is the same as the material of the first dielectric layer.

As shown in fig. 3E, a first mask layer 371 is formed on the upper surface of the second dielectric layer 362.

Here, a photoresist may be used as a mask layer.

As shown in fig. 3F, a patterned first mask layer 371 'is formed, and the opening of the patterned first mask layer 371' corresponds to the first chip 321.

As shown in fig. 3G, the second dielectric layer 362 is etched using the patterned first mask layer to form a first opening 381 corresponding to the first chip 321 in the second dielectric layer 362, and the patterned first mask layer is removed.

As shown in fig. 3H, the first opening in the second dielectric layer 362 is filled to form a first redistribution layer 391 of the first chip, and the first redistribution layer 391 of the first chip is flush with the upper surface of the second dielectric layer 362.

Here, the opening position of the patterned first mask layer is the same as the first opening position in the second dielectric layer, and the first opening position in the second dielectric layer is the setting position of the first redistribution layer of the first chip. Specifically, in the photolithography process, as described above, the bonding compensation method provided by the embodiment of the present application is used to determine the target position of the first chip according to the actual bonding position and the predetermined bonding position of the first chip on the wafer; the offset parameters between the target position of each chip on the wafer and the preset bonding position are the same; determining a setting position of a first rewiring layer to be formed on the first chip according to the actual bonding position and the target position; wherein the setting position of the first rewiring layer is the same as the target position.

Here, a vector pointing from the setting position of the first rewiring layer to the actual bonding position of the first chip may be defined according to an offset parameter between the setting position of the first rewiring layer and the actual bonding position of the first chip, alignment accuracy compensation may be performed on the opening position of the patterned first mask layer according to the vector, the second dielectric layer may be etched according to the opening of the patterned first mask layer to form a first opening corresponding to the first chip in the second dielectric layer, and the first opening in the second dielectric layer may be filled to form the first rewiring layer of the first chip. In this way, the alignment accuracy of the opening of the patterned first mask layer forming the first redistribution layer can be compensated for in the photolithography process using the aforementioned bonding compensation method.

As shown in fig. 3I, a second mask layer 372 is formed on the first redistribution layer 391 and the upper surface of the second dielectric layer 362 of the first chip.

As shown in fig. 3J, a patterned second mask layer 372 'is formed, and the opening of the patterned second mask layer 372' corresponds to the second chip 322.

As shown in fig. 3K, the second dielectric layer 362 is etched using the openings of the patterned second mask layer to form a second opening 382 in the second dielectric layer 362 corresponding to the second chip 322, and the patterned second mask layer is removed.

As shown in fig. 3L, the second opening in the second dielectric layer 362 is filled to form the first redistribution layer 392 of the second chip, and the first redistribution layer 392 of the second chip is flush with the upper surface of the second dielectric layer 362.

Here, the opening position of the patterned second mask layer is the same as the second opening position in the second dielectric layer, and the second opening position in the second dielectric layer is the setting position of the first redistribution layer of the second chip. Specifically, in the photolithography process, as described above, the bonding compensation method provided by the embodiment of the present application is used to determine the target position of the second chip according to the actual bonding position and the predetermined bonding position of the second chip on the wafer; the offset parameters between the target position of each chip on the wafer and the preset bonding position are the same; determining a setting position of a first rewiring layer to be formed on the second chip according to the actual bonding position and the target position; wherein the setting position of the first rewiring layer is the same as the target position.

Here, a vector pointing from the setting position of the first rewiring layer to the actual bonding position of the second chip may be defined according to an offset parameter between the setting position of the first rewiring layer and the actual bonding position of the second chip, alignment accuracy compensation may be performed on an opening position of the patterned second mask layer according to the vector, the second dielectric layer may be etched according to an opening of the patterned second mask layer to form a second opening corresponding to the second chip in the second dielectric layer, and the second opening in the second dielectric layer may be filled to form the first rewiring layer of the second chip. In this way, the alignment accuracy of the opening of the patterned second mask layer forming the first redistribution layer can be compensated for in the photolithography process using the aforementioned bonding compensation method.

As shown in fig. 3M, a third dielectric material is deposited on the upper surfaces of the second dielectric layer 362, the first redistribution layer 391 of the first chip, and the first redistribution layer 392 of the second chip to form a third dielectric layer 363; a third mask layer 373 is formed on the top surface of the third dielectric layer 363.

Here, the material of the third dielectric layer may be the same as or different from the material of the second dielectric layer, the material of the first dielectric layer, that is, the third dielectric material, the second dielectric material, and the first dielectric material may be the same as or different from each other. In one embodiment, the material of the third dielectric layer is the same as the material of the second dielectric layer and the material of the first dielectric layer.

As shown in fig. 3N, a patterned third mask layer 373 'is formed, and the opening of the patterned third mask layer 373' corresponds to the wafer 310.

As shown in fig. 3O, the third dielectric layer 363 is etched by using the openings of the patterned third mask layer to form third openings 383 corresponding to the wafer 310 in the third dielectric layer 363, and the patterned third mask layer is removed.

As shown in fig. 3P, the third opening in the third dielectric layer 363 is filled to form a third redistribution layer 393 corresponding to the wafer, and the upper surfaces of the third redistribution layer 393 and the third dielectric layer 363 are flush.

Here, the opening position of the patterned third mask layer is the same as the third opening position in the third dielectric layer, and the third opening position in the third dielectric layer is the setting position of the third redistribution layer corresponding to the wafer. As described above, the first rewiring layers are sequentially formed on the first chip and the second chip, and at this time, the arrangement positions of the first rewiring layers of the first chip and the second chip are the same as the offset parameters between the predetermined bonding positions of the first chip and the second chip, respectively. In this way, in the case where the offset parameter between the set position of the first wiring layer and the predetermined bonding position is the same, the third rewiring layer is formed on the upper surface of the first rewiring layer of each chip, and the third rewiring layer can achieve electrical connection between the first rewiring layers on each chip.

The chip rewiring method provided by the embodiment of the application considers that the deviation parameters between the actual bonding positions and the preset bonding positions of a plurality of chips on the wafer are different, namely the deviation of the actual bonding positions of the chips on the wafer relative to the preset bonding positions is different after the chips are mixed and bonded to the wafer. Therefore, in the photolithography process, a vector pointing from the set position of the first rewiring layer to the actual bonding position of each chip is defined according to the offset parameter between the set position of the first rewiring layer and the actual bonding position of each chip, and alignment accuracy compensation is performed on the opening position of the patterned mask layer forming the first rewiring layer according to the vector. After the first redistribution layer is formed on each chip, the offset parameters between the first redistribution layer on each chip and the predetermined bonding position of each chip are the same, so that alignment accuracy compensation can be performed on the opening position of the patterned mask layer forming the third redistribution layer on the first redistribution layer in units of exposure regions (including a plurality of chips).

The embodiment of the present application further provides a multilayer chip stacking method, where the stacking method includes:

providing at least one bottom chip having a plurality of top chips bonded thereto;

the setting position of at least one first rewiring layer to be formed on the top chip is determined through the bonding compensation method in the technical scheme.

Here, it is considered that the deviation parameters between the actual bonding positions and the predetermined bonding positions of the plurality of top chips on the bottom chip are different, that is, the deviation of the actual bonding positions of the respective top chips on the bottom chip from the predetermined bonding positions is different after the bonding of the top chip to the bottom chip. At this time, if the alignment accuracy compensation is performed in units of exposure regions, the rewiring requirements of all the top chips cannot be satisfied simultaneously. It should be noted that the bottom chips are usually in the unit of exposure area, that is, one exposure area has only one bottom chip.

Specifically, in the photolithography process, a vector pointing from the set position of the first redistribution layer to the actual bonding position of each top chip is defined according to an offset parameter between the set position of the first redistribution layer and the actual bonding position of each top chip, and alignment accuracy compensation is performed on the opening position of the patterned mask layer forming the first redistribution layer according to the vector. After the first redistribution layer is formed on each top chip, the offset parameters between the first redistribution layer on each top chip and the predetermined bonding position of each top chip are the same, so that the alignment accuracy compensation can be performed on the opening position of the patterned mask layer forming the third redistribution layer on the first redistribution layer by taking the exposure region (or called as the bottom chip) as a unit.

An embodiment of the present application further provides a bonding compensation apparatus, including:

The embodiment of the application provides a bonding compensation method and device, a chip rewiring method and a bonding structure. The compensation method comprises the following steps: providing at least one wafer, wherein a plurality of chips are bonded on the wafer; determining the target position of each chip according to the actual bonding position and the preset bonding position of each chip on the wafer; wherein the offset parameter between the target position and the predetermined bonding position of each of the chips is the same; for each of the chips on the wafer: determining a setting position of at least one first rewiring layer to be formed on the chip according to the actual bonding position and the target position; wherein, the setting position of the top first rewiring layer in the at least one first rewiring layer is the same as the target position. The wafer provided by the embodiment of the application is bonded with a plurality of chips, and the actual bonding position of each chip is different from the preset bonding position in offset parameters, namely the actual bonding position of each chip is different from the preset bonding position in offset; and determining a target position of each chip according to the actual bonding position and the preset bonding position of each chip, and determining a setting position of at least one first redistribution layer to be formed on each chip according to the actual bonding position and the target position, so that the setting position of a top first redistribution layer in the at least one first redistribution layer is the same as the target position, namely the offset parameter between the setting position of the top first redistribution layer corresponding to each chip and the preset bonding position is the same.

In this way, in the case that the deviation parameters between the actual bonding position and the predetermined bonding position of each chip bonded on the same wafer are different, the deviation parameters between the setting position of the top first redistribution layer on each chip bonded on the same wafer and the predetermined bonding position are the same, that is, the deviation of the setting position of the top first redistribution layer on each chip bonded on the same wafer with respect to the predetermined bonding position is the same, by adjusting the setting position of at least one layer of first redistribution layer to be formed on each chip. According to the embodiment of the application, the setting position of the first rewiring layer is adjusted to compensate the deviation from the preset bonding position to the actual bonding position in the bonding process from the chip to the wafer, so that the rewiring method of the chip is optimized, and the performance of the bonding structure from the chip to the wafer is improved.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that are included in the present application, which are made by the present specification and the accompanying drawings, or are directly/indirectly applied to other related technical fields, are included in the scope of the present application.

Claims

1. A bonding compensation method, the compensation method comprising:

2. The bonding compensation method of claim 1, wherein determining a placement position of at least one first redistribution layer to be formed on the chip based on the actual bonding position and the target position comprises:

3. The bonding compensation method of claim 1, wherein determining the target position of each of the chips based on the actual bonding position and the predetermined bonding position of each of the chips on the wafer comprises:

4. The bonding compensation method of claim 1, further comprising:

5. The bonding compensation method of claim 1, further comprising:

for each of the chips on the wafer: determining the setting position of at least one second rewiring layer to be formed on the top first rewiring layer according to the setting position of the top first rewiring layer and the preset bonding position; and the arrangement position of the top second re-wiring layer in the at least one second re-wiring layer is the same as the preset bonding position.

6. The bonding compensation method of claim 5, further comprising:

7. The bonding compensation method of claim 1, wherein the offset parameters include an offset angle and an offset value.

8. A bond compensation apparatus, comprising:

9. A chip rewiring method is characterized by comprising the following steps:

determining a setting position of at least one first rewiring layer to be formed on the chip by the bonding compensation method according to any one of claims 1 to 7.

10. The chip rewiring method of claim 9, wherein the wiring method further comprises:

11. A bonding structure, comprising:

12. The bonding structure of claim 11, further comprising:

13. The bonding structure of claim 11, further comprising:

14. The bonding structure of claim 13, further comprising: