CN114664336B - Stacked memory device, memory chip and control method thereof - Google Patents
Stacked memory device, memory chip and control method thereof Download PDFInfo
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- CN114664336B CN114664336B CN202210275948.2A CN202210275948A CN114664336B CN 114664336 B CN114664336 B CN 114664336B CN 202210275948 A CN202210275948 A CN 202210275948A CN 114664336 B CN114664336 B CN 114664336B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30141—Implementation provisions of register files, e.g. ports
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
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Abstract
The application discloses a stacked memory device, a memory chip and a control method thereof. The control method of the memory chip comprises the following steps: receiving a data operation instruction; judging whether the memory chip is used as a target chip or a non-target chip according to the relation between the instruction address of the data operation instruction and the chip identification of the memory chip; executing the data operation instruction in the case of the memory chip as a destination chip, and storing state information generated during the execution of the data operation instruction by itself in a state register of the memory chip; and in the case that the memory chip is a non-destination chip, discarding the data operation instruction, and synchronizing status information generated during execution of the data operation instruction by the destination chip in a status register of the memory chip. The control method of the memory chip utilizes the chip identification stored in the identification register and different working modes of the status register to embed and support terminal multiplexing so as to improve the data rate and reduce the device cost.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a stacked memory device, a memory chip and a control method thereof.
Background
Memories used in computer systems may be divided into volatile memories and non-volatile memories according to the data storage capacity in a power-off state. Volatile memories store data only in a powered state and lose data in a powered down state, including Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), for example. Non-volatile memory can store data in both a powered up state and a powered down state, including, for example, a variety of memories conventionally referred to as Read Only Memories (ROMs). The read-only memory includes, for example, NAND flash memory and NOR flash memory.
With the increase of hardware performance and the complication of software functions of computer systems, it is difficult to meet the requirements of computer systems on the capacity and speed of memory devices by using a single memory chip. In order to increase the capacity of the memory device, it has been proposed to stack a plurality of small-capacity memory chips together to package a single memory device. Stacking memory devices can reduce product development cycle time and chip cost compared to redesigning and manufacturing large capacity single chip memory devices.
However, existing memory chips are not designed specifically for stacked memory devices. The stacked memory device also needs to contain additional interface chips that multiplex the buses and provide separate connection terminals for the stacked memory chips, respectively. The interface chip not only causes an increase in the cost of stacked memory devices, but also causes a decrease in the data rate due to signal conversion in the multiplexed bus.
Accordingly, further improvements in the design of stacked memory devices to increase data rates and reduce device costs are desirable.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a stacked memory device, a memory chip and a control method thereof, in which memory chip embedding supports terminal multiplexing, and thus a plurality of memory chips can be directly connected in parallel in the stacked memory device to increase a data rate and reduce device cost.
According to a first aspect of the present invention, there is provided a method of controlling a memory chip, comprising: receiving a data operation instruction; judging whether the memory chip is used as a target chip or a non-target chip according to the relation between the instruction address of the data operation instruction and the chip identification of the memory chip; executing the data operation instruction under the condition that the memory chip is used as a destination chip, and storing state information generated during the data operation instruction executed by the memory chip in a state register of the memory chip; and in the case that the memory chip is a non-destination chip, discarding the data operation instruction, and synchronizing status information generated during the execution of the data operation instruction by the destination chip in a status register of the memory chip.
Preferably, the step of determining whether the memory chip is a destination chip or a non-destination chip includes: the memory chip judges whether the data operation instruction contains an instruction address; under the condition that the data operation instruction contains an instruction address, judging whether the memory chip is used as a target chip or a non-target chip according to a comparison result of the chip identification of the memory chip and the instruction address; and under the condition that the data operation instruction does not contain an instruction address, if the chip identification of the memory chip is a default value, the memory chip is a destination chip, and if the chip identification of the memory chip is not the default value, the memory chip is a non-destination chip.
Preferably, the chip identification of the memory chip is a serial number of the memory chip in the stacked memory device.
Preferably, the chip identifier of the memory chip is a serial number generated according to configuration information pre-stored in the memory chip.
Preferably, the chip identification of the memory chip is a sequence number randomly generated at a power-up stage of the stacked memory device.
Preferably, the chip identification of the memory chip is a high order address of an address range associated with the memory chip.
Preferably, in the case that the memory chip is used as a destination chip, the memory chip waits for a register reading instruction sent by a memory controller after executing the data operation instruction is completed.
Preferably, in a case where the memory chip is used as a destination chip, the memory chip enters a standby state after executing the register reading instruction.
Preferably, in the case where the memory chip is a non-destination chip, the memory chip diverts the read register to an update register instruction after the memory controller sends the read register instruction.
Preferably, the memory chip and the destination chip share an interface bus to be connected with the memory controller, and the memory chip establishes an inter-chip communication channel with the destination chip via the interface bus.
Preferably, after the memory controller sends a register reading instruction, the memory chip acquires the state information of the state register of the destination chip via the interface bus, and writes the state information into its own state register.
Preferably, in a case that the memory chip is a non-destination chip, the memory chip determines whether the destination chip executes the data operation instruction according to state information of a state register of the destination chip.
Preferably, the memory chip enters a standby state after confirming that the destination chip executes the data operation instruction.
According to a second aspect of the present invention, there is provided a memory chip comprising: the identification register is used for storing the chip identification of the memory chip; and the state register is used for storing state information related to the execution of the data operation instruction, wherein the memory chip judges whether the memory chip is used as a target chip or a non-target chip according to the relation between the chip identifier and the instruction address of the data operation instruction, and the state register is set to be in a corresponding working mode according to the judgment result so as to support terminal multiplexing when a plurality of memory chips are connected together.
Preferably, in the case that the memory chip is used as a destination chip, the status register stores status information generated during execution of the data operation instruction by itself, and in the case that the memory chip is used as a non-destination chip, the status register synchronizes status information of the status register in the destination chip during execution of the data operation instruction by the destination chip.
According to a third aspect of the present invention, there is provided a stacked memory device comprising: the above-mentioned plurality of memory chips, wherein the plurality of memory chips are stacked and packaged into a single device, connected to each other inside the stacked memory device, and execute the data operation instructions cooperatively.
Preferably, the internal structure and the terminal layout of the plurality of memory chips are identical to each other.
Preferably, the terminals of the plurality of memory chips are directly connected in parallel.
Preferably, the chip identification of the plurality of memory chips is a serial number of the plurality of memory chips in the stacked memory device.
Preferably, the chip identifiers of the plurality of memory chips are serial numbers generated according to configuration information pre-stored in the plurality of memory chips.
Preferably, the chip identifications of the plurality of memory chips are serial numbers randomly generated at a power-up stage of the stacked memory device.
Preferably, the chip identifications of the plurality of memory chips are upper addresses of address ranges respectively associated with the plurality of memory chips.
According to the stacked memory device of the embodiment of the present invention, the memory chip internally supports terminal multiplexing using different operation modes of the chip identification and status registers stored in the identification register. A plurality of memory chips may be directly connected in parallel in a stacked memory device. The stacked memory device does not need to contain a separate interface chip for signal conversion of the memory chip multiplexing bus, so that the cost rise of the stacked memory device can be reduced, and the data rate between the memory control and the stacked memory device can be improved.
According to the terminal multiplexing method of the memory chip, the memory chip obtains the address range associated with the memory chip according to the chip identification, and whether the memory chip is a target chip is judged according to the comparison between the data operation instruction address and the address range. Therefore, in the case that the stacked memory device includes a plurality of memory chips, only one memory chip is always used as a destination chip to execute the data operation instruction, the rest memory chips are used as non-destination chips to synchronize the state register of the destination chip, and after the destination chip executes the data operation instruction, all the memory chips are restored to the standby state, so that the plurality of memory chips of the stacked memory device cooperatively execute the data operation instruction to realize the embedded support terminal multiplexing. The control method of the memory chip allows a plurality of memory chips to be directly connected in parallel in the stacked memory device, and signal conversion of the memory chip multiplexing bus is not required to be carried out by containing a separate interface chip, so that the cost rise of the stacked memory device can be reduced, and the data rate between the memory control and the stacked memory device can be improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a schematic block diagram of a memory system according to an embodiment of the invention.
Fig. 2 shows a schematic block diagram of an internal structure of a memory chip in the stacked memory device.
FIG. 3 shows a flow chart of a memory chip terminal multiplexing method according to an embodiment of the invention.
Fig. 4 is a flowchart showing a destination chip determination in the memory chip terminal multiplexing method shown in fig. 3.
FIG. 5 illustrates a timing diagram for the memory chip to execute a read register instruction.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not drawn to scale. In addition, certain well known components may not be shown.
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to". In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
The following detailed description of the present invention is provided in connection with the accompanying drawings and examples.
FIG. 1 shows a schematic block diagram of a memory system according to an embodiment of the invention.
The internal structure of memory controller 120 is known in the art. By way of example, memory controller 120 includes a host interface, a memory interface, a controller, an instruction queue, an address generator, and the like.
The host interface is used to couple the storage controller 120 to a host processor, such as a CPU. The memory interface is used to couple the memory controller 120 to the memory devices. The memory controller 120 may be any type of memory controller, memory card controller, U disk controller, solid state hard disk controller, depending on the type of memory device. The bus interface between the host and the memory controller 120 includes a Universal Serial Bus (USB) interface, a memory card interface, a Serial Advanced Technology Attachment (SATA) interface, a Parallel Advanced Technology Attachment (PATA) interface, an Integrated Drive Electronics (IDE) interface, an IEEE 1394 (Fire Wire) interface, and the like. The bus interface between the memory controller 120 and the memory device is, for example, a synchronous serial interface (SPI).
The memory chips 130-1 and 130-2 may be any type of memory chips, such as Static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), NAND flash memory, and NOR flash memory.
In the present embodiment, the internal structures of the memory chips 130-1 and 130-2 in the stacked memory device 130 are the same and support the terminal multiplexing method is embedded, respectively, and thus the data operation instructions can be executed in cooperation.
Preferably, memory chips 130-1 and 130-2 are directly connected in parallel in the package of stacked memory device 130. The terminal layout of stacked memory device 130, memory chips 130-1 and 130-2 is the same, and thus, the memory device can provide a fully compatible terminal layout regardless of whether memory chips 130-1 and 130-2 are used alone or any number of memory chips make up stacked memory device 130. The manner of connection between memory controller 120 and the memory devices need not be changed.
Preferably, a synchronous serial interface (SPI) bus functions as both an address bus and a data bus. The terminals of stacked memory device 130 include power supply terminals, control signal terminals, and synchronous serial interface (SPI) terminals. The power supply terminal comprises a power supply voltage terminal VCC and a grounding terminal VSS. The control signal terminal includes a write protect signal terminal WP and a HOLD signal terminal HOLD. The synchronous serial interface (SPI) terminal comprises a serial clock signal end SCK, a slave input signal end SI, a slave output signal end SO and a chip selection signal end CS.
The plurality of memory chips simultaneously receive data operation requests of the memory controller. In the stacked memory device, a plurality of memory chips are respectively embedded in a support terminal multiplexing method, one of the plurality of memory chips is enabled according to an address of a data operation instruction, and after the data operation instruction is executed, standby states of all the memory chips are restored according to a register read instruction.
According to the memory system of the embodiment of the invention, a plurality of memory chips can be directly connected in parallel in the stacked memory device. The stacked memory device does not need to contain a separate interface chip for signal conversion of the memory chip multiplexing bus, so that the cost rise of the stacked memory device can be reduced, and the data rate between the memory control and the stacked memory device can be improved.
Fig. 2 shows a schematic block diagram of an internal structure of a memory chip in a stacked memory device.
The memory chip 130-1 includes an interface circuit 11, a control circuit 12, an address latch 13, a row decoder 14, a column decoder 15, a data buffer 16, a multiplexer 17, a memory cell array 18, and a status register 21 and an identification register 22. The control circuit 12 in the memory chip 130-1 is connected to the internal blocks.
In the present embodiment, the control circuit 12 not only provides various data operation functions of the memory device, but also judges whether or not itself is a destination chip of a data operation instruction based on the chip identification stored in the identification register 22, thereby inline supporting terminal multiplexing.
Interface circuit 11 of memory chip 130-1 is connected to terminals of stacked memory device 130, and further, interface circuit 11 is connected to a memory interface of memory controller 120 via terminals of stacked memory device 130. The interface circuitry of memory chip 130-1 is communicatively coupled to the memory interface of memory controller 120, receives data manipulation instructions and returns read data (e.g., data stored by memory cells and state information stored by a state register). For example, the data operation instruction contains an instruction code, and may further contain an additional address according to the type of the data operation request.
The address latch 13 is connected to the interface circuit 11 for storing the physical address received from the memory controller 120 and supplying the latched physical address to the row decoder 14 and the column decoder 15. The row decoder 14 and the column decoder 15 decode the physical addresses into a row address and a column address of the memory cell array 18, respectively.
The data buffer 16 is connected to the interface circuit 11 for buffering input data and output data of the memory chip. In the case of a data write command, the memory chip 130-1 receives input data from the memory controller 120, and the data buffer 16 temporarily stores the input data until the control circuit 12 executes the data write command. In the case of a data read instruction, the memory chip 130-1 sends the output data to the memory controller 120, and the data buffer 16 temporarily stores the output data until the control circuit 12 executes the data read instruction.
The multiplexer 17 is connected between the data buffer 16 and the memory cell array 18. The multiplexer 17 includes a plurality of transmission gates for combining a plurality of bit lines of the memory cell array 18 into a set of data lines. For example, the memory cell array 18 includes a plurality of memory banks that share one set of data lines via the multiplexer 17.
The status register 21 is used to store status information of the memory chip. For example, the status information is represented using a plurality of status bits. Control circuit 12 stores state information associated with the execution of the data manipulation instruction in state registers 21 at various stages of the execution of the data manipulation instruction. For example, in a data erase operation, the status information stored in the status register 21 indicates whether the erase operation is suspended and completed. The memory controller 120 reads the status information to determine whether the erase operation is completed and when the next data operation command should be sent.
In the case where the memory chip 130-1 is used as a destination chip, state information generated during execution of a data operation instruction is stored. In the case where the memory chip 130-1 is a non-destination chip, the memory chip 130-1 synchronizes the state information of the state register in the destination chip during the execution of the data operation instruction by the destination chip.
The identification register 22 is used to store the chip identification of the memory chip. For example, the chip identification is a memory chip number in the stacked memory device. A requirement for chip identification is that the order of different memory chips in a stacked memory device can be distinguished. The chip identifier may be a serial number generated according to configuration information pre-stored in the memory chip, or a serial number randomly generated by the memory chip in a power-on stage of the memory device. Preferably, the chip identification is a high order address that stores the address range associated with the chip.
According to the memory chip provided by the embodiment of the invention, the memory chip obtains the address range associated with the memory chip according to the chip identification stored by the identification register, judges whether the memory chip is a destination chip or not according to the comparison between the data operation instruction address and the address range, stores the state information generated during the execution of the data operation instruction by the memory chip when the memory chip is used as the destination chip, and synchronizes the state information of the state register in the destination chip when the memory chip is used as a non-destination chip. Thus, the memory chip internally supports terminal multiplexing with different operating modes of the chip identification and status registers stored in the identification register. A plurality of memory chips may be directly connected in parallel in a stacked memory device. The stacked memory device does not need to contain a separate interface chip for signal conversion of the memory chip multiplexing bus, so that the cost rise of the stacked memory device can be reduced, and the data rate between the memory control and the stacked memory device can be improved.
FIG. 3 shows a flow chart of a memory chip terminal multiplexing method according to an embodiment of the invention.
In step S11, the memory chip receives a data operation instruction sent by the memory controller.
As described above, in the memory system, the memory controller receives a data operation request including a read request, a write request, an erase request, a program request from the host, and generates a plurality of data operation instructions according to the data operation request. For example, the data operation instruction contains an instruction code, and may further contain an additional address according to the type of the data operation request.
In this step, after receiving the data operation instruction, the memory chip determines whether to modify the status register during execution of the data operation instruction according to the type of the data operation instruction. The data operation instruction that modifies the status register during execution of the data operation instruction includes, for example, a program instruction, an erase instruction, etc., or a direct write status register instruction of the memory controller to the memory chip.
In step S12, the memory chip determines whether it is a destination chip by using the chip identifier stored in the identifier register.
As described above, the chip identification is a memory chip number in the stacked memory device. In the case where the stacked memory device includes two memory chips, the memory chip numbers of the two memory chips may be represented by one bit, for example, a binary digit 0 represents the first chip, and a binary digit 1 represents the second chip.
In this step, the memory chip obtains an address range associated with the memory chip according to the chip identifier, and determines whether the memory chip is a destination chip according to a comparison between the data operation instruction address and the address range. For example, the address range of the first chip is 0x0000-0x0FFF, and the address range of the second chip is 0x1000-0x1FFF. If the instruction address of the data operation instruction belongs to the address range of 0x0000-0x0FFF, or the data operation instruction does not contain the instruction address, the first chip confirms that the first chip is the target chip, and the second chip confirms that the second chip is the non-target chip. If the instruction address of the data operation instruction belongs to the address range of 0x1000-0x1FFF, the first chip confirms that the first chip is a non-destination chip, and the second chip confirms that the second chip is a destination chip.
Therefore, one of the first chip and the second chip in the stacked memory device can always confirm that it is the destination chip and the other chip can always confirm that it is the non-destination chip.
Further, the destination chip executes the data operation instruction sent by the memory controller, as shown in steps S13 to S16.
In step S13, the destination chip executes a data operation instruction. In step S14, the destination chip waits for a read status register instruction from the memory controller during execution of the complete data operation instruction. In step S15, the destination chip executes the read status register instruction, and returns the status information of the status register. Then, in step S16, the destination chip enters a standby state.
Further, the non-destination chip masks the data operation command, as shown in steps S17 to S20.
In step S17, the non-destination chip discards the data operation instruction sent by the memory controller.
In step S18, the non-destination chip synchronizes the state information of the state register of the destination chip.
After the memory controller sends a register read instruction to the plurality of memory chips, only the destination chip returns register state information to the memory controller in response to the register read instruction. The non-destination chip does not execute the register reading instruction to return the register state information, and the non-destination chip turns the register reading instruction sent by the memory controller into a register updating instruction.
Furthermore, the non-destination chip establishes an inter-chip communication channel with the destination chip via an interface bus shared by the plurality of memory chips. With a similar timing sequence as the memory controller, the non-destination chip obtains the state information of the state register returned by the destination chip. Further, the non-destination chip writes the register state information of the destination chip into the state register of the non-destination chip.
Referring to FIG. 5, during execution of the read register instruction, the non-destination chip obtains the state information of the state register returned by the destination chip via the shared interface bus at substantially the same timing as the memory controller. The memory controller sends the read register command code to the plurality of memory chips of the stacked memory device via an interface bus common to the plurality of memory chips of the stacked memory device. In a first plurality of clock cycles of the serial clock signal SCK, the destination chip obtains the register command code from the input data signal SI of the stacked memory device, and in a second plurality of clock cycles of the serial clock signal SCK, the destination chip sends the state information of its own state register as the output data signal SO of the stacked memory device to the interface bus. At each rising edge of the second plurality of clock cycles (dashed line position in the timing diagram), not only does the memory controller sample the status information of the status register of the destination chip on the interface bus, but the non-destination chip samples the status information of the status register of the destination chip on the interface bus. Therefore, the data communication between the non-destination chip and the destination chip can be realized.
In step S19, the non-destination chip determines whether the destination chip completes the data operation instruction according to the status information of the status register of the destination chip. If the destination chip completes the data operation command, step S20 is executed. In step S20, the non-destination chip enters a standby state. If the destination chip does not complete the data operation instruction, returning to step S18, continuing to wait for the memory controller to execute the next register reading instruction, and after receiving the register reading instruction, synchronizing the status register of the destination chip. And repeating the step S18 until the destination register is confirmed to complete the data operation instruction according to the state information of the destination register.
According to the terminal multiplexing method of the memory chip, the memory chip obtains the address range associated with the memory chip according to the chip identification, and whether the memory chip is a target chip is judged according to the comparison between the data operation instruction address and the address range. Therefore, in the case that the stacked memory device includes a plurality of memory chips, only one memory chip is always used as a destination chip to execute the data operation instruction, the rest memory chips are used as non-destination chips to synchronize the state register of the destination chip, and after the destination chip executes the data operation instruction, all the memory chips are restored to the standby state, so that the plurality of memory chips of the stacked memory device cooperatively execute the data operation instruction to realize the embedded support terminal multiplexing. A plurality of memory chips may be directly connected in parallel in a stacked memory device. The stacked memory device does not need to contain a separate interface chip for signal conversion of the memory chip multiplexing bus, so that the cost rise of the stacked memory device can be reduced, and the data rate between the memory control and the stacked memory device can be improved.
Fig. 4 is a flowchart illustrating a destination chip determination method in the memory chip terminal multiplexing method illustrated in fig. 3.
The detailed flow of the above-described destination chip determination includes steps S101 to S105.
In step S101, the memory chip determines whether the data operation command has an address. The data operation instructions for the memory cell array include addresses, such as a read instruction, a program instruction, and an erase instruction. The operation command to the memory device does not contain an address, for example, a read memory device basic information code command or the like.
If it is confirmed in step S101 that the data operation instruction contains an instruction address, step S102 is performed. In step S102, the chip id is compared with the instruction address to determine whether the two match. For example, if an instruction address falls within address range 0x0000-0x0FFF, the instruction address matches the address range of the first chip, and if the instruction address falls within address range 0x1000-0x1FFF, the instruction address matches the address range of the second chip. If the memory chip confirms that the chip identifier matches the instruction address, step S104 is performed, otherwise step S105 is performed. In step S104, the memory chip takes itself as a destination chip of the data operation instruction. In step S105, the memory chip treats itself as a non-destination chip of the data operation instruction.
If it is confirmed in step S101 that the data operation instruction does not contain an instruction address, step S103 is performed. In step S103, the memory chip further determines whether the chip id is a default value. For example, if the value of the chip id read by the memory chip is a binary value 0, the memory chip determines that it is the first chip, and step S104 is performed, and if the value of the chip id read by the memory chip is a binary value 1, the memory chip determines that it is the second chip, and step S105 is performed. In step S104, the memory chip takes itself as a destination chip of the data operation instruction. In step S105, the memory chip takes itself as a non-destination chip of the data operation instruction.
In this embodiment, the default value of the chip identifier is 0. Thus, the first chip executes all data operation instructions that do not contain an instruction address.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (20)
1. A control method of a memory chip includes:
receiving a data operation instruction;
under the condition that the data operation instruction contains an instruction address, judging whether the memory chip is used as a target chip or a non-target chip according to a comparison result of the chip identification of the memory chip and the instruction address; or
Under the condition that the data operation instruction does not contain an instruction address, if the chip identification of the memory chip is a default value, the memory chip is a destination chip, if the chip identification of the memory chip is not the default value, the memory chip is a non-destination chip,
executing the data operation instruction under the condition that the memory chip is used as a destination chip, and storing state information generated during the data operation instruction executed by the memory chip in a state register of the memory chip; and
and in the case that the memory chip is a non-destination chip, discarding the data operation instruction, and after the memory controller sends a register reading instruction, diverting the register reading instruction to an register updating instruction, and synchronizing status information generated during the data operation instruction executed by the destination chip in a status register of the memory chip.
2. The control method according to claim 1, wherein the chip identification of the memory chip is a serial number of the memory chip in a stacked memory device.
3. The control method according to claim 1, wherein the chip identification of the memory chip is a serial number generated from configuration information stored in advance in the memory chip.
4. The control method according to claim 1, wherein the chip identification of the memory chip is a sequence number randomly generated at a power-up stage of the stacked memory device.
5. The control method of claim 1, wherein the chip identification of the memory chip is a high order address of an address range associated with the memory chip.
6. The control method according to claim 1, wherein in a case where the memory chip is a destination chip, the memory chip waits for a read register instruction sent by a memory controller after execution of the data operation instruction is completed.
7. The control method according to claim 6, wherein in a case where the memory chip is a destination chip, the memory chip enters a standby state after executing the read register instruction.
8. The control method according to claim 1, wherein the memory chip and the destination chip share an interface bus to be connected with the memory controller, and the memory chip establishes an inter-chip communication channel with the destination chip via the interface bus.
9. The control method according to claim 8, wherein the memory chip acquires the status information of the status register of the destination chip via the interface bus after the memory controller sends a register read instruction, and writes the status information into its own status register.
10. The control method according to claim 8, wherein in a case where the memory chip is a non-destination chip, the memory chip determines whether the destination chip executes the data operation instruction according to state information of a state register of the destination chip.
11. The control method according to claim 10, wherein the memory chip enters a standby state after confirming that the destination chip executes the data operation instruction.
12. A memory chip for executing the control method of any one of claims 1 to 11, comprising:
the identification register is used for storing the chip identification of the memory chip; and
a status register for storing status information relating to execution of the data operation instruction,
the memory chip judges whether the memory chip is used as a target chip or a non-target chip according to the relation between the chip identification and the instruction address of the data operation instruction, and sets the status register to be in a corresponding working mode according to the judgment result so as to support terminal multiplexing when a plurality of memory chips are connected together.
13. The memory chip of claim 12, wherein the status register stores status information generated during execution of a data operation instruction by itself in a case where the memory chip is a destination chip,
in the case that the memory chip is used as a non-destination chip, the status register synchronizes the status information of the status register in the destination chip during the execution of the data operation instruction by the destination chip.
14. A stacked memory device, comprising:
the plurality of memory chips of any one of claims 12 to 13,
wherein the plurality of memory chips are stacked and packaged into a single device, connected to each other inside the stacked memory device and cooperatively executing data operation instructions.
15. The stacked memory device of claim 14, wherein the internal structure and terminal layout of the plurality of memory chips are identical to each other.
16. The stacked memory device of claim 14, wherein the terminals of the plurality of memory chips are directly connected in parallel.
17. The stacked memory device of claim 14, wherein the chip identification of the plurality of memory chips is a serial number of the plurality of memory chips in the stacked memory device.
18. The stacked memory device of claim 17, wherein the chip identifications of the plurality of memory chips are serial numbers generated according to configuration information pre-stored in the plurality of memory chips.
19. The stacked memory device of claim 17, wherein the chip identifications of the plurality of memory chips are randomly generated sequence numbers during a power-up phase of the stacked memory device.
20. The stacked memory device of claim 17, wherein the chip identifications of the plurality of memory chips are upper addresses of address ranges respectively associated with the plurality of memory chips.
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