CN114649366A - Manufacturing method of three-dimensional memory and three-dimensional memory - Google Patents

Abstract

The embodiment of the invention discloses a three-dimensional memory and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a storage region and a counterpoint region, and a first conductive wire loop, a lower phase change storage unit and a second conductive wire loop are arranged in the storage region; forming a first groove and a second groove in the storage area and the alignment area respectively by adopting an etching process, wherein the first groove is used for removing two ends of the first conductive wire ring and two ends of the second conductive wire ring to form a first conductive wire and a second conductive wire respectively; forming a first dielectric layer which covers the semiconductor structure and fills the first groove and the second groove, wherein a gap is formed in the second groove; performing a planarization process on the first dielectric layer and the semiconductor structure to expose the second conductive line and the gap; and forming an upper phase change memory stacked material layer on the semiconductor structure, wherein a recess is formed in the upper phase change memory stacked material layer at a position above the gap, and the recess forms a first alignment mark.

Description

Manufacturing method of three-dimensional memory and three-dimensional memory

Technical Field

The invention relates to the technical field of three-dimensional memories, in particular to a manufacturing method of a three-dimensional memory and the three-dimensional memory.

Background

A three-dimensional memory (e.g., a three-dimensional phase change memory) includes a memory region for setting a device structure including a memory cell array for mainly storing data and a peripheral circuit for mainly realizing functional control of phase change memory operations (read operations, write operations, etc.), and a bit alignment region.

In the manufacturing process of the three-dimensional memory, alignment control is usually performed by using the alignment marks in the alignment area to achieve alignment between the device structures formed in the device area.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a method for manufacturing a three-dimensional memory and a three-dimensional memory to solve at least one problem in the background art.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

the embodiment of the invention provides a method for manufacturing a three-dimensional memory, which comprises the following steps:

providing a semiconductor structure, wherein the semiconductor structure comprises a storage region and a counterpoint region, and a first conductive wire loop, a lower phase change storage unit and a second conductive wire loop are arranged in the storage region from bottom to top;

forming a first groove and a second groove in the storage area and the alignment area respectively by adopting an etching process; wherein the first trench is used for removing two ends of the first conductive wire loop and the second conductive wire loop to form a first conductive wire and a second conductive wire respectively;

forming a first dielectric layer which covers the semiconductor structure and fills the first groove and the second groove; wherein, the second groove is provided with a gap which is not filled by the first dielectric layer;

performing a planarization process on the first dielectric layer and the semiconductor structure to expose the second conductive line and the gap;

and forming an upper phase change memory stacked material layer on the semiconductor structure, wherein the upper phase change memory stacked material layer is formed with a recess at a position above the gap, and the recess forms a first alignment mark.

In the above scheme, the ratio of the aspect ratio of the second trench is greater than 2.

In the above scheme, the first dielectric layer is formed on the semiconductor structure by a chemical vapor deposition method.

In the above scheme, the semiconductor structure further includes a substrate and an insulating layer formed on the substrate; wherein the first conductive line loop, the lower phase change memory cell, and the second conductive line loop are located within the insulating layer.

In the above scheme, the semiconductor structure further includes a second dielectric layer, and the second dielectric layer covers the surface of the second conductive wire loop and the surface of the insulating layer.

In the above scheme, forming a second trench in the alignment region includes: and etching and removing part of the second dielectric layer and part of the insulating layer in the alignment area to form the second groove.

In the above aspect, forming a first trench in the memory region includes: etching and removing part of the second dielectric layer, part of the insulating layer, and the two ends of the first conductive wire loop and the two ends of the second conductive wire loop which are surrounded by part of the insulating layer to form the first trench; wherein the two ends of the first loop of conductive lines are removed to form a plurality of first conductive lines extending in a first direction, and the two ends of the second loop of conductive lines are removed to form a plurality of second conductive lines extending in a second direction.

In the above scheme, performing a planarization process on the first dielectric layer and the semiconductor structure includes: and performing a grinding process on the first dielectric layer, the second dielectric layer and the insulating layer to expose the second conductive line and the gap in the second groove.

In the above scheme, after forming the upper phase change memory stack material layer, the method further includes:

etching the upper phase change storage stacked material layer and the insulating layer by taking the first alignment mark as an alignment base point to form a third groove on the alignment area, wherein the third groove forms a second alignment mark;

and etching the upper phase change storage stacked material layer on the storage area by taking the second alignment mark as an alignment base point to form a plurality of upper storage unit structural bodies extending along the second direction.

An embodiment of the present invention further provides a three-dimensional memory, including:

the semiconductor structure comprises a storage region and a counterpoint region, wherein a first conductive wire, a lower phase change storage unit and a second conductive wire are arranged in the storage region from bottom to top;

a first trench and a second trench respectively located in the storage region and the alignment region;

the first dielectric layer is used for filling the first groove and the second groove; wherein, the second groove is provided with a gap which is not filled by the first dielectric layer;

an upper phase change memory stack material layer on the semiconductor structure; wherein the upper phase change memory stacked material layer fills the gap and is formed with a recess at a position above the gap, the recess constituting a first alignment mark.

The embodiment of the invention provides a three-dimensional memory and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a storage area and a contraposition area; forming a first groove and a second groove in the storage area and the alignment area respectively by adopting an etching process; forming a first dielectric layer on the semiconductor structure, wherein the first dielectric layer fills the first groove and the second groove; wherein, the second groove is provided with a gap which is not filled by the first dielectric layer; performing a planarization process; the planarization process exposes the gap in the second trench; and forming an upper phase change memory stacked material layer on the semiconductor structure, wherein the upper phase change memory stacked material layer is formed with a recess at a position above the gap, and the recess forms a first alignment mark. According to the manufacturing method, an etching process is adopted, a first groove is formed in the storage area, a second groove is formed in the alignment area, position information of the second groove is transferred to the upper phase change storage stacked material layer through a gap formed in the second groove, and the upper phase change storage stacked material layer forms the recess of the first alignment mark.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the invention;

FIG. 2 is a schematic top view of a three-dimensional memory according to an embodiment of the invention;

fig. 3 to 9 are process flow diagrams of a three-dimensional memory according to an embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily indicate that the invention does not necessarily involve the first element, component, region, layer or section.

Spatial relational terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In some related arts, memory cells belonging to different layers in a multi-layer stacked three-dimensional memory are vertically aligned with each other, and the alignment needs to be achieved by introducing an alignment mark in a manufacturing process of the three-dimensional memory. The method for manufacturing a two-layer (2-stack) three-dimensional phase change memory will be briefly described below.

Firstly, forming a lower phase change memory unit on a substrate, wherein the lower phase change memory unit is surrounded by a dielectric layer; then, forming an alignment groove on the dielectric layer of the alignment area through an etching process; then, forming an upper phase change memory stack material layer over the lower phase change memory cell and the alignment trench, the upper phase change memory stack material layer having a recess formed based on the alignment trench, the recess serving as a first alignment mark to form a second alignment mark at the alignment region; and finally, etching the upper phase change storage stacked material layer by taking the second alignment mark as an alignment reference to form an upper storage unit aligned with the lower phase change storage unit.

However, in the related art, when the alignment trench is formed, a separate mask and etching process are required, the process is complicated, and the production efficiency is low.

Based on this, the following technical scheme of the embodiment of the invention is provided:

an embodiment of the invention provides a method for manufacturing a three-dimensional memory, and particularly refers to fig. 1. As shown, the method comprises the steps of:

step 101, providing a semiconductor structure, wherein the semiconductor structure comprises a storage region and a counterpoint region, and a first conductive wire loop, a lower phase change memory cell and a second conductive wire loop are arranged in the storage region from bottom to top;

102, forming a first groove and a second groove in the storage area and the alignment area respectively by adopting an etching process; wherein the first trench is used for removing two ends of the first conductive wire loop and the second conductive wire loop to form a first conductive wire and a second conductive wire respectively;

103, forming a first dielectric layer which covers the semiconductor structure and fills the first trench and the second trench; wherein, the second groove is provided with a gap which is not filled by the first dielectric layer;

104, performing a planarization process on the first dielectric layer and the semiconductor structure to expose the second conductive line and the gap;

step 105, forming an upper phase change memory stacked material layer on the semiconductor structure, wherein a recess is formed in the upper phase change memory stacked material layer at a position above the gap, and the recess forms a first alignment mark.

In the embodiment of the invention, an etching process is adopted, the first groove is formed in the storage area, the second groove is formed in the alignment area, and the position information of the second groove is transferred to the upper phase change storage stacked material layer by utilizing the gap formed in the second groove, namely the recess of the first alignment mark is formed.

The manufacturing method provided by the embodiment of the invention can be used for manufacturing a three-dimensional phase change memory (3D PCM). But is not limited thereto, the manufacturing method may also be used to manufacture other types of three-dimensional memories.

The following detailed description of embodiments of the invention refers to the accompanying drawings. In describing the embodiments of the present invention in detail, the drawings are not to be taken as being generally to scale, and the drawings are for illustrative purposes only and should not be construed as limiting the scope of the present invention.

FIG. 2 is a schematic top view of a three-dimensional memory according to an embodiment of the invention; fig. 3 to 9 are process flow diagrams of a three-dimensional memory according to an embodiment of the invention, in which fig. 3, 4a, 5, 6, 7, 8 and 9 are schematic cross-sectional structures of steps taken along line a-a' of fig. 2, and fig. 4b is a schematic view of a second trench according to an embodiment of the invention. The method for manufacturing the three-dimensional memory according to the embodiment of the invention is further described in detail with reference to fig. 2 to 9.

First, step 101 is executed, as shown in fig. 2 to fig. 3, a semiconductor structure 200 is provided, where the semiconductor structure 200 includes a storage region 20a and a registration region 20b, and a first conductive wire loop 25, a lower phase-change memory cell 26, and a second conductive wire loop 27 are disposed in the storage region 20a from bottom to top.

As shown in fig. 2, the alignment area 20b is disposed adjacent to the storage area 20 a. In actual processing, the semiconductor structure 200 is formed on a wafer, and includes a plurality of memory regions 20a and a plurality of alignment regions 20b, the alignment regions 20b are usually disposed on dicing streets, and the plurality of memory regions 20a can be separated into individual devices in subsequent processing steps. It should be noted that the shape of the alignment region 20b is not limited to the shape shown in fig. 2, fig. 2 is only an illustration, and a person skilled in the art can arrange the alignment region 20b in any shape as needed. In a specific embodiment, the alignment area 20b may also be in a ring shape, and the alignment area 20b is disposed around the storage area 20 a.

As shown in fig. 3, in one embodiment, the semiconductor structure 200 further includes a substrate 20 and an insulating layer 24 formed on the substrate 20; wherein the first conductive wire loop 25, the lower phase change memory cell 26 and the second conductive wire loop 27 are located within the insulating layer 24. The material of the insulating layer 24 includes, but is not limited to, insulating materials such as Tetraethylorthosilicate (TEOS), silicon dioxide, silicon nitride, or silicon oxynitride.

Here, the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a particular embodiment, the substrate is a silicon substrate, which may be doped or undoped.

As shown in fig. 2, the first conductive wire loop 25 extends along a first direction, the number of the first conductive wire loops 25 is multiple, the multiple first conductive wire loops 25 are uniformly arranged along a second direction, and each first conductive wire loop 25 has two opposite ends 251, 252; the second wire loop 27 extends along the second direction, the number of the second wire loops 27 is plural, the plural second wire loops 27 are uniformly arranged along the first direction, and each second wire loop 27 has two end portions 271, 272 arranged oppositely. Wherein the first direction is different from the second direction. In one embodiment, the first direction is perpendicular to the second direction. The material of the first conductive wire loop 25 and the second conductive wire loop 27 includes, but is not limited to, tungsten, diamond, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

The lower phase change memory cell 26 is located at the intersection of the first loop of conductive wire 25 and the second loop of conductive wire 27. In one embodiment, the lower phase-change memory cell 26 includes a first lower electrode layer 261, a lower gate layer 262, a second lower electrode layer 263, and a lower portion disposed from bottom to topA phase change memory layer 264, and a third lower electrode layer 265. The materials of the first, second, and third lower electrode layers 261, 263, and 265 may be the same. In a specific embodiment, the material of the first lower electrode layer 261, the second lower electrode layer 263 and the third lower electrode layer 265 includes a carbon material, such as amorphous carbon or carbon nanotubes. The material of the lower gate layer 262 may include any suitable Ovonic Threshold Switch (OTS) material, such as Zn_xTe_y、Ge_xTe_y、Nb_xO_y、Si_xAs_yTe_zAnd the like. The material of the lower phase-change memory layer 264 may be a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase-change material.

In one embodiment, the lower phase-change memory cell 26 further includes a first adhesive layer (not shown) on a lower surface of the first lower electrode layer 261, a first lower barrier layer (not shown) between the second lower electrode layer 263 and the lower phase-change memory layer 264, and a second lower barrier layer (not shown) between the lower phase-change memory layer 264 and the third lower electrode layer 265. The material of the first adhesive layer (not shown) includes a metal nitride, for example, tungsten nitride or titanium nitride. The material of the first lower barrier layer (not shown) and the second lower barrier layer (not shown) includes a conductive material such as tungsten, tantalum, or titanium nitride.

In an embodiment, the semiconductor structure 200 further includes a second adhesive layer (not shown) on a lower surface of the second wire loop 27, where a material of the second adhesive layer (not shown) may be the same as a material of the first adhesive layer (not shown). In some embodiments, the semiconductor structure 200 further includes a protective layer (not labeled) on a side surface of the lower phase-change memory cell 26, and a material of the protective layer (not labeled) includes silicon nitride.

In an embodiment, the semiconductor structure 200 further includes a first interlayer dielectric layer 21 and a second interlayer dielectric layer 22 between the substrate 20 and the insulating layer 24, and the second interlayer dielectric layer 22 is located on the first interlayer dielectric layer 21. In a specific embodiment, a plurality of interconnection lines 211 are disposed in the first interlayer dielectric layer 21, and the second interlayer dielectric layer 22 is used for protecting the interconnection lines 211. In a more specific embodiment, at least one of the interconnect lines 211 is electrically connected to either long side of the first conductive wire loop 25 through a contact plug 23. Here, the material of the first interlayer dielectric layer 21 and the material of the insulating layer 24 may be the same. The material of the second interlayer dielectric layer 22 may include silicon nitride. The material of the interconnection line 211 may include conductive materials such as tungsten, cobalt, copper, aluminum, graphene, or carbon nanotubes. The material of the contact plug 23 may include, but is not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

In one embodiment, the semiconductor structure 200 further includes a second dielectric layer 28, and the second dielectric layer 28 covers the surface of the second conductive wire loop 27 and the surface of the insulating layer 24. It should be noted that the second dielectric layer 28 may include a single material layer or multiple material layers, and when multiple material layers are included, the materials of the multiple material layers may be the same or different. In a specific embodiment, the material of the second dielectric layer 28 includes, but is not limited to, silicon nitride.

Next, step 102 is executed, as shown in fig. 4a to 4b, a first trench T1 and a second trench T2 are respectively formed in the storage region 20a and the alignment region 20b by using an etching process; wherein the first trench T1 is used to remove the two ends 251, 252 of the first conductive wire loop 25 and the two ends 271, 272 of the second conductive wire loop 27 to form the first conductive wire 253 and the second conductive wire 273, respectively.

In one embodiment, forming the second trench T2 in the alignment region 20b includes: and etching to remove part of the second dielectric layer 28 and part of the insulating layer 24 in the alignment region 20b, thereby forming the second trench T2. In a specific embodiment, the second dielectric layer 28 is removed from over a portion of the insulating layer 24 at the same time that the portion of the insulating layer 24 is removed.

In an embodiment, the number of the second trenches T2 is plural, and the plural second trenches T2 may constitute any one of plural alignment marks commonly used in the art. In one embodiment, a plurality of the second trenches T2 form a plurality of alignment marks as shown in fig. 4 b. The second trench T2 is subsequently filled with the first dielectric layer 29 to form the gap 31 (see fig. 5 to 6), and in a more specific embodiment, the ratio of the aspect ratio of the second trench T2 is greater than 2, wherein the ratio of the aspect ratio of the second trench T2 is not too small, and the too small aspect ratio may cause the gap 31 formed in the second trench T2 to be too small.

Referring again to fig. 2 and 4a, in one embodiment, a first trench T1 is formed in the storage area 20a, including: etching away a portion of the second dielectric layer 28, a portion of the insulating layer 24, and the two end portions 251, 252 of the first conductive line ring 25 and the two end portions 271, 272 of the second conductive line ring 27 surrounded by a portion of the insulating layer 24 in the storage region 20a to form the first trench T1; wherein the two ends 251, 252 of the first conductive wire loop 25 are removed to form a plurality of the first conductive wires 253 extending along a first direction, and the two ends 271, 272 of the second conductive wire loop 27 are removed to form a plurality of the second conductive wires 273 extending along a second direction. In a particular embodiment, the first conductive line 253 is a word line or bit line and the second conductive line 273 is a bit line or word line. More specifically, if the first conductive line 253 is a word line, the second conductive line 273 is a bit line; if the first conductive line 253 is a bit line, the second conductive line 273 is a word line.

Next, step 103 is performed, as shown in fig. 5, a first dielectric layer 29 is formed, wherein the first dielectric layer 29 covers the semiconductor structure 200 and fills the first trench T1 and the second trench T2; the second trench T2 has a gap 31 therein, which is not filled with the first dielectric layer 29.

Specifically, the first dielectric layer 29 is formed on the semiconductor structure 200 by chemical vapor deposition. The gap 31 is formed because the first dielectric layer 29 cannot completely fill the second trench T2 due to the large aspect ratio of the second trench T2. The material of the first dielectric layer 29 may be an oxide, such as silicon oxide.

Next, in step 104, as shown in fig. 6, a planarization process is performed on the first dielectric layer 29 and the semiconductor structure 200 to expose the second conductive lines 273 and the gaps 31.

Specifically, performing a planarization process on the first dielectric layer 29 and the semiconductor structure 200 includes: a grinding process is performed on the first dielectric layer 29, the second dielectric layer 28 and the insulating layer 24 to expose the second conductive line 273 and the slit 31 within the second trench T2. The planarization process includes a chemical mechanical polishing process, an etch back process, or a combination thereof.

Finally, step 105 is executed, as shown in fig. 7, forming an upper phase change memory stack material layer 32 on the semiconductor structure 200, wherein the upper phase change memory stack material layer 32 is formed with a recess 35 at a position above the slit 31, and the recess 35 constitutes a first alignment mark.

As such, the position information of the second trench T2 is transferred onto the upper phase change memory stack material layer 32 through the recess 35. In one embodiment, the upper phase-change memory stack material layer 32 includes a first upper electrode material layer 321, an upper gate material layer 322, a second upper electrode material layer 323, an upper phase-change memory material layer 324, a third upper electrode material layer 325 and a third dielectric layer 326 disposed from bottom to top, and the third dielectric layer 326 is used for protecting the material layer located thereunder. The first, second, and third upper electrode material layers 321, 323, and 325 may be the same material. In a specific embodiment, the material of the first upper electrode material layer 321, the second upper electrode material layer 323, and the third upper electrode material layer 325 includes a carbon material, such as amorphous carbon or carbon nanotubes. The material of the upper gate material layer 322 may comprise any suitable Ovonic Threshold Switch (OTS) material, such as Zn_xTe_y、Ge_xTe_y、Nb_xO_y、Si_xAs_yTe_zAnd the like. The material of the upper phase-change memory material layer 324 may be a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase-change material. The material of the third dielectric layer 326 may be silicon nitride.

In an embodiment, the upper phase change memory stack material layer 32 further includes a third adhesive layer (not shown) on a lower surface of the first upper electrode material layer 321, a first upper barrier material layer (not shown) between the second upper electrode material layer 323 and the upper phase change memory material layer 324, and a second upper barrier material layer (not shown) between the upper phase change memory material layer 324 and the third upper electrode material layer 325. The material of the third adhesive material layer may be the same as the material of the first adhesive layer. The first upper barrier material layer (not shown) and the second upper barrier material layer (not shown) may be the same material as the first lower barrier layer.

The above layers are formed using one or more thin film deposition processes; specifically, the formation process of each layer structure includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

In an embodiment, after forming the upper phase change memory stack material layer 32, the method further comprises:

etching the upper phase change memory stack material layer 32 and the insulating layer 24 with the first alignment mark as an alignment base point to form a third trench T3 on the alignment region 20b, wherein the third trench T3 constitutes a second alignment mark, as shown in fig. 8; the second alignment mark may be any alignment mark commonly used in the art;

etching the upper phase change memory stack material layer 32 on the memory region 20a with the second alignment mark as an alignment base point to form a plurality of upper memory cell structures 36 extending in the second direction, as shown in fig. 9.

In one embodiment, after the forming of the upper memory cell structure body, the method further includes:

forming a third conductive material layer on the upper memory cell structure;

and etching the third conductive material layer and the upper storage unit structural body to form a third conductive line and an upper phase change storage unit, wherein the third conductive line extends along the first direction, and the upper phase change storage unit and the lower phase change storage unit are in one-to-one correspondence.

It can be seen that, in the embodiment of the present invention, an etching process is adopted, the first trench T1 is formed in the storage region 20a, the second trench T2 is formed in the alignment region 20b, and the position information of the second trench T2 is transferred to the upper phase change memory stack material layer 32, that is, the recess 35 forming the first alignment mark, by using the slit 31 formed in the second trench T2, so that a mask process for forming the alignment mark can be omitted, the manufacturing process of the three-dimensional memory can be simplified, and the production efficiency of the three-dimensional memory can be improved.

It should be noted that a person skilled in the art is able to make possible variations between the sequences of steps described above without departing from the scope of protection of the invention.

The present invention also provides a three-dimensional memory, as shown in fig. 7, including: the semiconductor structure 200 comprises a storage region 20a and a registration region 20b, wherein a first conductive line 253, a lower phase-change memory unit 26 and a second conductive line 273 are arranged in the storage region 20a from bottom to top; a first trench T1 and a second trench T2 located in the storage region 20a and the alignment region 20b, respectively; a first dielectric layer 29 filling the first trench T1 and the second trench T2; wherein, the second trench T2 has a gap 31 not filled by the first dielectric layer 29; an upper phase change memory stack material layer 32 on the semiconductor structure 200; wherein the upper phase change memory stack material layer 32 fills the gap 31 and is formed with a recess 35 at a position above the gap 31, the recess 35 constituting a first alignment mark.

In one embodiment, the alignment area 20b is disposed adjacent to the storage area 20 a. In actual processing, the semiconductor structure 200 is formed on a wafer, and includes a plurality of memory regions 20a and a plurality of alignment regions 20b, the alignment regions 20b are usually disposed on dicing streets, and the plurality of memory regions 20a can be separated into individual devices in subsequent processing steps. It should be noted that the shape of the alignment region 20b is not limited to the shape shown in fig. 2, fig. 2 is only an illustration, and a person skilled in the art can arrange the alignment region 20b in any shape as needed. In a specific embodiment, the alignment area 20b may also be in a ring shape, and the alignment area 20b is disposed around the storage area 20 a.

In one embodiment, the semiconductor structure 200 further includes a substrate 20 and an insulating layer 24 formed on the substrate 20; wherein the first conductive line 253, the lower phase-change memory cell 26, and the second conductive line 273 are located within the insulating layer 24. The material of the insulating layer 24 includes, but is not limited to, insulating materials such as Tetraethylorthosilicate (TEOS), silicon dioxide, silicon nitride, or silicon oxynitride.

Here, the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a particular embodiment, the substrate is a silicon substrate, which may be doped or undoped.

In an embodiment, the first conductive lines 253 extend along a first direction, the number of the first conductive lines 253 is multiple, and the first conductive lines 253 are uniformly arranged along a second direction; the second conductive lines 273 extend along the second direction, the number of the second conductive lines 273 is multiple, and the plurality of second conductive lines 273 are uniformly arranged along the first direction. Wherein the first direction is different from the second direction, for example, the first direction may be perpendicular to the second direction. In a specific embodiment, the first conductive line 253 is a word line or bit line and the second conductive line 273 is a bit line or word line. More specifically, if the first conductive line 253 is a word line, the second conductive line 273 is a bit line; if the first conductive line 253 is a bit line, the second conductive line 273 is a word line. The material of the first and second conductive lines 253, 273 includes, but is not limited to, tungsten, diamond, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

The lower phase change memory cell 26 is located at the intersection of the first conductive line 253 and the second conductive line 273. In one embodiment, the lower phase-change memory cell 26 includes a first lower electrode layer 261, a lower gate layer 262, a second lower electrode layer 263, a lower phase-change memory layer 264, and a third lower electrode layer 265 disposed from bottom to top. The materials of the first, second, and third lower electrode layers 261, 263, and 265 may be the same. In a specific embodiment, the material of the first lower electrode layer 261, the second lower electrode layer 263 and the third lower electrode layer 265 includes a carbon material, such as amorphous carbon or carbon nanotubes. The material of the lower gate layer 262 may include any suitable Ovonic Threshold Switch (OTS) material, such as Zn_xTe_y、Ge_xTe_y、Nb_xO_y、Si_xAs_yTe_zAnd the like. The material of the lower phase-change memory layer 264 may be a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase-change material.

In one embodiment, the lower phase-change memory cell 26 further includes a first adhesive layer (not shown) on a lower surface of the first lower electrode layer 261, a first lower barrier layer (not shown) between the second lower electrode layer 263 and the lower phase-change memory layer 264, and a second lower barrier layer (not shown) between the lower phase-change memory layer 264 and the third lower electrode layer 265. The material of the first adhesive layer (not shown) includes a metal nitride, for example, tungsten nitride or titanium nitride. The material of the first lower barrier layer (not shown) and the second lower barrier layer (not shown) includes a conductive material such as tungsten, tantalum, or titanium nitride.

In an embodiment, the semiconductor structure 200 further includes a second adhesive layer (not shown) on the lower surface of the second conductive line 273, where the material of the second adhesive layer (not shown) may be the same as the material of the first adhesive layer (not shown). In some embodiments, the semiconductor structure 200 further includes a protective layer (not shown) on a side surface of the lower phase-change memory cell 26, wherein a material of the protective layer (not shown) includes silicon nitride.

In an embodiment, the semiconductor structure 200 further includes a first interlayer dielectric layer 21 and a second interlayer dielectric layer 22 between the substrate 20 and the insulating layer 24, and the second interlayer dielectric layer 22 is located on the first interlayer dielectric layer 21. In a specific embodiment, a plurality of interconnection lines 211 are disposed in the first interlayer dielectric layer 21, and the second interlayer dielectric layer 22 is used for protecting the interconnection lines 211. In a more specific embodiment, at least one of the interconnection lines 211 is electrically connected to any one of the first conductive lines 253 through a contact plug 23. Here, the material of the first interlayer dielectric layer 21 and the material of the insulating layer 24 may be the same. The material of the second interlayer dielectric layer 22 may include silicon nitride. The material of the interconnection line 211 may include conductive materials such as tungsten, cobalt, copper, aluminum, graphene, or carbon nanotubes. The material of the contact plug 23 may include, but is not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

In an embodiment, the first trench T1 is used to form the first conductive line 253 and the second conductive line 273, and the second trench T2 and the first trench T1 are formed by a single etching process. In an embodiment, the number of the second trenches T2 is plural, and the plural second trenches T2 may constitute plural alignment marks of any kind commonly used in the art, for example, the plural second trenches T2 constitute plural alignment marks as shown in fig. 4 b. In a specific embodiment, the ratio of the aspect ratio of the second trench T2 is greater than 2. More specifically, the first dielectric layer 29 is formed on the semiconductor structure 200 by using a chemical vapor deposition method. The gap 31 is formed because the first dielectric layer 29 cannot completely fill the second trench T2 due to the large aspect ratio of the second trench T2. The material of the first dielectric layer 29 may be an oxide, such as silicon oxide.

The upper phase change memory stack material layer 32 covers the second conductive line 273, the insulating layer 24, the first dielectric layer 29. In an embodiment, the upper phase change memory stack material layer 32 includes a first upper electrode material layer 321, an upper gate material layer 322, a second upper electrode material layer 323, an upper phase change memory material layer 324, a third upper electrode material layer 325 and a third dielectric layer 326 disposed from bottom to top, and the third dielectric layer 326 is used for protecting the material layer located therebelow. The first, second, and third upper electrode material layers 321, 323, and 325 may be the same material. In one embodiment, the material of the first upper electrode material layer 321, the second upper electrode material layer 323, and the third upper electrode material layer 325 includes a carbon material, such as amorphous carbon or carbon nanotubes. The material of the upper gate material layer 322 may comprise any suitable Ovonic Threshold Switch (OTS) material, such as Zn_xTe_y、Ge_xTe_y、Nb_xO_y、Si_xAs_yTe_zAnd the like. The material of the upper phase-change memory material layer 324 may be a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase-change material. The material of the third dielectric layer 326 may be silicon nitride.

In an embodiment, the upper phase change memory stack material layer 32 further includes a third adhesive layer (not shown) on a lower surface of the first upper electrode material layer 321, a first upper barrier material layer (not shown) between the second upper electrode material layer 323 and the upper phase change memory material layer 324, and a second upper barrier material layer (not shown) between the upper phase change memory material layer 324 and the third upper electrode material layer 325. The material of the third adhesive material layer may be the same as the material of the first adhesive layer. The first upper barrier material layer (not shown) and the second upper barrier material layer (not shown) may be the same material as the first lower barrier layer.

In the embodiment of the present invention, an etching process is adopted to form the first trench T1 in the storage region 20a and simultaneously form the second trench T2 in the alignment region 20b, and the position information of the second trench T2 is transferred to the upper phase change storage stacked material layer 32, i.e., the recess 35 forming the first alignment mark, by using the slit 31 formed in the second trench T2, so that a mask process for forming the alignment mark can be omitted in the process of forming the three-dimensional memory in the embodiment of the present invention, which is beneficial to simplifying the manufacturing process of the three-dimensional memory and improving the production efficiency of the three-dimensional memory.

In an embodiment, the upper phase-change memory stack material layer 32 and the insulating layer 24 may be etched using the first alignment mark as an alignment base point to form a third trench T3 on the alignment region 20b, so as to form the structure shown in fig. 8; the third trench T3 constitutes a second alignment mark, which may be any alignment mark commonly used in the art; next, the upper phase-change memory stacked material layer 32 on the memory area 20a is etched using the second alignment mark as an alignment base point to form a plurality of upper memory cell structure bodies 36 extending in the second direction, and finally the structure shown in fig. 9 is formed.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.

Claims (10)

1. A method of fabricating a three-dimensional memory, comprising:

providing a semiconductor structure, wherein the semiconductor structure comprises a storage region and a counterpoint region, and a first conductive wire loop, a lower phase change storage unit and a second conductive wire loop are arranged in the storage region from bottom to top;

forming a first groove and a second groove in the storage area and the alignment area respectively by adopting an etching process; wherein the first trench is used for removing two ends of the first conductive wire loop and the second conductive wire loop to form a first conductive wire and a second conductive wire respectively;

forming a first dielectric layer which covers the semiconductor structure and fills the first groove and the second groove; wherein, the second groove is provided with a gap which is not filled by the first dielectric layer;

performing a planarization process on the first dielectric layer and the semiconductor structure to expose the second conductive line and the gap;

and forming an upper phase change memory stacked material layer on the semiconductor structure, wherein a recess is formed in the upper phase change memory stacked material layer at a position above the gap, and the recess forms a first alignment mark.

2. The method of claim 1, wherein a ratio of an aspect ratio of the second trench is greater than 2.

3. The method of claim 1, wherein the first dielectric layer is formed on the semiconductor structure using a chemical vapor deposition process.

4. The method of claim 1, wherein the semiconductor structure further comprises a substrate and an insulating layer formed on the substrate; wherein the first conductive line loop, the lower phase change memory cell, and the second conductive line loop are located within the insulating layer.

5. The method of claim 4, wherein the semiconductor structure further comprises a second dielectric layer covering a surface of the second conductive wire loop and a surface of the insulating layer.

6. The method of claim 5, wherein forming a second trench in the registration region comprises: and etching and removing part of the second dielectric layer and part of the insulating layer in the alignment area to form the second groove.

7. The method of claim 5, wherein forming a first trench within the storage region comprises: etching and removing a part of the second dielectric layer, a part of the insulating layer, and the two ends of the first conductive wire loop and the two ends of the second conductive wire loop which are surrounded by the insulating layer to form the first trench; wherein the two ends of the first loop of conductive lines are removed to form a plurality of first conductive lines extending in a first direction, and the two ends of the second loop of conductive lines are removed to form a plurality of second conductive lines extending in a second direction.

8. The method of claim 5, wherein performing a planarization process on the first dielectric layer and the semiconductor structure comprises: and performing a grinding process on the first dielectric layer, the second dielectric layer and the insulating layer to expose the second conductive line and the gap in the second groove.

9. The method of claim 4, wherein after forming the upper phase change memory stack material layer, the method further comprises:

etching the upper phase change storage stacked material layer and the insulating layer by taking the first alignment mark as an alignment base point to form a third groove on the alignment area, wherein the third groove forms a second alignment mark;

and etching the upper phase change storage stacked material layer on the storage area by taking the second alignment mark as an alignment base point to form a plurality of upper storage unit structural bodies extending along the second direction.

10. A three-dimensional memory, comprising:

the semiconductor structure comprises a storage region and a counterpoint region, wherein a first conductive wire, a lower phase change storage unit and a second conductive wire are arranged in the storage region from bottom to top;

a first trench and a second trench respectively located in the storage region and the alignment region;

the first dielectric layer is used for filling the first groove and the second groove; wherein, the second groove is provided with a gap which is not filled by the first dielectric layer;

an upper phase change memory stack material layer on the semiconductor structure; wherein the upper phase change memory stacked material layer fills the gap and is formed with a recess at a position above the gap, the recess constituting a first alignment mark.

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