CN114637710B - High-speed data acquisition and processing system based on heterogeneous platform - Google Patents
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Abstract
The invention relates to the technical field of network on chip, in particular to a high-speed data acquisition and processing system based on a heterogeneous platform, which comprises a data acquisition subsystem, a processing subsystem, a cache controller resource node and an external storage, wherein the data acquisition subsystem comprises a router group and an external ADC (analog to digital converter), the router group is used as a lower computer, the processing subsystem is used as an upper computer, and the cache controller resource node is additionally arranged between the router group and the processing subsystem, so that the processing subsystem is connected with the router group through the cache controller resource node, the data interaction through one interface is realized, and the problem that the parallel interfaces of the lower computer and the upper computer are more and the system power consumption and the overall development difficulty are increased is solved.
Description
Technical Field
The invention relates to the technical field of network on chip, in particular to a high-speed data acquisition and processing system based on a heterogeneous platform.
Background
With the development of science and technology, the requirements of data acquisition on performance indexes such as sampling rate and resolution of Analog-to-digital conversion chips (ADC) are increasing.
Network-on-Chip (NoC) technology references and absorbs packet switching and routing technologies in computer Network communication, so that communication efficiency is greatly improved. The system reusability is greatly enhanced by adopting a mode of separating the IP core from the communication network. By adopting the global asynchronous local synchronous (GloballyAsynchronous and Locally Synchronous, GALS) communication technology, the generation of a huge clock tree is avoided, so that the power consumption of the clock network is reduced.
The network-on-chip technology and the time-alternating sampling technology are combined to realize high-speed data acquisition, so that the advantages of the network-on-chip are fully utilized, the communication bandwidth and the communication speed are expanded, and the resource nodes are expanded more flexibly. The interaction interface between the NoC high-speed data acquisition subsystem and the upper computer plays an important role in the whole high-speed data acquisition subsystem, the NoC high-speed data acquisition subsystem is mapped into resource nodes in the NoC system design, whether data acquired by the ADC can be cached and transmitted to the upper computer or not is determined, and the data throughput rate, the data transmission delay and the system power consumption of the whole system are significantly influenced. At present, the high-speed data acquisition and processing system of the NoC adopts a mode of combining a lower computer with an upper computer, the lower computer is responsible for acquiring the high-speed data, the upper computer is responsible for processing the acquired data, and the upper computer is usually mainly a personal computer (Personal Computer, PC), so that external interface protocols such as gigabit Ethernet, tera Ethernet and PCIe are needed to pass through the data of the lower computer, but the communication mode of the lower computer and the upper computer is more than that of internal parallel interfaces, the problems of slow speed, large delay and complex protocol exist, and the interfaces consume more logic resources in an FPGA chip, so that the system power consumption and the overall development difficulty are increased.
Disclosure of Invention
The invention aims to provide a high-speed data acquisition and processing system based on a heterogeneous platform, which aims to solve the problem that more parallel interfaces of a lower computer and an upper computer can cause increase of system power consumption and overall development difficulty.
In order to achieve the above purpose, the invention provides a high-speed data acquisition and processing system based on a heterogeneous platform, which comprises a data acquisition subsystem, a processing subsystem, a cache controller resource node and an external storage, wherein the data acquisition subsystem, the cache controller resource node, the processing subsystem and the external storage are sequentially connected;
the data acquisition subsystem comprises a router group and an external ADC, and the router group is connected with the external ADC;
the router group is used for acquiring the digital signals, obtaining data packets and transmitting the data packets to the resource nodes of the cache controller;
the buffer controller resource node is used for resolving and converting the data packet to obtain matching data and sending the matching data to the processing subsystem;
the processing subsystem is used for sending the matching data to the external storage in a direct memory access mode;
the external memory is used for storing the matching data.
The buffer controller resource node comprises a frame analysis module and an AXI system module, and the frame analysis module is connected with the AXI system module;
the frame analysis module is used for analyzing the data packet and then converting the data packet to obtain converted data;
and the AXI system module is used for configuring a register and arbitrating the conversion data to obtain matching data and transmitting the matching data to the processing subsystem.
The frame analysis module comprises an analysis unit and a bit width conversion unit, and the analysis unit is connected with the bit width conversion unit;
the analyzing unit is used for analyzing the data packet to obtain analysis data, and removing the frame head and the frame tail of the analysis data to obtain original data;
the bit width conversion unit converts the bit width of the original data based on the bit width of the AXI system module to obtain converted data.
The AXI system module comprises an AXI interconnection unit and an AXI bus register configuration unit;
the AXI interconnection unit is used for receiving the conversion data and transmitting the conversion data to the AXI bus register configuration unit;
the AXI bus register configuration unit is used for configuring registers and arbitration for the conversion data to obtain matching data, and sending the matching data to the processing subsystem.
According to the high-speed data acquisition and processing system based on the heterogeneous platform, the router group acquires ADC data and transmits the data packet to the resource node of the cache controller; the cache controller resource node analyzes and converts the data packet to obtain matching data, and sends the matching data to the processing subsystem; the processing subsystem sends the matching data to the external storage in a direct memory access mode; the external storage stores the matching data, the router group is used as a lower computer, the processing subsystem is used as an upper computer, and the cache controller resource node is additionally arranged between the router group and the processing subsystem, so that the processing subsystem is connected with the router group through the cache controller resource node, data interaction is realized through one interface, and the problem that the parallel interfaces of the lower computer and the upper computer can cause the increase of system power consumption and overall development difficulty is solved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a high-speed data acquisition and processing system based on a heterogeneous platform according to the present invention.
FIG. 2 is a schematic diagram of a cache controller resource node.
Fig. 3 is a schematic diagram of a frame parsing module.
Fig. 4 is a schematic diagram of the architecture of the AXI system module.
Fig. 5 is a port schematic diagram of a frame parsing module.
Fig. 6 is a port schematic diagram of an AXI system module.
The system comprises a 1-data acquisition subsystem, a 2-processing subsystem, a 3-external storage, a 4-router group, a 5-buffer controller resource node, a 6-frame analysis module, a 7-AXI system module, an 8-analysis unit, a 9-bit width conversion unit, a 10-AXI interconnection unit, an 11-AXI bus register configuration unit and a 12-external ADC.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
Referring to fig. 1 to 5, the present invention provides a high-speed data acquisition and processing system based on heterogeneous platform, which includes a data acquisition subsystem 1, a processing subsystem 2, a cache controller resource node 5 and an external storage 3, wherein the data acquisition subsystem 1, the cache controller resource node 5, the processing subsystem 2 and the external storage 3 are sequentially connected;
the data acquisition subsystem 1 comprises a router group 4 and an external ADC12, wherein the router group 4 is connected with the external ADC 12;
the external ADC12 for converting an analog signal into a digital signal;
the router group 4 is configured to obtain the digital signal, obtain a data packet, and transmit the data packet to the cache controller resource node 5;
the buffer controller resource node 5 is configured to parse the data packet, convert the parsed data packet to obtain matching data, and send the matching data to the processing subsystem 2;
the processing subsystem 2 is configured to send the matching data to the external storage 3 through a direct memory access manner;
the external memory 3 is used for storing the matching data.
Specifically, the router group 4 collects the digital signal converted by the external ADC12 from the analog signal, obtains a data packet, and transmits the data packet to the resource node 5 of the cache controller; the cache controller resource node 5 analyzes and converts the data packet to obtain matching data, and sends the matching data to the processing subsystem 2; the processing subsystem 2 sends the matching data to the external storage 3 by means of direct memory access; the external storage 3 stores the matching data, the router group 4, the cache controller resource node 5 and the processing subsystem 2 belong to the same chip, the chip is a DDR SDRAM chip, the router group 4 is used as a lower computer, the processing subsystem 2 is used as an upper computer, and the cache controller resource node 5 is additionally arranged between the router group 4 and the processing subsystem 2, so that the processing subsystem 2 is connected with the router group 4 through the cache controller resource node 5, data interaction is realized through one interface, and the problem that the parallel interfaces of the lower computer and the upper computer can cause increase of system power consumption and overall development difficulty is solved.
Further, the buffer controller resource node 5 includes a frame parsing module 6 and an AXI system module 7, where the frame parsing module 6 is connected with the AXI system module 7;
the frame parsing module 6 is configured to parse the data packet and then convert the parsed data packet to obtain converted data;
the AXI system module 7 is configured to configure registers and arbitrate for the conversion data to obtain matching data, and send the matching data to the processing subsystem 2.
The frame analysis module 6 comprises an analysis unit 8 and a bit width conversion unit 9, and the analysis unit 8 is connected with the bit width conversion unit 9;
the parsing unit 8 is configured to parse the data packet to obtain parsed data, and remove a frame header and a frame tail of the parsed data to obtain original data;
the bit width conversion unit 9 converts the bit width of the original data based on the bit width of the AXI system module 7 to obtain converted data.
The AXI system module 7 comprises an AXI interconnection unit 10 and an AXI bus register configuration unit 11;
the AXI interconnection unit 10 is configured to receive the conversion data and transmit the conversion data to the AXI bus register configuration unit 11;
the AXI bus register configuration unit 11 is configured to configure registers and arbitrate for the conversion data, obtain matching data, and send the matching data to the processing subsystem 2.
Specifically, the router group 4 sends a data packet to the frame parsing module 6 of the cache controller resource node 5, the parsing unit 8 of the frame parsing module 6 is responsible for parsing the data packet sent by the router into original data, then the bit width of the original data is converted into the bit width of the adaptive AXI system module 7 by the bit width converting unit 9 through the FIFO, so as to obtain converted data, then the converted data is sent to the AXI bus register configuration unit 11 by the AXI interconnection unit 10 of the AXI system module 7, the AXI bus register configuration unit 11 configures registers required by the AXI function for the converted data and multi-AXI arbitration, so as to obtain matched data, then the matched data is sent to the processing subsystem 2, the processing subsystem 2 sends the data to the external storage 3 for caching by the way of direct memory access (DirectMemoryAccess, DMA), and then waits for the upper computer system to read the data in the external storage 3 to the processing subsystem 2 for DMA processing the data by the way of the cache system. FIFO depths up to 4,194,304 words FIFO data widths from 1 to 1024 bits (for native FIFO configurations), a maximum of 4096 bits (for AXI FIFO configurations) asymmetric aspect ratio (read/write port ratio range 1:8 to 8:1), AXI (Advanced eXtensible Interface) is a bus protocol.
In fig. 5, the signal port of the frame parsing module 6 is explained as follows:
router_clk: the synchronized router group 4 clocks.
rst_n: the clock synchronization completion signal serves as a reset for the router group 4.
s_axi_rx_valid: and inputting a flit valid flag signal. The flit data is transmitted by the router group 4.
s_axi_rx_flit [ n-1:0]: flit data is entered. Transmitted by the router group 4 along with the flit valid flag signal.
m_axi_tx_valid: and analyzing the frame head and the frame tail and carrying out effective flag signals of converted data after the bit width conversion. This signal will be passed to AXI system module 7.
m_axi_tx_data [ n-1:0]: and analyzing the frame head and the frame tail and performing conversion data after the bit width conversion. And passes this data to AXI system module 7.
In fig. 6, the signal ports of the AXI system module 7 are explained as follows:
router_clk: the synchronized router group 4 clocks.
rst_n: the clock synchronization completion signal serves as a reset for the router group 4.
s_axi_rx_valid: the frame analysis module 6 sends the converted data valid flag signal after analysis.
s_axi_rx_data [ n-1:0]: the frame analysis module 6 transmits the analyzed conversion data.
axi_awaddr [ m-1:0]: write address signals of the AXI bus. The write address signal gives the first transport address of the write burst. The associated control signal lines in the AXI system module 7 are used to determine the remaining transport addresses in the burst.
axi_awvalid [ m-1:0]: the write address valid flag signal of the AXI bus. This signal indicates that the write address valid and control signals are available in AXI system module 7. This signal remains active until the response signal axi_awready is high.
axi_awready: the write address ready signal of the AXI bus. This signal indicates that the PS-side slave is ready to accept an address and associated control signals.
axi_wdata [ n-1:0]: write data signals of the AXI bus. The write data bus may be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide.
axi_wlast: the AXI bus writes the last data flag signal. Representing the last transmission in the write burst.
axi_wvalid: the write data valid flag signal of the AXI bus. This signal indicates that the required write-valid data and strobe is available.
axi_wreready: the write data ready signal of the AXI bus. This signal indicates that the PS-side slave can accept write data.
The beneficial effects are that:
1. the volume of the whole hardware platform of the high-speed data acquisition and processing system is reduced.
2. The structure ensures that the communication speed of the lower computer and the upper computer of the high-speed data acquisition and processing system is high, the time delay is small, the protocol is simple, the logic resource in the FPGA chip is saved, and the system power consumption and the overall development difficulty are greatly reduced.
While the invention has been described with respect to a preferred embodiment of a heterogeneous platform based high speed data acquisition and processing system, it will be understood by those skilled in the art that the present invention is not limited thereto, and that all or a portion of the process steps may be performed according to the present invention as defined by the appended claims.
Claims (4)
1. A high-speed data acquisition and processing system based on heterogeneous platform is characterized in that,
the system comprises a data acquisition subsystem, a processing subsystem, a cache controller resource node and an external storage, wherein the data acquisition subsystem, the cache controller resource node, the processing subsystem and the external storage are sequentially connected;
the data acquisition subsystem comprises a router group and an external ADC, and the router group is connected with the external ADC;
the external ADC is used for converting the analog signal into a digital signal;
the router group is used for acquiring the digital signals, obtaining data packets and transmitting the data packets to the resource nodes of the cache controller;
the buffer controller resource node is used for resolving and converting the data packet to obtain matching data and sending the matching data to the processing subsystem;
the processing subsystem is used for sending the matching data to the external storage in a direct memory access mode;
the external memory is used for storing the matching data.
2. The heterogeneous platform based high-speed data acquisition and processing system of claim 1,
the buffer controller resource node comprises a frame analysis module and an AXI system module, and the frame analysis module is connected with the AXI system module;
the frame analysis module is used for analyzing the data packet and then converting the data packet to obtain converted data;
and the AXI system module is used for configuring a register and arbitrating the conversion data to obtain matching data and transmitting the matching data to the processing subsystem.
3. A heterogeneous platform based high speed data acquisition and processing system as recited in claim 2, wherein,
the frame analysis module comprises an analysis unit and a bit width conversion unit, and the analysis unit is connected with the bit width conversion unit;
the analyzing unit is used for analyzing the data packet to obtain analysis data, and removing the frame head and the frame tail of the analysis data to obtain original data;
the bit width conversion unit converts the bit width of the original data based on the bit width of the AXI system module to obtain converted data.
4. A heterogeneous platform based high speed data acquisition and processing system as recited in claim 2, wherein,
the AXI system module comprises an AXI interconnection unit and an AXI bus register configuration unit;
the AXI interconnection unit is used for receiving the conversion data and transmitting the conversion data to the AXI bus register configuration unit;
the AXI bus register configuration unit is used for configuring registers and arbitration for the conversion data to obtain matching data, and sending the matching data to the processing subsystem.
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| CN111475460A (en) * | 2020-04-06 | 2020-07-31 | 桂林电子科技大学 | High-speed data acquisition system and upper computer communication interface controller based on NoC |
| CN113093585A (en) * | 2021-03-03 | 2021-07-09 | 桂林电子科技大学 | High-speed data acquisition system and upper computer communication interface controller based on NoC |
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| US8559333B2 (en) * | 2009-07-24 | 2013-10-15 | Broadcom Corporation | Method and system for scalable switching architecture |
| US11580054B2 (en) * | 2018-08-24 | 2023-02-14 | Intel Corporation | Scalable network-on-chip for high-bandwidth memory |
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| CN111475460A (en) * | 2020-04-06 | 2020-07-31 | 桂林电子科技大学 | High-speed data acquisition system and upper computer communication interface controller based on NoC |
| CN113093585A (en) * | 2021-03-03 | 2021-07-09 | 桂林电子科技大学 | High-speed data acquisition system and upper computer communication interface controller based on NoC |
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