CN114637697A - Data stream processing device, processing method, chip and electronic equipment - Google Patents
Data stream processing device, processing method, chip and electronic equipment Download PDFInfo
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Abstract
The present disclosure relates to the technical field of data stream processing, and provides a data stream processing apparatus, a processing method, a chip and an electronic device, wherein the apparatus comprises: the bit complementing unit is used for complementing the original data stream of which the initial bit width is smaller than a set value, adjusting the bit width of the original data stream to the set value, and outputting the complemented data stream and the initial bit width; the FIFO device is used for receiving the selected data stream and the initial bit width, determining a write address corresponding to the original data stream of the selected data stream according to the current depth pointer, the current bit pointer and the initial bit width of the FIFO device, and writing the original data stream of the selected data stream into the FIFO device in parallel according to the write address. The device of the embodiment of the disclosure greatly reduces the total combinational logic amount, and reduces the area of the chip by 70% under a specific process, thereby saving the cost.
Description
Technical Field
The present disclosure relates to the field of data stream processing technologies, and in particular, to a data stream processing apparatus, a data stream processing method, a chip, and an electronic device.
Background
A DPU (Data Processing Unit) or other large chip needs to support multiple different types of encoders, and the core algorithm of each encoder is different, so that the bit width of the Data stream output by each encoder is different; in addition, since the encoder needs to support data packets with different lengths, the data bit width of the last clock cycle is not long, and therefore, a conventional barrel-shaped shift register is arranged behind the encoder and used for reshaping different data formats into a uniform data stream format so as to be used by downstream logic. With the increasing complexity of the algorithm, the bit width of the data stream is larger and larger, which results in larger and larger chip area consumed by data stream processing.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a data stream processing apparatus and a data stream processing method, so as to solve the problem in the prior art that due to increasing complexity of an algorithm, bit width of a data stream is increasing, and chip area consumed by data stream processing is also increasing.
In a first aspect of the disclosed embodiments, there is provided a data stream processing apparatus comprising at least two encoders, a complementary bit unit, a mode selection unit, and a FIFO device, wherein,
the encoder is used for receiving first data, processing the first data and outputting an original data stream and an initial bit width of the original data stream;
the bit complementing unit is used for complementing the original data stream of which the initial bit width is smaller than a set value, adjusting the bit width of the original data stream to the set value, and outputting the bit-complemented data stream and the initial bit width;
the mode selection unit is used for selecting the data stream input into the mode selection unit according to the received instruction and outputting the selected data stream and the initial bit width of the selected data stream;
the FIFO device is used for receiving the selected data stream and the initial bit width, determining a write address corresponding to the original data stream of the selected data stream according to the current depth pointer, the current bit pointer and the initial bit width of the FIFO device, and writing the original data stream of the selected data stream into the FIFO device in parallel according to the write address.
Preferably, the bit-complementing unit is specifically configured to:
acquiring an initial bit width of an original data stream input into the data stream and the set value, and calculating a difference value between the set value and the initial bit width;
and when the initial bit width is smaller than a set value, supplementing the difference preset values after the low bit of the original data stream, so that the data bit width of the data stream after bit supplementation is the set value, and outputting the data stream after bit supplementation and the initial bit width.
Preferably, the FIFO device comprises at least a write logic unit and a storage unit, wherein,
the write logic unit is configured to receive the selected data stream and the initial bit width, determine whether an original data stream corresponding to the selected data stream needs to be blocked according to a current bit pointer of the FIFO device and the initial bit width, split the original data stream into at least two block data and determine a write address of each block data in the storage unit if the original data stream needs to be blocked, and write each block data in the storage unit in parallel according to the respective write address;
the storage unit is used for caching data input into the storage unit.
Preferably, the write logic unit includes a judgment module, a block division module, a write address determination module, and a write data module, wherein,
the judging module is used for determining whether the original data stream of the selected data stream needs to be partitioned according to the current bit pointer and the initial bit width;
the write address determining module is configured to split the original data stream into at least two block data and determine a write address corresponding to each block data in the storage unit, when the determining module determines that the original data stream of the selected data stream is to be blocked;
the data writing module is used for writing each block of data into the storage unit in parallel according to the corresponding writing address.
Preferably, the determining module is specifically configured to:
obtaining a residual bit width based on the current bit pointer and the write bit width of the storage unit;
and judging whether the initial bit width is larger than the residual bit width, if so, determining that the original data stream needs to be partitioned, otherwise, determining that the original data stream does not need to be partitioned.
Preferably, when the original data stream needs to be partitioned, the write address determining module is specifically configured to:
extracting the data with the residual bit width values from the original data stream according to the sequence from high bits to low bits to serve as first block data, and determining a first address of a write address corresponding to the first block data as an address pointed by a current bit pointer in a depth row corresponding to the current depth pointer value;
calculating a first difference value between the initial bit width and the residual bit width, and dividing the first difference value by the write bit width to obtain a quotient M and a remainder N;
extracting M block data from the residual data after the first block data is extracted from the original data stream according to the sequence from the high order to the low order, wherein according to the sequence from the high order to the low order, the write address corresponding to each block data in the M block data is the first address of the depth after the current depth pointer correspondingly stores the depth and M is added, wherein M refers to the extraction order, and M is 1, 2, … and M;
and if N is not zero, determining the residual data of the original data stream after M blocks of data are extracted as the (M +2) th block, wherein the writing address of the (M +2) th block corresponds to the first address of the depth obtained by adding M +1 to the storage depth by the current depth pointer.
A second aspect of the present invention provides a chip, which includes the foregoing data stream processing apparatus.
A third aspect of the present invention provides a data stream processing method, including:
receiving first data, and processing the first data to obtain an original data stream and an initial bit width of the original data stream;
supplementing bits to the original data stream with the initial bit width smaller than a set value, adjusting the bit width of the original data stream to the set value, and obtaining the bit-supplemented data stream and the initial bit width;
selecting data stream input into the instruction according to the received instruction to obtain the selected data stream and the initial bit width of the selected data stream
And determining a write address corresponding to the original data stream of the selected data stream according to the current depth pointer, the current bit pointer and the initial bit width of the FIFO device, and writing the original data stream of the selected data stream into the FIFO device in parallel according to the write address.
Preferably, the determining, according to the current depth pointer, the current bit pointer, and the initial bit width of the FIFO device, a write address corresponding to the original data stream of the selected data stream, and writing the original data stream of the selected data stream in parallel to the FIFO device according to the write address specifically includes:
and determining whether the original data stream corresponding to the selected data stream needs to be partitioned according to the current bit pointer of the FIFO device and the initial bit width, splitting the original data stream into at least two block data and determining the corresponding write address of each block data in the FIFO device if the original data stream needs to be partitioned, and writing each block data into the FIFO device in parallel according to the corresponding write address.
Preferably, the determining whether the original data stream corresponding to the selected data stream needs to be partitioned according to the current bit pointer of the FIFO device and the initial bit width specifically includes:
generating a residual bit width based on the current bit pointer and the write bit width of the FIFO device;
and judging whether the initial bit width is larger than the residual bit width, if so, determining that the original data stream needs to be partitioned, otherwise, determining that the original data stream does not need to be partitioned.
Preferably, splitting the original data stream into at least two blocks of data and determining a corresponding write address of each block of data in the storage unit includes:
extracting the data with the residual bit width values from the original data stream according to the sequence from high bits to low bits to serve as first block data, and determining a first address of a write address corresponding to the first block data as an address pointed by a current bit pointer in a depth row corresponding to the current depth pointer value;
calculating a first difference value between the initial bit width and the residual bit width, and dividing the first difference value by the write bit width to obtain a quotient M and a remainder N;
extracting M block data from the residual data after extracting the first block data from the original data stream according to the sequence from high order to low order, wherein according to the sequence from high order to low order, the write address corresponding to each block data in the M block data is the first address of the depth after the current depth pointer corresponds to the storage depth plus M, wherein M refers to the extraction order, and M is 1, 2, … and M;
and if N is not zero, determining the residual data of the original data stream after M blocks of data are extracted as the (M +2) th block, wherein the writing address of the (M +2) th block corresponds to the first address of the depth obtained by adding M +1 to the storage depth by the current depth pointer.
A fourth aspect of the invention provides an electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method when executing the computer program.
Has the advantages that: compared with the prior art, the embodiment of the disclosure has the advantages that at least: the device of the invention realizes the parallel writing of the original data stream into the FIFO device by splitting the original data stream into a plurality of block data and determining the writing address of each block data, the device places the corresponding combinational logic in the writing logic unit of the FIFO module, and the logic is split into a plurality of addresses, thus greatly reducing the total combinational logic amount, reducing the area of the chip by 70 percent under the specific process, and saving the cost.
Drawings
To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.
Fig. 1 is a schematic diagram of a simple structure of a data stream processing apparatus according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a simple FIFO memory according to an embodiment of the present disclosure;
fig. 3 is a flow diagram of some embodiments of a data stream processing method provided in accordance with an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of an electronic device provided in accordance with an embodiment of the present disclosure;
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings. The embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict.
It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different systems, devices, modules or units, and are not used for limiting the order or interdependence of the functions executed by the systems, devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.
The names of messages or information exchanged between devices in the embodiments of the present disclosure are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
The embodiment of the invention provides a data stream processing device, which comprises at least two encoders, a bit complementing unit, a mode selecting unit and a FIFO device, wherein the encoders are used for receiving first data and processing the first data to output an original data stream and an initial bit width of the original data stream, the bit complementing unit is used for complementing the original data stream of which the initial bit width is smaller than a set value to adjust the bit width of the original data stream to the set value and output the data stream after bit complementing and the initial bit width, and the mode selecting unit is used for selecting the data stream input into the mode selecting unit according to a received instruction and outputting the selected data stream and the initial bit width of the selected data stream; the FIFO device is used for receiving the selected data stream and the initial bit width, determining a write address corresponding to the original data stream of the selected data stream according to the current depth pointer, the current bit pointer and the initial bit width of the FIFO device, and writing the original data stream of the selected data stream into the FIFO device in parallel according to the write address.
As shown in fig. 1, the data stream processing apparatus 100 may include 3 encoders 101 (encoder a, encoder b, and encoder c), 2 complementary bit units 102 (complementary bit unit a and complementary bit unit b), 1 mode selection unit 103, and 1 FIFO device 104.
The encoder 101 may be configured to receive the first data, process the first data, and output a raw data stream and an initial bit width of the raw data stream. The number of the encoders 101 is at least greater than 2, and may be 2, 3 or other numbers, which are set as required. The first data may refer to data received by the encoder 101, which may be data or a data stream. The original data stream may refer to a data stream obtained after processing by the encoder 101, and the original data stream may be binary data. The initial bit width may refer to the amount of data output by the original data stream in each clock cycle, and as shown in fig. 1, the initial bit width of encoder a may be 144, the initial bit width of encoder b may be 96, and the initial bit width of encoder a may be 15.
The bit complementing unit 102 is configured to complement an original data stream with an initial bit width smaller than a set value, adjust the bit width of the original data stream to the set value, and output the bit-complemented data stream and the initial bit width. The bit complementing unit 102 may be a circuit or an electronic device, and is set as required. The set value may refer to the maximum initial bit width in the encoder 101, such as 144 for the encoder a in fig. 1, and the set value may be 144. The bit complementing of the original data stream with the initial bit width smaller than the set value may refer to adding a certain number of preset values after the data of each clock cycle of the original data stream, so that the data number (i.e., the initial bit width) of each clock cycle of the original data stream is set to 144. The preset value may be 0. In addition, the bit complementing unit 102 may be 1 unified unit, and is configured to receive inputs of all the encoders 101, and select a data stream requiring bit complementing to perform bit complementing; or, for the encoder 101 with a number of bit complementing units 102, selecting a data stream requiring bit complementing to perform bit complementing; it may also be a number of bit-padding units 102 of the encoder 101 (as shown in fig. 1) that require padding.
The mode selection unit 103 is configured to select a data stream input thereto according to a received instruction, and output the selected data stream and an initial bit width of the selected data stream.
Note that, the data in the encoder 101, the bit complement unit 102, and the mode selection unit 103 may be arranged in order from the higher order bits to the lower order bits in each clock cycle.
The FIFO device 104 is configured to receive the selected data stream and the initial bit width, determine a write address corresponding to an original data stream of the selected data stream according to the current depth pointer, the current bit pointer, and the initial bit width of the FIFO device 104, and write the original data stream of the selected data stream into the FIFO device 104 in parallel according to the write address.
The current depth pointer may be a pointer to the current storage depth of a storage location in the FIFO device 104. The current memory depth may refer to the depth that the memory cell is currently processing. Referring to fig. 2, the size of the storage space of the storage unit of the FIFO device 104 in fig. 2 may be 16 (columns) × 32 (rows), and if the current depth pointer points to the storage depth-0, the storage depth-0 is the processing depth (i.e. row value). The current Bit pointer may refer to the Bit address to be written in the current depth row, see Bit-14 in FIG. 2. In general, the line pointed to by the current depth pointer may be the last line written last time, or the next line to the last line; the current bit pointer may point to the next data bit to the last data bit last written.
The original data stream may correspond to at least one write address, and each write address may refer to a first address to which the original data stream is written. As an example, if the original data stream only corresponds to one write address, the current bit pointer is the write address of the original data stream, and the data in the original data stream is written in the order from the high order to the low order. If the original data stream corresponds to 2 write addresses, the first write address may be the current bit pointer, and the second write address may be the first address of the storage depth corresponding to the current depth pointer after adding 1 to the storage depth.
The beneficial effects of one of the above embodiments of the present disclosure at least include: the device of the invention realizes the parallel writing of the original data stream into the FIFO device by splitting the original data stream into a plurality of block data and determining the writing address of each block data, the device places the corresponding combinational logic in the writing logic unit of the FIFO module, and the logic is split into a plurality of addresses, thus greatly reducing the total combinational logic amount, reducing the area of the chip by 70 percent under the specific process, and saving the cost.
When the original data streams of the selected data streams are written in parallel into the FIFO device 104 according to the write addresses, the number of write control signals of the write addresses may be set to write the original data streams of the selected data streams in parallel into the FIFO device 104. The write signal may refer to a write enable signal.
In some embodiments, the bit complement unit is specifically configured to: acquiring an initial bit width and a set value of an original data stream input into the data stream, and calculating a difference value between the set value and the initial bit width; and when the initial bit width is smaller than the set value, supplementing the difference preset numerical values after the low bit of the original data stream, enabling the data bit width of the data stream after bit supplementation to be the set value, and outputting the data stream after bit supplementation and the initial bit width.
In some embodiments, the FIFO device 104 at least includes a write logic unit and a storage unit, where the write logic unit is configured to receive the selected data stream and an initial bit width, determine whether an original data stream corresponding to the selected data stream needs to be partitioned according to a current depth pointer, a current bit pointer, and the initial bit width of the FIFO device 104, split the original data stream into at least two block data and determine a write address of each block data in the storage unit if the original data stream needs to be partitioned, and write each block of fast data in parallel into the storage unit according to the respective write address; the storage unit is used for caching data input into the storage unit. The storage unit may refer to a unit for buffering data.
In some embodiments, the write logic unit includes a judging module, a partitioning module, a write address determining module, and a write data module, where the judging module is configured to determine whether an original data stream of the selected data stream needs to be partitioned according to the current bit pointer and the initial bit width; the writing address determining module is used for splitting the original data stream into at least two block data and determining the corresponding writing address of each block data in the storage unit under the condition that the judging module determines that the original data stream of the selected data stream is to be blocked; the data writing module is used for writing each block of data into the storage unit in parallel according to the corresponding writing address.
In some embodiments, the determining module is specifically configured to: generating a residual bit width based on the current bit pointer and the write bit width of the storage unit; and judging whether the initial bit width is larger than the residual bit width, if so, determining that the original data stream needs to be partitioned, otherwise, determining that the original data stream does not need to be partitioned.
In some optional implementations of some embodiments, since data in the storage unit of the FIFO is written in an order from a high digit to a low digit, and corresponding sequence numbers of the data bits are 15, 14, 1, and 0, respectively, the remaining bit width can be obtained by adding 1 to the sequence number of the digit corresponding to the current bit pointer. Referring to the current bit pointer in fig. 2, i.e., 14+ 1-15.
In other alternative implementations of some embodiments, the write logic may generate the remaining bit width based on the current bit pointer and the write bit width. The remaining bit width may refer to the number of data bits that are writable for the currently written row. With continued reference to FIG. 2, the write bit width of the FIFO memory is 16, and the current bit pointer points to bit-14, the second data bit. The write bit width (16) -the corresponding sequence number of the current bit pointer (2) +1, i.e. 16-2+1 ═ 15, i.e. the remaining bit width is 15. The calculation of the remaining bit width may also be calculated by other manners, which are all within the scope of the present disclosure.
In some embodiments, when the original data stream needs to be partitioned, the write address determining module is specifically configured to: extracting the data with the residual bit width from the original data stream according to the sequence from the high bit to the low bit as first block data, and determining a write address corresponding to the first block data as an address pointed by a current bit pointer; calculating a first difference value between the initial bit width and the residual bit width, and dividing the first difference value by the write-in bit width to obtain a quotient M and a remainder N; extracting M block data from the residual data after extracting the first block data from the original data stream according to the sequence from high order to low order, wherein the writing address corresponding to each block data in the M block data is the first address of the depth after the current depth pointer correspondingly stores the depth plus M according to the sequence from high order to low order, wherein M refers to the extraction order; and if N is not zero, determining the residual data of the original data stream after M blocks of data are extracted as the (M +2) th block, wherein the writing address of the (M +2) th block is the first address of the depth of the current depth pointer after the depth is added by M + 1.
As an example, assuming that the initial bit width is 50, the remaining bit width is 9, the write bit width is 16, and the current depth pointer points to the 3 rd storage depth. (50-9)/16 ═ 2, i.e., quotient 2 (for M) and remainder 9 (for N). Then, in order from the high order to the low order, the first 9 data are taken out as the first block data, and the remaining 41 data of the original data stream (i.e. the first difference value) are obtained, and the write address of the first block data is the address pointed by the current bit pointer. Then, according to the order from the high order to the low order, the 2 nd block data (including 9 data) and the 3 rd block data (including 9 data) are sequentially taken out from the 41 data, and the first address corresponding to the second block data is the first address of the depth obtained by adding 1 (corresponding to m) to the storage depth (3) corresponding to the current depth pointer, that is, the first address of the 4 th storage depth. The first address corresponding to the third block data is the first address of the depth of adding 2 (corresponding to m) to the storage depth (3) corresponding to the current depth pointer, namely the first address of the 5 th storage depth. The remainder is 9 and is not 0, so the remaining 9 data are regarded as 4 (corresponding to M +2) th block data, and the write address of the 4 th block is the first address of the depth after the current depth pointer corresponds to the storage depth (3) plus M + 1.
In some embodiments, when the original data stream does not require chunking, the write address determination module is specifically configured to: the write address is determined to be the address pointed to by the current bit pointer.
Through the setting of the write address determining module, the determining speed of the write address can be greatly improved, and the operating efficiency of the system is improved.
In some embodiments, the write logic unit further includes a pointer update module, configured to point the current depth pointer to a first address of a storage depth corresponding to the last block data, and point the current bit pointer to a preset number of data bits after the current depth pointer, where the preset number is the same as the number of data of the last data block.
Embodiments of the present disclosure also provide a chip, which may include, but is not limited to, one of the following: a fingerprint identification chip, an AI chip, an LCD driver chip, a TP driver chip, etc., which are not limited herein; the chip includes a functional integrated circuit that performs the functions of the chip itself and a data stream processing module as described in the embodiments of the present disclosure.
With continued reference to fig. 3, a flow 300 of some embodiments of a data stream processing method according to the present disclosure is shown. The data stream processing method comprises the following steps:
s301, receiving first data, and processing the first data to obtain an original data stream and an initial bit width of the original data stream.
S302, bit complementing is carried out on the original data stream of which the initial bit width is smaller than a set value, the bit width of the original data stream is adjusted to be the set value, and the data stream after bit complementing and the initial bit width are obtained.
S303, selecting the data stream input into the instruction according to the received instruction, and obtaining the selected data stream and the initial bit width of the selected data stream.
S304, determining a write address corresponding to the original data stream of the selected data stream according to the current depth pointer, the current bit pointer and the initial bit width of the FIFO device, and writing the original data stream of the selected data stream into the FIFO device in parallel according to the write address.
In a specific embodiment, the step S304 includes: and determining whether the original data stream corresponding to the selected data stream needs to be partitioned according to the current bit pointer of the FIFO device and the initial bit width, splitting the original data stream into at least two block data and determining the corresponding write address of each block data in the FIFO device if the original data stream needs to be partitioned, and writing each block data into the FIFO device in parallel according to the corresponding write address.
In a specific embodiment, the determining whether the original data stream corresponding to the selected data stream needs to be partitioned according to the current bit pointer of the FIFO device and the initial bit width specifically includes: generating a residual bit width based on the current bit pointer and the write bit width of the FIFO device; and judging whether the initial bit width is larger than the residual bit width, if so, determining that the original data stream needs to be partitioned, otherwise, determining that the original data stream does not need to be partitioned.
In a specific embodiment, splitting the original data stream into at least two blocks of data and determining a corresponding write address of each block of data in the storage unit includes: extracting the remaining bit width value data from the original data stream as first block data according to the sequence from high bits to low bits, determining a head address of a write address corresponding to the first block data as an address pointed by a current bit pointer in a depth row corresponding to the current depth pointer value, calculating a first difference value between the initial bit width and the remaining bit width, dividing the first difference value by the write bit width to obtain a quotient M and a remainder N, extracting M block data from the remaining data after extracting the first block data from the original data stream according to the sequence from high bits to low bits, wherein the write address corresponding to each block data in the M block data is the head address of a depth which is stored by adding M corresponding to the current depth pointer according to the sequence from high bits to low bits, wherein M refers to an extraction sequence, and M is 1, 2.…, M, if N is not zero, determining the residual data after extracting M blocks of data from the original data stream as the M +2 th block, wherein the write address of the M +2 th block corresponds to the first address of the depth after adding M +1 to the storage depth.
As shown in fig. 4, electronic device 500 may include a processing means (e.g., central processing unit, graphics processor, etc.) 501 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)502 or a program loaded from a storage means 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data necessary for the operation of the electronic apparatus 500 are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.
Generally, the following devices may be connected to the I/O interface 505: input devices 506 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 507 including, for example, a Liquid Crystal Display (LCD), speakers, vibrators, and the like; storage devices 508 including, for example, magnetic tape, hard disk, etc.; and a communication device 509. The communication means 509 may allow the electronic device 500 to communicate with other devices wirelessly or by wire to exchange data. While fig. 4 illustrates an electronic device 500 having various means, it is to be understood that not all illustrated means are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided. Each block shown in fig. 4 may represent one device or may represent multiple devices as desired.
In particular, according to some embodiments of the present disclosure, the processes described above with reference to the flow diagrams may be implemented as computer software programs. For example, some embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In some such embodiments, the computer program may be downloaded and installed from a network via the communication means 509, or installed from the storage means 508, or installed from the ROM 502. The computer program, when executed by the processing device 501, performs the above-described functions defined in the methods of some embodiments of the present disclosure.
It should be noted that the computer readable medium described above in some embodiments of the present disclosure may be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In some embodiments of the disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In some embodiments of the present disclosure, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.
In some embodiments, the clients, servers may communicate using any currently known or future developed network Protocol, such as HTTP (Hyper Text Transfer Protocol), and may interconnect with any form or medium of digital data communication (e.g., a communications network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the Internet (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed network.
The computer readable medium may be embodied in the apparatus; or may be separate and not incorporated into the electronic device. The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: receiving a data stream and an initial bit width; judging whether the original data stream corresponding to the data stream needs to be partitioned or not; if the data needs to be partitioned, splitting the original data stream into a plurality of partitioned data and determining a corresponding write address of each partitioned data in the storage unit; and writing each block of data into a storage unit of the FIFO device in parallel according to the write address corresponding to each block of data.
Computer program code for carrying out operations for embodiments of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Small talk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), systems on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and the like.
The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention in the embodiments of the present disclosure is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is made without departing from the inventive concept as defined above. For example, the above features and (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure are mutually replaced to form the technical solution.
Claims (12)
1. A data stream processing apparatus comprising at least two encoders, a bit-complementing unit, a mode-selecting unit and a FIFO device, wherein,
the encoder is used for receiving first data, processing the first data and outputting an original data stream and an initial bit width of the original data stream;
the bit complementing unit is used for complementing the original data stream of which the initial bit width is smaller than a set value, adjusting the bit width of the original data stream to the set value, and outputting the bit-complemented data stream and the initial bit width;
the mode selection unit is used for selecting the data stream input into the mode selection unit according to the received instruction and outputting the selected data stream and the initial bit width of the selected data stream;
the FIFO device is used for receiving the selected data stream and the initial bit width, determining a write address corresponding to the original data stream of the selected data stream according to the current depth pointer, the current bit pointer and the initial bit width of the FIFO device, and writing the original data stream of the selected data stream into the FIFO device in parallel according to the write address.
2. The apparatus of claim 1, wherein the bit-padding unit is specifically configured to:
acquiring an initial bit width of an original data stream input into the data stream and the set value, and calculating a difference value between the set value and the initial bit width;
and when the initial bit width is smaller than a set value, supplementing the difference preset values after the low bit of the original data stream, so that the data bit width of the data stream after bit supplementation is the set value, and outputting the data stream after bit supplementation and the initial bit width.
3. The apparatus of claim 2, wherein the FIFO device comprises at least a write logic unit and a storage unit, wherein,
the write logic unit is configured to receive the selected data stream and the initial bit width, determine whether an original data stream corresponding to the selected data stream needs to be blocked according to a current bit pointer of the FIFO device and the initial bit width, split the original data stream into at least two block data and determine a write address of each block data in the storage unit if the original data stream needs to be blocked, and write each block data in the storage unit in parallel according to the respective write address;
the storage unit is used for caching data input into the storage unit.
4. The apparatus of claim 3, wherein the write logic unit comprises a determination module, a partitioning module, a write address determination module, and a write data module, wherein,
the judging module is used for determining whether the original data stream of the selected data stream needs to be partitioned according to the current bit pointer and the initial bit width;
the write address determining module is configured to split the original data stream into at least two block data and determine a write address corresponding to each block data in the storage unit, when the determining module determines that the original data stream of the selected data stream is to be blocked;
the data writing module is used for writing each block of data into the storage unit in parallel according to the corresponding writing address.
5. The apparatus according to claim 4, wherein the determining module is specifically configured to:
obtaining a residual bit width based on the current bit pointer and the write bit width of the storage unit;
and judging whether the initial bit width is larger than the residual bit width, if so, determining that the original data stream needs to be partitioned, otherwise, determining that the original data stream does not need to be partitioned.
6. The apparatus of claim 5, wherein when the original data stream needs to be partitioned, the write address determination module is specifically configured to:
extracting the data with the residual bit width values from the original data stream according to the sequence from high bits to low bits to serve as first block data, and determining a first address of a write address corresponding to the first block data as an address pointed by a current bit pointer in a depth row corresponding to the current depth pointer value;
calculating a first difference value between the initial bit width and the residual bit width, and dividing the first difference value by the write bit width to obtain a quotient M and a remainder N;
extracting M block data from the residual data after extracting the first block data from the original data stream according to the sequence from high order to low order, wherein according to the sequence from high order to low order, the write address corresponding to each block data in the M block data is the first address of the depth after the current depth pointer corresponds to the storage depth plus M, wherein M refers to the extraction order, and M is 1, 2, … and M;
and if N is not zero, determining the residual data of the original data stream after M blocks of data are extracted as the (M +2) th block, wherein the writing address of the (M +2) th block corresponds to the first address of the depth obtained by adding M +1 to the storage depth by the current depth pointer.
7. A chip comprising a data stream processing apparatus as claimed in any one of claims 1 to 6.
8. A method for processing a data stream, comprising:
receiving first data, and processing the first data to obtain an original data stream and an initial bit width of the original data stream;
supplementing bits to the original data stream with the initial bit width smaller than a set value, adjusting the bit width of the original data stream to the set value, and obtaining the bit-supplemented data stream and the initial bit width;
selecting data stream input into the instruction according to the received instruction to obtain the selected data stream and the initial bit width of the selected data stream
And determining a write address corresponding to the original data stream of the selected data stream according to the current depth pointer, the current bit pointer and the initial bit width of the FIFO device, and writing the original data stream of the selected data stream into the FIFO device in parallel according to the write address.
9. The method according to claim 8, wherein the determining a write address corresponding to the original data stream of the selected data stream according to the current depth pointer, the current bit pointer, and the initial bit width of the FIFO device, and writing the original data stream of the selected data stream into the FIFO device in parallel according to the write address specifically includes:
and determining whether the original data stream corresponding to the selected data stream needs to be partitioned according to the current bit pointer of the FIFO device and the initial bit width, splitting the original data stream into at least two block data and determining the corresponding write address of each block data in the FIFO device if the original data stream needs to be partitioned, and writing each block data into the FIFO device in parallel according to the corresponding write address.
10. The method according to claim 9, wherein said determining whether the original data stream corresponding to the selected data stream needs to be partitioned according to the current bit pointer of the FIFO device and the initial bit width specifically comprises:
generating a residual bit width based on the current bit pointer and the write bit width of the FIFO device;
and judging whether the initial bit width is larger than the residual bit width, if so, determining that the original data stream needs to be partitioned, otherwise, determining that the original data stream does not need to be partitioned.
11. The method of claim 10, wherein splitting the original data stream into at least two blocks of data and determining a corresponding write address of each block of data in the storage unit comprises:
extracting the data with the residual bit width values from the original data stream according to the sequence from high bits to low bits to serve as first block data, and determining a first address of a write address corresponding to the first block data as an address pointed by a current bit pointer in a depth row corresponding to the current depth pointer value;
calculating a first difference value between the initial bit width and the residual bit width, and dividing the first difference value by the write bit width to obtain a quotient M and a remainder N;
extracting M block data from the residual data after extracting the first block data from the original data stream according to the sequence from high order to low order, wherein according to the sequence from high order to low order, the write address corresponding to each block data in the M block data is the first address of the depth after the current depth pointer corresponds to the storage depth plus M, wherein M refers to the extraction order, and M is 1, 2, … and M;
and if N is not zero, determining the residual data of the original data stream after M blocks of data are extracted as the (M +2) th block, wherein the writing address of the (M +2) th block corresponds to the first address of the depth obtained by adding M +1 to the storage depth by the current depth pointer.
12. An electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method according to any one of claims 8 to 11 when executing the computer program.
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