CN114629444A - Amplifying circuit, deviation adjusting method thereof, amplifier and electronic equipment - Google Patents
Amplifying circuit, deviation adjusting method thereof, amplifier and electronic equipment Download PDFInfo
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- CN114629444A CN114629444A CN202210510250.4A CN202210510250A CN114629444A CN 114629444 A CN114629444 A CN 114629444A CN 202210510250 A CN202210510250 A CN 202210510250A CN 114629444 A CN114629444 A CN 114629444A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
- H03F1/086—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers with FET's
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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Abstract
The application discloses amplifier circuit and deviation adjustment method, amplifier, electronic equipment thereof relates to electronic circuit technical field, and amplifier circuit includes: the input port is used for acquiring a differential input signal; the amplifying unit is used for amplifying the differential input signal and outputting a differential amplified signal; the comparison unit is used for determining deviation voltage in the differential amplification signal; the deviation adjusting unit is used for outputting a deviation voltage adjusting signal according to the deviation voltage; the output port is used for acquiring the differential amplification signal and the deviation voltage adjustment signal, performing deviation voltage adjustment on the differential amplification signal by using the deviation voltage adjustment signal, and outputting the adjusted differential amplification signal. Therefore, the manufacturing deviation of the amplifier is improved, and further, the deviation voltage caused by the amplifier is eliminated, so that the working performance of the post-stage equipment connected with the amplifier is stable.
Description
Technical Field
The present disclosure relates to the field of electronic circuits, and in particular, to an amplifying circuit, a deviation adjusting method thereof, an amplifier, and an electronic device.
Background
In the prior art, due to manufacturing deviation of an amplifier, both an amplification factor and a bias voltage of an amplifying circuit inside the amplifier have deviation, and the deviation can cause amplitude deviation of an output signal of the amplifier, so that a potential difference is generated in an amplitude center voltage of the output signal, and thus the working performance of a post-stage device connected with the amplifier is influenced.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide an amplifying circuit, a deviation adjusting method thereof, an amplifier, and an electronic device, so as to solve the problem of stability that the output signal of the amplifier has a deviation due to manufacturing deviation of the amplifier itself, and thus the working performance of a subsequent device connected to the amplifier is affected.
The application provides an amplifying circuit, includes:
an input port for acquiring a differential input signal;
the amplifying unit is connected with the input port and used for amplifying the differential input signal and outputting a differential amplified signal;
the comparison unit is connected with the amplification unit and used for determining the deviation voltage in the differential amplification signal and outputting the differential amplification signal passing through the comparison unit;
the deviation adjusting unit is connected with the comparing unit and used for outputting a deviation voltage adjusting signal according to the deviation voltage;
and the output port is respectively connected with the comparison unit and the deviation adjustment unit and is used for acquiring the differential amplification signal and the deviation voltage adjustment signal which pass through the comparison unit, performing deviation voltage adjustment on the differential amplification signal which passes through the comparison unit by using the deviation voltage adjustment signal and outputting the adjusted differential amplification signal.
Optionally, the switch unit further includes:
and the switch unit is respectively connected with the input port and the amplifying unit and is used for controlling the transmission path of the differential input signal.
Optionally, the transmission path of the differential input signal includes a first path and a second path that are connected in sequence, and the switch unit includes:
the first switch subunit is connected with the input port and used for controlling the on-off of the first path;
and the second switch subunit is respectively connected with the first switch subunit and the amplifying unit and is used for controlling the on-off of the second path and outputting the differential input signal acquired from the first switch subunit to the amplifying unit when the second path is disconnected.
Optionally, the deviation adjusting unit includes:
the compensation voltage subunit is used for outputting a compensation voltage signal;
and the adjusting subunit is respectively connected with the output port, the comparing unit and the compensation voltage subunit, and is used for adjusting the compensation voltage signal according to the offset voltage and outputting an offset voltage adjusting signal according to the compensation voltage signal.
Optionally, the amplifying circuit further includes:
and the control unit is respectively connected with the output port, the comparison unit and the deviation adjustment unit and is used for providing working voltage and working current for the comparison unit and the deviation adjustment unit, acquiring a clock signal and controlling the on-off of the output port according to the clock signal.
In a second aspect, an embodiment of the present application provides a method for adjusting a bias of an amplifying circuit, where the amplifying circuit is the amplifying circuit described above, and the method for adjusting a bias of an amplifying circuit includes:
acquiring a differential amplification signal and a deviation voltage adjustment signal;
performing deviation voltage adjustment on the differential amplification signal by using the deviation voltage adjustment signal, and outputting an adjusted differential amplification signal;
the method for acquiring the differential amplification signal comprises the following steps:
the amplifying unit acquires a differential input signal input through the input port, and amplifies the differential input signal to obtain a differential amplified signal;
the method for acquiring the deviation voltage adjustment signal comprises the following steps:
the amplifying unit sends the differential amplifying signal to the comparing unit to determine a deviation voltage in the differential amplifying signal, and the deviation adjusting unit receives the deviation voltage output by the comparing unit and outputs a deviation voltage adjusting signal according to the deviation voltage.
Optionally, before the obtaining the differential amplified signal, the offset adjusting method further includes:
the first switch subunit is switched off, the second switch subunit is switched on, and the second switch subunit sends the differential input signal to the amplifying unit;
if the differential amplification signal output by the amplification unit has deviation, the differential amplification signal is sent to the comparison unit, the comparison unit determines the deviation voltage in the differential amplification signal and outputs the differential amplification signal;
and if the differential amplified signal output by the amplifying unit has no deviation, outputting the differential input signal through an output port.
Optionally, the differential amplified signal is subjected to offset voltage adjustment by using the offset voltage adjustment signal, and the adjusted differential amplified signal is output, including increasing or decreasing the offset voltage adjustment signal output by the offset adjustment unit;
and if the voltage of the adjusted differential amplification signal is inverted, maintaining and storing the offset voltage adjustment signal output by the offset adjustment unit, simultaneously switching on the first switch subunit, switching off the second switch subunit, and acquiring the differential input signal at the next moment.
In a third aspect, an embodiment of the present application provides an amplifier including the amplification circuit described above, where the amplification circuit performs the offset adjustment method described above.
In a fourth aspect, an embodiment of the present application provides an electronic device, including a housing, where the amplification circuit is disposed in the housing, and the amplification circuit is configured to perform the offset adjustment method.
In the embodiment of the application, the differential input signal is acquired through the input port, the amplifying unit amplifies the differential input signal and outputs the differential amplified signal, the comparing unit acquires the differential amplified signal and compares the differential amplified signal to determine the offset voltage in the differential amplified signal, then the offset adjusting unit adjusts the differential amplified signal according to the offset voltage to eliminate the offset voltage of the differential amplified signal, and the output port outputs the adjusted differential amplified signal, so that the influence of the manufacturing offset of the amplifier on the amplifying circuit is reduced, and the stability of the working performance of the rear-stage equipment connected with the amplifier can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of an amplifier circuit used in the prior art.
Fig. 2 is a schematic diagram of an output waveform of an amplifying circuit used in the prior art.
Fig. 3 is a schematic structural diagram of an amplifying circuit according to an embodiment of the present disclosure
Fig. 4 is another schematic structural diagram of an amplifying circuit according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of an amplifying circuit according to an embodiment of the present application.
Fig. 6 is a schematic diagram of an output waveform of an amplifying circuit according to an embodiment of the present disclosure.
Fig. 7 is a flowchart illustrating a method for adjusting a deviation of an amplifying circuit according to an embodiment of the present disclosure.
Fig. 8 is a flowchart illustrating steps S01 to S03 in the offset adjustment method of the amplifier circuit according to the embodiment of the disclosure.
Fig. 9 is a flowchart illustrating steps S21 to S22 in the offset adjustment method of the amplifier circuit according to the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that, as shown in fig. 1-2, fig. 1 is a schematic diagram of an amplifying circuit used in the prior art. Fig. 2 is a waveform diagram of an amplifying circuit used in the prior art.
In fig. 2, INP and INN are input signals of the amplifier AMP; EQP and EQN are output signals of the amplifier AMP; CLK is a sampling clock; OUTP and OUN are output signals of the amplifier circuit in the prior art, wherein fail in fig. 2 represents a waveform with a voltage deviation, and pass represents a waveform without a voltage deviation.
And in the prior art, the amplifier AMP is internally composed of a set (two) of linear amplifiers, the amplification factor and the DC bias voltage of the amplifier AMP are different due to the influence of the manufacturing variation of the amplifier AMP, so the amplitudes of the outputs EQP and EQN of the amplifier AMP are shifted from the amplitude center, thereby generating a potential difference dV in the amplitude center voltages of the EQP and EQN. As a result, by observation of the differential signal, it was found that there was a case where the aperture of the output eye pattern of the amplifier AMP was reduced, while both the setting time margin and the holding time margin of the output clock of the amplifier AMP were reduced.
The amplifying circuit, the deviation adjusting method of the amplifying circuit, the amplifier and the electronic device provided by the embodiment of the application mainly aim to solve the problem that the output signal of the amplifier has deviation due to the deviation caused by the manufacturing of the amplifier, so that the stability of the working performance of a post-stage device connected with the amplifier is influenced. In order to solve the problem of manufacturing deviation of the amplifier, an embodiment of the present application provides an amplifying circuit, which determines a deviation voltage and adjusts the deviation voltage by using a deviation adjusting unit, so as to ensure stability of working performance of a subsequent device connected to the amplifier.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an amplifying circuit according to an embodiment of the present disclosure, specifically, the amplifying circuit includes input ports INP and INN; an amplification unit 1; a comparison unit 2; a deviation adjustment unit 3; and output ports OUTP, OUTN.
Wherein, the input ports INP, INN are connected with the amplifying unit 1, the amplifying unit 1 is connected with the comparing unit 2, and the output ports OUTP, OUTN are respectively connected with the comparing unit 2 and the deviation adjusting unit 3; the input ports INP, INN are used to obtain differential input signals; the amplifying unit 1 is used for amplifying the differential input signal and outputting a differential amplified signal; the comparison unit 2 is used to determine an offset voltage in the differentially amplified signal, which contains a manufacturing offset of the amplification unit 1, or an offset voltage which contains an offset of the differentially input signal itself and a manufacturing offset of the amplification unit 1, and to output the differentially amplified signal through the comparison unit 2.
The deviation adjusting unit 3 is used for outputting a deviation voltage adjusting signal according to the deviation voltage; the output ports OUTP and OUTN are used to acquire the differential amplified signal and the offset voltage adjustment signal that have passed through the comparison unit 2, perform offset voltage adjustment on the differential amplified signal that has passed through the comparison unit 2 using the offset voltage adjustment signal, and output the adjusted differential amplified signal.
The present embodiment provides an amplifying circuit, which obtains a differential input signal through input ports INP and INN, amplifies the differential input signal by an amplifying unit 1, outputs the differential amplified signal, since there may be manufacturing deviation of the amplifying unit 1 produced in the manufacturing process itself in the differential amplifying signal, in order to eliminate the manufacturing deviation and ensure the normal operation of the subsequent device, it is necessary to obtain the manufacturing deviation of the amplifying unit 1 through the comparing unit 2, i.e. the differential amplified signals are compared to determine a deviation voltage in the differential amplified signals, after which the differential amplified signals are adjusted by the deviation adjustment unit 3 in dependence of the deviation voltage, so as to eliminate the offset voltage, and output the adjusted differential amplified signal from the output ports OUTP, OUTN, the influence of the manufacturing deviation of the amplifier on the amplifying circuit is reduced, so that the stability of the working performance of the post-stage equipment connected with the amplifier can be improved.
In an embodiment, in the amplifying circuit provided in this embodiment, the amplifying unit 1 may be an operational amplifier AMP, the comparing unit 2 may be a comparing circuit composed of a first MOS transistor M1, a second MOS transistor M2, and a third MOS transistor M3, and the deviation adjusting unit 3 may be a deviation adjusting circuit composed of the compensation voltage subunit 31 and the adjusting subunit 32.
In this embodiment, the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are all the same type of MOS transistor (PMOS transistor or NMOS transistor), wherein the first stage of the MOS transistor is a drain, the second stage of the MOS transistor is a gate, and the third stage of the MOS transistor is a source; the compensation voltage subunit 31 is configured to output a compensation voltage signal; the adjusting subunit 32 is configured to adjust the compensation voltage signal according to the offset voltage, and output an offset voltage adjusting signal according to the compensation voltage signal.
In the amplifying circuit provided in the embodiment of the present application, as shown in fig. 4-5, an INP input port and an INN input port of the amplifying unit 1 are connected, an output end EQP of the amplifying unit 1 is connected to a gate of a second MOS transistor M2, an output end EQN is connected to a gate of a third MOS transistor M3, a drain of the second MOS transistor M2 is connected to a power VDD, an output port OUTP, and a deviation adjusting unit 3, a drain of the third MOS transistor M3 is connected to the power VDD, the output port OUTN, and the deviation adjusting unit 3, a source of the second MOS transistor M2 and a source of the third MOS transistor M3 are connected to a drain of the first MOS transistor M1, a source of the first MOS transistor M1 is grounded, and a gate of the first MOS transistor M1 is used for acquiring a clock signal.
Alternatively, the compensation voltage subunit 31 may be a digital-to-analog converter or an adjustable voltage source.
Optionally, the adjusting subunit 32 may include an eighth MOS transistor M8 and a ninth MOS transistor M9, wherein a drain of the eighth MOS transistor M8 is connected to a drain of the second MOS transistor M2 and the output port OUTP, respectively, a drain of the ninth MOS transistor M9 is connected to a drain of the third MOS transistor M3 and the output port OUTN, a gate of the eighth MOS transistor M8 and a gate of the ninth MOS transistor M9 are both connected to the compensation voltage subunit 31, and a source of the eighth MOS transistor M8 and a source of the ninth MOS transistor M9 are both connected to the power supply VSS. In this embodiment, the compensation voltage subunit 31 may further include a gate connection of the first digital-to-analog converter DAC1 and the eighth MOS transistor M8, and a gate connection of the second digital-to-analog converter DAC2 and the ninth MOS transistor M9.
In the present embodiment, the operational amplifier AMP acquires the differential input signal, amplifies the differential input signal, and outputs the differential amplified signal, and then the comparison unit 2 performs voltage comparison on the differential amplified signal in order to determine whether there is a deviation voltage in the amplification circuit, and when the voltages output by the comparison unit 2 are equal, there is no deviation in the operational amplifier AMP. When the voltages output by the comparing unit 2 are not equal, it is indicated that the operational amplifier AMP has a deviation, and the deviation voltage output by the comparing unit 2 needs to be adjusted by the deviation adjusting unit 3, and in order to eliminate the deviation voltage in the amplifying circuit, the offset voltage is gradually adjusted by providing the compensation voltage sub-unit 32 and utilizing the on-state characteristic of the adjusting sub-unit 31.
Furthermore, when the regulated voltage is inverted, it indicates that the positive and negative errors are cancelled, and at this time, no offset voltage exists in the amplifying circuit, so as to ensure the stable operation of the subsequent circuit.
Optionally, in the amplifying circuit, in order to ensure that the amplifying circuit can normally operate, a control unit 5 is further required to be provided, where the control unit 5 is connected to the output ports OUTP and OUTN, the comparing unit 2, and the deviation adjusting unit 3, and is configured to provide a working voltage and a working current to the comparing unit 2 and the deviation adjusting unit 3, obtain a clock signal, and control on/off of the output ports OUTP and OUTN according to the clock signal.
As shown in fig. 4, fig. 4 is another schematic structural diagram of an amplifying circuit provided in the embodiment of the present application. In order to further determine the manufacturing deviation of the amplifier, in the embodiment of the present application, the amplifying circuit is further provided with a switch unit 4, the switch unit 4 may be disposed between the input ports INP and INN and the amplifying unit 1, by providing the switch unit 4, the differential input signal is short-circuited before the circuit works, the amplifying unit 2 obtains the differential input signal, and if the output ports EQP and EQN of the amplifying unit 2 output the differential amplified signal with the same potential, which indicates that the amplifying unit 2 itself has no manufacturing error, the offset voltage adjustment of the amplifying circuit is not needed; if the output terminals EQP and EQN of the amplifying unit 2 output differential amplified signals having different potentials, indicating that the amplifying unit 2 itself has a manufacturing error, the offset voltage of the amplifying circuit needs to be adjusted.
The switch unit 4 is connected to the input ports INP and INN and the amplifying unit 1, respectively, and the switch unit 4 is configured to control a transmission path of the differential input signal.
Optionally, the transmission path of the differential input signal includes a first path and a second path that are sequentially connected, and the switch unit 4 may further include a first switch subunit 41 and a second switch subunit 42, where the first switch subunit 41 is connected to the input port and is used to control on/off of the first path; the second switch subunit 42 is connected to the first switch subunit 41 and the amplifying unit 1, respectively, and is configured to control on/off of the second path, and output the differential input signal obtained from the first switch subunit 41 to the amplifying unit 1 when the second path is disconnected. While when the second path is on, the first switching subunit 41 will be short circuited and the differential input signal will be provided by the second switching subunit 42.
As shown in fig. 5, fig. 5 is a schematic circuit diagram of an amplifying circuit according to an embodiment of the present application. The amplifying circuit includes: input ports INP, INN, amplification means 1, comparison means 2, deviation adjustment means 3, switch means 4, control means 5, and output ports OUTP, OUTN; the deviation adjustment unit 3 further comprises a compensation voltage subunit 31 and an adjustment subunit 32; the switching unit 4 comprises a first switching subunit 41 and a second switching subunit 42.
In one embodiment, the first switch subunit 41 includes a first switch SW1, a second switch SW 2; the second switch subunit 42 includes a third switch SW 3; the amplification unit 1 includes an operational amplifier AMP; the comparison unit 2 comprises a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3; the deviation adjusting unit 3 comprises an eighth MOS transistor M8, a ninth MOS transistor M9, a first adjustable voltage source DAC1, and a second adjustable voltage source DAC 2; the control unit 5 includes a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7.
In one embodiment, the first switch SW1 and the second switch SW2 are disposed in the first path, and the third switch SW3 is disposed in the second path.
The signal INPUT ports INP, INN are used to obtain differential INPUT signals, the signal INPUT port INN is connected to a first end of the first switch SW1, the signal INPUT port INP is connected to a first end of the second switch SW2, a second end of the first switch SW1 is connected to a second end of the second switch SW2, a second end of the first switch SW1 and a second end of the second switch SW2 are both used to obtain an interrupt signal INPUT _ ON for interrupting/conducting (SHORT-circuiting) the first switch SW1 and the second switch SW2, a third end of the first switch SW1 is connected to a third end of the third switch SW3 and an INPUT end of the amplifier AMP, a third end of the second switch SW1 is connected to a first end of the third switch SW3 and an INPUT end of the amplifier AMP, respectively, and a second end of the third switch SW3 is used to obtain a signal INPUT for SHORT-circuiting the differential INPUT signal INPUT _ SHORT from the first switch SW1 and the second switch SW 2.
The output terminal EQN of the amplifier AMP is connected to the second terminal of the third MOS transistor M3, and the output terminal EQP of the amplifier AMP is connected to the second terminal of the second MOS transistor M2.
A first end of the second MOS transistor M2 is connected to a first end of the fourth MOS transistor M4, a first end of the sixth MOS transistor M6, a second end of the fifth MOS transistor M5, an output port OUTP, and a first end of the eighth MOS transistor M8, a first end of the third MOS transistor M3 is connected to a first end of the fifth MOS transistor M5, a first end of the seventh MOS transistor M7, a second end of the fourth MOS transistor M4, an output port OUTN, and a first end of the ninth MOS transistor M9, a third end of the second MOS transistor M2 and a third end of the third MOS transistor M3 are connected to a first end of the first MOS transistor M1, a third end of the first MOS transistor M1 is connected to a power supply, and a second end of the first MOS transistor M1 is used for obtaining a clock signal, so as to implement time-sharing sampling of the input amplified signal and implement comparison of the input amplified signal.
The third terminal of the fourth MOS transistor M4, the third terminal of the fifth MOS transistor M5, the third terminal of the sixth MOS transistor M6, and the third terminal of the seventh MOS transistor M7 are all grounded to VDD, and the second terminal of the sixth MOS transistor M6 and the second terminal of the seventh MOS transistor M7 are both connected to the second terminal of the first MOS transistor M1, and are used for acquiring a clock signal and utilizing the clock signal so as to implement time-sharing sampling control on an input amplified signal, and implement comparison on the input amplified signal.
The second end of the eighth MOS transistor M8 is connected to the first adjustable voltage source DAC1, the second end of the ninth MOS transistor M9 is connected to the second adjustable voltage source DAC2, and the third end of the eighth MOS transistor M8 and the third end of the ninth MOS transistor M9 are both connected to the power supply.
In the present embodiment, the first adjustable voltage source DAC1 and the second adjustable voltage source DAC2 in the compensation voltage subunit 31 may also be the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC 2.
Alternatively, the first switch SW1 and the second switch SW2 may be analog switches, for example: the analog switch may be a switching transistor; when the first switch SW1 and the second switch SW2 are switching transistors, the first terminal of the switching transistor is a source, the second terminal of the switching transistor is a gate, and the third terminal of the switching transistor is a drain.
Optionally, first ends of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the eighth MOS transistor M8, the ninth MOS transistor M9, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 are drains, first ends of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the eighth MOS transistor M8, the ninth MOS transistor M9, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 are gates, and first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the eighth MOS transistor M8, the ninth MOS transistor M9, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 are source electrodes.
Optionally, when the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the eighth MOS transistor M8 and the ninth MOS transistor M9 are PMOS transistors, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 are NMOS transistors; when the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the eighth MOS transistor M8 and the ninth MOS transistor M9 are NMOS transistors, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 are PMOS transistors.
As shown in fig. 6, fig. 6 is a schematic diagram of an output waveform of an amplifying circuit provided in the embodiment of the present application; the working principle of the amplifying circuit provided by the embodiment is as follows:
before the amplification circuit starts operating, the first switch SW1 and the second switch SW2 provided between the input ports INP, INN and the amplifier AMP are turned off, and the third switch SW3 is turned on to short-circuit the input port of the amplifier AMP. The output voltages of the first adjustable voltage source DAC1 and the second adjustable voltage source DAC2 are then set such that the eighth MOS transistor M8 and the ninth MOS transistor M9 are in an off state. The output ports OUTP and OUNT of the sixth and seventh MOS transistors M6 and M7 stop outputting the differential amplification signals when the clock CLK is at the low level L, and the output ports EQP and EQN of the amplifier AMP output potentials corresponding to the voltages when the clock CLK is at the high level H.
Since the input of the amplifier AMP is short-circuited, when there is no deviation in the amplifier AMP, the output ports EQP and EQN of the amplifier AMP have the same potential; when the output ports EQP and EQN of the amplifier AMP are deviated, a potential difference dV is generated due to the influence of the manufacturing deviation of the amplifier AMP (see waveform diagram). The manufacturing variation corresponds the potential difference dV of the amplifier AMP to the potential difference dV output by the amplifier AMP. Alternatively, when dV =0, it indicates that the output of the amplifier AMP is in an ideal state.
When the output voltage of the first adjustable voltage source DAC1 or the second adjustable voltage source DAC2 is gradually changed and the output port OUTP or OUTN is observed in a state where the amplifier circuit has a variation, if the state of the output signal from the output port OUTP or OUTN is inverted at a certain time, the variation voltage generated in the amplifier circuit can be cancelled out by the signal inversion.
The specific adjustment process may be:
first, the output voltage of the first adjustable voltage source DAC1 can be changed, and the initial value of the second adjustable voltage source DAC2 is maintained, so that the ninth MOS transistor M9 is turned off. When the output of the first adjustable voltage source DAC1 gradually changes until the eighth MOS transistor M8 is fully turned on, the corresponding offset adjustment voltage is output. If the output port OUTP or OUTN of the first adjustable voltage source DAC1 is not changed due to the adjustment of the output voltage, the output value of the first adjustable voltage source DAC1 needs to be restored to the initial value of the eighth MOS transistor M8, and then the output value of the second adjustable voltage source DAC2 needs to be adjusted.
If the output values/levels of the output ports OUTP or OUTN are inverted at a random time when the outputs of the first adjustable voltage source DAC1 and the second adjustable voltage source DAC2 are changed, the current output values of the first adjustable voltage source DAC1 and the second adjustable voltage source DAC2 are stored, and then the first switch SW1 and the second switch SW2 are turned on, and the third switch SW3 is turned off, so that the amplification thereof is recovered to the normal operation.
In this embodiment, since the output voltage V2 and the previous voltage V1 of the first adjustable voltage source DAC1 and the second adjustable voltage source DAC2 immediately after the output port OUTP or OUTN output signal inversion are just able to obtain the voltage output required for eliminating the manufacturing deviation of the amplifier AMP by the voltage difference therebetween, after the output voltage is adjusted, it is also necessary to store the voltage output value V1 or V2 of the first adjustable voltage source DAC1 and the second adjustable voltage source DAC2 immediately before or after the inversion, and then to hold/maintain the output values of the first adjustable voltage source DAC1 and the second adjustable voltage source DAC2, thereby eliminating the voltage deviation in the amplifying circuit.
It should be noted that, when the output values of the first adjustable voltage source DAC1 and the second adjustable voltage source DAC2 are set, the operating point of the second MOS transistor M2 or the third MOS transistor M3 is shifted by the forced shift, which is the shift of the center of the amplitude of the output ports EQP and EQN of the amplifier AMP by dV. Therefore, when the outputs of the second and third MOS transistors M2 and M3 are equivalent to the amplitude center offsets dV of the output ports EQP and EQN of the amplifier AMP when the offset amount becomes 0, as viewed from the second and third MOS transistors M2 and M3, it can be said that there is no manufacturing variation in the amplifier AMP.
Alternatively, assuming that the amplifier AMP output ports EQP and EQN are offset by 0 in the center, it is also possible to ensure that the setting time and the holding time of the clock CLK are at the original values, thereby avoiding the reduction of the setting margin and the holding margin.
In the present embodiment, analog switches SW1, SW2 for cutting off signals and an analog switch SW3 for short-circuiting between both input terminals of the AMP are inserted between the input ports INP, INN of the amplifier AMP, and MOS transistors M8, M9 are added between the output terminals OUTP, OUTN and the power supply VSS. The outputs of the DA converters DAC1 and DAC2 are connected to the added gate inputs of M8 and M9, respectively, thereby eliminating the influence of manufacturing variations of the amplifier AMP on the amplification circuit.
In addition, INP, INN in the waveform diagram of fig. 6 is an input waveform inputted from the input port INP, INN of the amplifier AMP; EQP, EQN are represented as actual output waveforms output by output ports EQP and EQN of amplifier AMP; EQP, EQN (imaginary) represents an ideal output waveform output by the output ports EQP and EQN of the amplifier AMP; LCK represents the time pulse output as a clock signal; OUTP and OUTN are waveforms output from the amplifier circuit after being adjusted by the offset adjusting means.
Referring to fig. 7, fig. 7 is a schematic flowchart illustrating a method for adjusting a deviation of an amplifier circuit according to an embodiment of the present disclosure, where the method for adjusting a deviation of an amplifier circuit includes the following steps:
s1 obtains a differential amplified signal of the offset voltage to be adjusted and an offset voltage adjustment signal.
In this embodiment, the differential amplified signal of the offset voltage to be adjusted obtains a differential input signal input by an input port through an amplifying unit, amplifies the differential input signal to obtain a differential amplified signal, and sends the differential amplified signal to a comparing unit to determine the offset voltage in the differential amplified signal to obtain the differential amplified signal of the offset voltage to be adjusted; the deviation voltage adjusting signal is obtained by the output of the deviation adjusting unit.
S2 performs offset voltage adjustment on the differential amplified signal of the offset voltage to be adjusted using the offset voltage adjustment signal, and outputs the differential amplified signal after the offset voltage adjustment.
In this embodiment, the method for acquiring the offset voltage adjustment signal includes: the amplifying unit sends the differential amplifying signal to the comparing unit to determine a deviation voltage in the differential amplifying signal, and the deviation adjusting unit receives the deviation voltage output by the comparing unit and outputs a deviation voltage adjusting signal according to the deviation voltage.
As shown in fig. 8, fig. 8 is a schematic flowchart of steps S01 to S03 in the offset adjustment method of the amplifier circuit according to the embodiment of the present application.
Before the above step S1 is executed, the following steps are executed in advance:
s01, the first switch subunit is switched off, the second switch subunit is switched on, and the second switch subunit sends a differential input signal to the amplifying unit;
s02 is configured to send the differential amplified signal to the comparing means when the differential amplified signal outputted from the amplifying means has a deviation, determine a deviation voltage in the differential amplified signal by the comparing means, and output the differential amplified signal.
S03 is a step of outputting a differential input signal from the output port if there is no variation in the differential amplified signal output from the amplifying section.
Fig. 9 shows a schematic flowchart of steps S21 to S22 in the offset adjustment method of the amplifier circuit according to the embodiment of the present application, where fig. 9 is a flowchart of steps S21 to S22.
The step S2 further includes:
s21 increases or decreases the offset voltage adjustment signal output by the offset adjustment unit.
S22, when the voltage of the adjusted differential amplified signal is inverted, maintains and stores the offset voltage adjustment signal outputted from the offset adjustment unit, and turns on the first switch subunit and turns off the second switch subunit to obtain the differential input signal at the next time.
The embodiment of the present application provides an amplifier, which includes a housing, and the amplifier circuit provided in the foregoing embodiment is disposed in the housing, and the amplifier circuit may be used to perform the offset adjustment method of the amplifier circuit in the foregoing embodiment.
An embodiment of the present application provides an electronic device, which includes the amplifier provided in the foregoing embodiment, and the amplifier performs the offset adjustment method of the amplifying circuit in the foregoing embodiment.
It should be noted that, in the several embodiments provided in the present application, the disclosed circuit and method may be implemented in other ways, as would be appreciated by one of ordinary skill in the art. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some interfaces, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (10)
1. An amplification circuit, comprising:
an input port for acquiring a differential input signal;
the amplifying unit is connected with the input port and used for amplifying the differential input signal and outputting a differential amplified signal;
the comparison unit is connected with the amplification unit and used for determining the deviation voltage in the differential amplification signal and outputting the differential amplification signal passing through the comparison unit;
the deviation adjusting unit is connected with the comparing unit and used for outputting a deviation voltage adjusting signal according to the deviation voltage;
and the output port is respectively connected with the comparison unit and the deviation adjustment unit and used for acquiring the differential amplification signal passing through the comparison unit and the deviation voltage adjustment signal, performing deviation voltage adjustment on the differential amplification signal passing through the comparison unit by using the deviation voltage adjustment signal and outputting the adjusted differential amplification signal.
2. The amplification circuit of claim 1, further comprising:
and the switch unit is respectively connected with the input port and the amplifying unit and is used for controlling the transmission path of the differential input signal.
3. The amplification circuit according to claim 2, wherein the transmission path of the differential input signal includes a first path and a second path connected in series, the switching unit includes:
the first switch subunit is connected with the input port and used for controlling the on-off of the first path;
and the second switch subunit is respectively connected with the first switch subunit and the amplifying unit and is used for controlling the on-off of the second path and outputting the differential input signal acquired from the first switch subunit to the amplifying unit when the second path is disconnected.
4. The amplification circuit according to any one of claims 1 to 3, wherein the offset adjustment unit includes:
the compensation voltage subunit is used for outputting a compensation voltage signal;
and the adjusting subunit is respectively connected with the output port, the comparing unit and the compensation voltage subunit, and is used for adjusting the compensation voltage signal according to the offset voltage and outputting an offset voltage adjusting signal according to the compensation voltage signal.
5. The amplification circuit of claim 4, further comprising:
and the control unit is respectively connected with the output port, the comparison unit and the deviation adjustment unit and is used for providing working voltage and working current for the comparison unit and the deviation adjustment unit, acquiring a clock signal and controlling the on-off of the output port according to the clock signal.
6. An offset adjustment method for an amplification circuit, the amplification circuit using the amplification circuit according to any one of claims 1 to 5, the offset adjustment method comprising:
acquiring a differential amplification signal and a deviation voltage adjustment signal;
performing deviation voltage adjustment on the differential amplification signal by using the deviation voltage adjustment signal, and outputting an adjusted differential amplification signal;
the method for acquiring the differential amplification signal comprises the following steps: the amplifying unit acquires a differential input signal input through an input port, and amplifies the differential input signal to obtain a differential amplified signal;
the method for acquiring the offset voltage adjustment signal comprises the following steps: the amplifying unit sends the differential amplifying signal to the comparing unit to determine a deviation voltage in the differential amplifying signal, and the deviation adjusting unit receives the deviation voltage output by the comparing unit and outputs a deviation voltage adjusting signal according to the deviation voltage.
7. The skew adjustment method according to claim 6, wherein before said obtaining the differential amplified signal, the skew adjustment method further comprises:
the first switch subunit is switched off, the second switch subunit is switched on, and the second switch subunit sends the differential input signal to the amplifying unit;
if the differential amplification signal output by the amplification unit has deviation, the differential amplification signal is sent to the comparison unit, the comparison unit determines the deviation voltage in the differential amplification signal and outputs the differential amplification signal;
and if the differential amplified signal output by the amplifying unit has no deviation, outputting the differential input signal through an output port.
8. The offset adjustment method according to claim 7, wherein the offset voltage adjusting the differential amplified signal using the offset voltage adjustment signal and outputting an adjusted differential amplified signal includes:
increasing or decreasing the offset voltage adjustment signal output by the offset adjustment unit;
and if the voltage of the adjusted differential amplification signal is inverted, maintaining and storing the offset voltage adjustment signal output by the offset adjustment unit, simultaneously switching on the first switch subunit, switching off the second switch subunit, and acquiring the differential input signal at the next moment.
9. An amplifier, comprising: a housing in which an amplification circuit according to any one of claims 1 to 5 is disposed, the amplification circuit performing the offset adjustment method according to any one of claims 6 to 8.
10. An electronic device, characterized in that the amplifier as claimed in claim 9 is provided in the electronic device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210510250.4A CN114629444B (en) | 2022-05-11 | 2022-05-11 | Amplifying circuit, deviation adjusting method thereof, amplifier and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210510250.4A CN114629444B (en) | 2022-05-11 | 2022-05-11 | Amplifying circuit, deviation adjusting method thereof, amplifier and electronic equipment |
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| CN114629444A true CN114629444A (en) | 2022-06-14 |
| CN114629444B CN114629444B (en) | 2022-08-23 |
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| US20010048344A1 (en) * | 2000-05-11 | 2001-12-06 | Martin Isken | Amplifier circuit with offset compensation, in particular for digital modulation devices |
| US6388521B1 (en) * | 2000-09-22 | 2002-05-14 | National Semiconductor Corporation | MOS differential amplifier with offset compensation |
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|---|---|
| CN114629444B (en) | 2022-08-23 |
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