CN114628233A - Semiconductor device preparation method - Google Patents
Semiconductor device preparation method Download PDFInfo
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- CN114628233A CN114628233A CN202210189807.9A CN202210189807A CN114628233A CN 114628233 A CN114628233 A CN 114628233A CN 202210189807 A CN202210189807 A CN 202210189807A CN 114628233 A CN114628233 A CN 114628233A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 239000010409 thin film Substances 0.000 claims abstract description 64
- 239000013077 target material Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 57
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims abstract description 39
- 238000004544 sputter deposition Methods 0.000 claims abstract description 37
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 27
- 239000010408 film Substances 0.000 claims abstract description 26
- 229910000449 hafnium oxide Inorganic materials 0.000 claims abstract description 10
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 48
- 239000003990 capacitor Substances 0.000 claims description 34
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- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/08—Oxides
- C23C14/083—Oxides of refractory metals or yttrium
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/3464—Sputtering using more than one target
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
Abstract
The invention discloses a preparation method of a semiconductor device, wherein the semiconductor device comprises a ferroelectric thin film layer, and the method comprises the following steps: and arranging a hafnium dioxide target material and a zirconium dioxide target material at the target material position, and sputtering the hafnium dioxide target material and the zirconium dioxide target material simultaneously to obtain the ferroelectric thin film layer. The application is to hafnium oxide (HfO)2) Target material and zirconium dioxide (ZrO)2) The target material is sputtered, so that the ferroelectric film layer with better ferroelectric property can be quickly obtained, and the production efficiency of the semiconductor device containing the ferroelectric film layer can be further improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device manufacturing method.
Background
The semiconductor refers to a material having a conductivity between a conductor and an insulator at normal temperature, and the semiconductor device is a device manufactured using a semiconductor, such as a memory device, a logic device, or the like. Among them, the discovery of ferroelectric thin films has promoted the development of semiconductor devices such as memory devices, logic devices, and the like.
In the related art, in the preparation of semiconductor devices such as memory devices and logic devices including ferroelectric thin films, the fabrication is mainly performed by ALD (Atomic Layer Deposition). However, the production efficiency of the ferroelectric thin film by the ALD method is low.
Disclosure of Invention
The embodiment of the application provides a method for manufacturing a semiconductor device, which solves the technical problem that the production efficiency of a semiconductor device containing a ferroelectric film is low due to the low production efficiency of the ferroelectric film in the prior art, and achieves the technical effects of improving the production efficiency of the ferroelectric film and further improving the production efficiency of the semiconductor device containing the ferroelectric film.
The application provides a semiconductor device preparation method, the semiconductor device comprises a ferroelectric thin film layer, and the method comprises the following steps:
arranging a hafnium dioxide target material and a zirconium dioxide target material at the target material position;
and sputtering the hafnium dioxide target material and the zirconium dioxide target material simultaneously to obtain the ferroelectric thin film layer.
Further, the purity of the hafnium dioxide target material and the purity of the zirconium dioxide target material are both at least 99%.
Further, sputtering the hafnium dioxide target material and the zirconium dioxide target material comprises:
sputtering a hafnium dioxide target material and a zirconium dioxide target material in the process of introducing argon, oxygen and nitrogen; wherein, the range of the introducing rate of the argon is 10-50 standard milliliters per minute, the range of the introducing rate of the oxygen is 0-10 standard milliliters per minute, and the range of the introducing rate of the nitrogen is 0-10 standard milliliters per minute.
Furthermore, the thickness range of the ferroelectric film layer is 3-70 nanometers.
Further, when the semiconductor device is a ferroelectric capacitor, the method further comprises:
and sequentially forming a first electrode, a ferroelectric film layer and a second electrode on the capacitor substrate layer to obtain the ferroelectric capacitor.
Furthermore, the first electrode and the second electrode are made of at least one material of titanium nitride, tungsten, tantalum nitride, high-conductivity silicon, iridium, ruthenium dioxide, platinum and palladium.
Further, a method of preparing the first electrode and/or the second electrode comprises:
and sputtering the titanium nitride target under the conditions that the beam voltage is 700-900V, the beam current is 40-60 mA, the accelerating voltage is 150-170V, and the gas is argon and nitrogen to obtain an electrode layer, wherein the flow rate of the argon is 7-9 standard milliliters per minute, and the flow rate of the nitrogen is 4-6 standard milliliters per minute.
Further, when the semiconductor device is a ferroelectric field effect transistor, the method further comprises:
sequentially preparing a grid dielectric layer, a ferroelectric film layer and a grid electrode on a transistor substrate layer to obtain a ferroelectric field effect transistor;
wherein the transistor substrate layer includes a source region and a drain region, and the gate dielectric layer is located between the source region and the drain region.
Furthermore, the thickness of the gate dielectric layer is in the range of 1-3 nm.
Furthermore, the dielectric constant of the manufacturing material of the gate dielectric layer is 3.9-25.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
according to the method, the hafnium dioxide (HfO2) target and the zirconium dioxide (ZrO2) target are sputtered simultaneously, so that the ferroelectric thin film layer with excellent ferroelectric property can be obtained quickly, and the production efficiency of the semiconductor device containing the ferroelectric thin film layer can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device provided in the present application;
FIG. 2 is a schematic structural diagram of a ferroelectric capacitor provided herein;
FIG. 3 is a schematic illustration of a polarization hysteresis curve of a ferroelectric capacitor or ferroelectric field effect transistor provided herein;
fig. 4-6 are schematic structural diagrams of ferroelectric capacitors with dielectric layers added based on fig. 2 provided herein;
fig. 7 is a schematic structural diagram of a ferroelectric field effect transistor provided herein;
fig. 8 is an Id-Vg curve obtained by testing the ferroelectric field effect transistor shown in fig. 7.
Reference numerals:
11-a capacitor substrate layer, 12-a first electrode, 13-a ferroelectric thin film layer, 14-a second electrode, an A-dielectric layer and a B-dielectric layer;
21-transistor substrate layer, 22-source region, 23-drain region, 24-gate dielectric layer, 25-ferroelectric thin film layer, 26-gate electrode.
Detailed Description
The embodiment of the application provides a semiconductor device manufacturing method, and solves the technical problem that the production efficiency of a semiconductor device containing a ferroelectric film is low due to the fact that the production efficiency of the ferroelectric film is low in the prior art.
In order to solve the technical problems, the general idea of the embodiment of the application is as follows:
a method of fabricating a semiconductor device, the semiconductor device including a ferroelectric thin film layer, the method comprising: and arranging a hafnium dioxide target material and a zirconium dioxide target material at the target material position, and sputtering the hafnium dioxide target material and the zirconium dioxide target material simultaneously to obtain the ferroelectric thin film layer.
This example is carried out by subjecting hafnium oxide (HfO)2) Target material and zirconium dioxide (ZrO)2) The target material is sputtered at the same time, so that the ferroelectric material with better ferroelectric property can be obtained quicklyThe ferroelectric thin film layer can further improve the production efficiency of a semiconductor device including the ferroelectric thin film layer.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
First, it is noted that the term "and/or" appearing herein is merely an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
The present embodiment provides a method for manufacturing a semiconductor device including a ferroelectric thin film layer, the method including step S11 and step S12 shown in fig. 1.
Step S11, arranging a hafnium dioxide target and a zirconium dioxide target at the target position;
step S12, for hafnium oxide (HfO)2) Target material and zirconium dioxide (ZrO)2) And sputtering the target material simultaneously to obtain the ferroelectric film layer.
In the related art, the ferroelectric thin film layer is mainly obtained by the ALD method, but with this method, the thin film growth rate is slow, which in turn results in low efficiency in manufacturing a semiconductor device.
This example was carried out by sputtering hafnium oxide (HfO)2) Target material and zirconium dioxide (ZrO)2) The ferroelectric thin film layer is obtained by using a target material, and specifically, sputtering methods such as magnetron sputtering, ion beam sputtering, direct current sputtering, reactive sputtering and the like can be used, which are not limited herein. In the embodiment, the ferroelectric film layer is grown in a sputtering mode, so that the growth speed of the film can be greatly improved. Sputtering hafnium oxide (HfO)2) Target material and zirconium dioxide (ZrO)2) When the target material is used, two target materials can be sputtered simultaneously so as to ensure hafnium oxide (HfO)2) And zirconium dioxide (ZrO)2) The ferroelectric thin film layer can be uniformly formed.
Compared with the ALD method, the sputtering method has higher efficiency, and the time spent on depositing the thin film with the same thickness is less than one sixth of the time spent on the ALD method. For example, a 10nm film may take at least 2 hours to deposit using ALD, and only about 20 minutes to deposit using sputtering. Therefore, the ferroelectric thin film layer is obtained by the sputtering method, so that the preparation time of the ferroelectric thin film layer can be greatly shortened, the preparation time of the semiconductor device can be further shortened, the preparation efficiency of the semiconductor device is improved, and the production efficiency of the semiconductor device is also improved.
When the ferroelectric thin film layer is prepared by the ALD method, impurities such as carbon C, hydrogen H, nitrogen N and the like are easily introduced, so that the ferroelectric property of the ferroelectric thin film layer is poor. This example uses HfO having a purity of at least 99%2Target material and ZrO2The target material is used for preparing the ferroelectric film layer, so that the impurity content in the ferroelectric film layer can be reduced, and the ferroelectric film layer is ensured to have better ferroelectric performance.
This embodiment is to HfO2Target material and ZrO2When the target material is sputtered, the method specifically comprises the following steps:
introducing Ar and oxygen O2And nitrogen gas N2In the process of (2), the first power is applied to HfO2Sputtering the hafnium oxide target material, and carrying out ZrO at a second power2And sputtering the target. Ar and O2And nitrogen gas N2The two gases may be introduced simultaneously or after mixing, and are not limited herein.
Wherein, the selection range of the first power and the selection range of the second power are 30-200W (watt). The flow rate range of argon is 10-50 sccm (standard milliliters per minute, flow unit), the flow rate range of oxygen is 0-10 sccm, and the flow rate range of nitrogen is 0-10 sccm.
The ferroelectric thin film layer obtained in the process parameter range has the characteristics of good film quality, excellent ferroelectric property, high reliability, small electric leakage, good breakdown characteristic, fatigue characteristic, awakening effect, retention characteristic and the like.
The thickness range of the ferroelectric thin film layer obtained in the embodiment is 3-70 nm (nanometers, distance units). Doped ZrO formed if the ferroelectric thin film layer has a thickness of less than about 3nm2The ferroelectric properties of the thin film are poor and it is difficult to realize practical applications, on the other hand, if the thickness of the ferroelectric thin film layer is greater than 70nm, the ferroelectric thin film layer may be too thick for advanced process technologies.
In summary, the present embodiment is implemented by applying hafnium oxide (HfO)2) Target material and zirconium dioxide (ZrO)2) The target material is sputtered, so that a ferroelectric film layer with better ferroelectric property can be quickly obtained, and the production efficiency of a semiconductor device containing the ferroelectric film layer can be further improved.
The ferroelectric thin film layer provided by this embodiment can be applied to ferroelectric semiconductor devices, such as ferroelectric capacitors and ferroelectric field effect transistors. The fabrication method of the semiconductor device will now be described by taking a ferroelectric capacitor and a ferroelectric field effect transistor as examples, respectively.
First, referring to fig. 2, a method for manufacturing a ferroelectric capacitor is described as follows:
a first electrode 12, a ferroelectric thin film layer 13, and a second electrode 14 are formed in this order on the capacitor substrate layer 11, to obtain a ferroelectric capacitor.
The capacitor substrate layer 11 is generally referred to as a substrate or a substrate layer, and herein, in order to distinguish the ferroelectric capacitor from the substrate of the ferroelectric field effect transistor, the substrate of the ferroelectric capacitor is referred to as the capacitor substrate layer 11, and the substrate of the ferroelectric field effect transistor is referred to as the transistor substrate layer.
The capacitor substrate layer 11 may be made of a semiconductor material, for example, a substrate made of silicon or silicon oxide alone, a multilayer substrate made of silicon and silicon oxide, or a semiconductor substrate made of germanium, gallium arsenide, or the like, which is not limited herein. When the capacitor substrate 11 is made of silicon, the thickness of the capacitor substrate 11 may be 500 um; when a multilayer substrate composed of silicon and silicon oxide is used, the thickness of silicon in the capacitor substrate 11 may be 500um, and the thickness of silicon oxide may be 300 nm.
The first electrode 12 and the second electrode 14 can be made of TiN, W, TaN, or TiN,High conductivity Si, Ir, Ru oxide RuO2At least one material selected from platinum Pt and palladium Pd. The first electrode 12 and the second electrode 14 may be obtained by a sputtering process, and may specifically include ion beam sputtering, direct current sputtering, reactive sputtering, and the like, without limitation.
Specifically, in this embodiment, the preparation process of the ferroelectric capacitor is described below by taking silicon Si as a substrate material, TiN as a first electrode 12 and a second electrode 14 material, preparing the first electrode 12 and the second electrode 14 by ion beam sputtering, and preparing the ferroelectric thin film layer 13 by magnetron sputtering.
Soaking and cleaning the substrate silicon by acetone and absolute ethyl alcohol in sequence for 3 min; and soaking and washing the substrate for 3min by using deionized water, and drying the substrate by blowing to finish the cleaning of the substrate silicon.
And 2, sputtering the cleaned substrate silicon by using an ion beam sputtering process to prepare a first electrode 12.
The beam current voltage is 700-900V (volt, voltage unit), the beam current is 40-60 mA (milliampere, current unit), the acceleration voltage is 150-170V, and the gas is argon Ar and nitrogen N2Sputtering the TiN target material to obtain a first electrode 12, wherein the flow rate of the argon Ar is 7-9 sccm, and the nitrogen N is2The flow rate of (2) is 4 to 6 sccm. Wherein the first electrode 12 is prepared to have a thickness of not less than 10 nm.
The roughness of the surface of the first electrode 12 prepared in the process range is less than 1nm, so that the leakage amount of the ferroelectric thin film layer 13 can be effectively reduced, and the generation of ferroelectric performance of the ferroelectric thin film layer 13 is facilitated.
For example, the beam current voltage is 800V, the beam current is 46mA, the acceleration voltage is 160V, and the gas is Ar and N2Mixed gas, Ar flow rate is 8sccm, N2The first electrode 12 is fabricated at a process parameter of 5sccm, and the thickness of the first electrode 12 may be 40 nm.
And 3, sputtering the first electrode 12 by using a magnetron sputtering process to prepare a ferroelectric thin film layer 13.
Firstly selecting HfO2Target material and ZrO2The purity of the two target materials is more than 99%; to mix HfO2Target material and ZrO2The target material is arranged on the magnetron sputtering coating equipment, and HfO is set based on an alternating current power supply2Target material and ZrO2Sputtering power of target material, wherein ZrO2The sputtering power can be between 30 and 200W, HfO2The sputtering power of (2) can be between 30 and 200W. The set range of the introduced Ar can be between 10sccm and 50sccm, O2The setting range of (b) can be between 0 to 10sccm, N2The setting range of (b) can be between 0 to 10 sccm. The parameters are adjusted within the process parameter range, so that the ferroelectric film with better quality can be obtained, and the generation of ferroelectricity is facilitated. In this embodiment, the thickness of the ferroelectric thin film layer 13 is 3 to 70 nm.
For example, ZrO may be specifically set2Sputtering power of 50W, HfO2The sputtering power of (2) is 80W; the flow rate of Ar introduced was set to 20sccm, and O was introduced2The flow rate of (2) was set to 0.2sccm, and N was introduced2The flow rate of (2) was set to 0sccm to obtain 10 nm-grown ZrO2A base ferroelectric thin film layer 13.
And 4, coating photoresist on the ferroelectric thin film layer 13, and exposing and developing.
For example, in ZrO2The base ferroelectric thin film layer 13 is coated with negative photoresist, and can be baked at 150 ℃ (centigrade, temperature unit) for 2min (minutes, time unit), baked at 120 ℃ for 2min after exposure, soaked in developing solution for 45s (seconds, time unit) for development, and then rinsed with deionized water for drying.
And 5, sputtering the ferroelectric film layer 13 by using an ion beam sputtering process to prepare a second electrode 14.
The beam current voltage is 700-900V, the beam current is 40-60 mA, the acceleration voltage is 150-170V, and the gas is argon Ar and nitrogen N2Sputtering the titanium nitride TiN target material to obtain a second electrode 14, wherein the flow rate of argon Ar is 7-9 sccm, and the flow rate of nitrogen is 4-6 sccm. The second electrode 14 is prepared to have a thickness of not less than 10 nm.
The roughness of the surface of the second electrode 14 prepared in the above process range is less than 1nm, which can effectively reduce the leakage amount of the ferroelectric thin film layer 13, and is beneficial to the generation of ferroelectric performance of the ferroelectric thin film layer 13.
For example, the beam current voltage is 800V, the beam current is 46mA, the acceleration voltage is 160V, and the gas is Ar and N2Mixed gas, Ar flow rate is 8sccm, N2The second electrode 14 is prepared at a process parameter of 5sccm, and the thickness of the second electrode 14 may be 40 nm.
And 6, removing the photoresist and the redundant metal to obtain the ferroelectric capacitor.
ZrO of the capacitor substrate layer 11, the first electrode 12, the ferroelectric thin film layer 13 and the second electrode 14 obtained through the steps 1 to 52Soaking the ferroelectric device in acetone solution until the photoresist and the redundant metal fall off; then soaking in absolute ethyl alcohol to remove acetone; and then the glass is washed by deionized water and dried. Rinsing and drying the ZrO2Based on ferroelectric devices in N2Annealing at 500 deg.C for 30s in an atmosphere (the temperature may be 400-700 deg.C, here 500 deg.C for example) to obtain ZrO2A ferroelectric capacitor.
Applying voltage excitation to the ferroelectric capacitor obtained in the above steps 1 to 6, specifically, grounding the second electrode 14, applying a dc voltage to the first electrode 12, and applying a voltage scanning mode, wherein the voltage value is increased from 0V to 3V, the applied pulse amplitude is 3V, and the pulse width is 200 μ s (microseconds, time unit), so as to obtain the polarization hysteresis curve as shown in fig. 3.
In summary, in the embodiment, the ferroelectric thin film layer 13 with good ferroelectric property and high reliability can be rapidly prepared by sputtering the hafnium dioxide target and the zirconium dioxide target, and the content of impurities in the ferroelectric thin film layer 13 can be reduced by sputtering the hafnium dioxide target and the zirconium dioxide target with high purity, so that the production efficiency of the ferroelectric capacitor with the ferroelectric thin film layer 13 is improved, and the prepared ferroelectric capacitor has good ferroelectric property.
In practical operation, a dielectric layer can be added on the basis of the ferroelectric capacitor shown in fig. 2, and the probability of electric leakage of the ferroelectric capacitor can be reduced by adding the dielectric layer.
A dielectric layer a, as shown in fig. 4, may be disposed between the first electrode 12 and the ferroelectric thin film layer 13. A dielectric layer B, as shown in fig. 5, may also be provided between the ferroelectric thin film layer 13 and the second electrode 14. Of course, dielectric layers, such as dielectric layer a and dielectric layer B shown in fig. 6, may be provided between the first electrode 12 and the ferroelectric thin film layer 13, and between the ferroelectric thin film layer 13 and the second electrode 14, respectively. The materials of the dielectric layer a and the dielectric layer B shown in fig. 6 may be the same or different, and this embodiment does not limit this.
The dielectric layers shown in fig. 4-6 may each be formed of a suitable dielectric material, such as silicon oxide, silicon nitride (SiN), a high K dielectric material having a dielectric constant (K value) greater than 3.9 (e.g., between about 3.9 and about 25), and so forth. The dielectric layer may be formed by a suitable formation method such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or a combination thereof.
The thickness of the dielectric layer may be selected from a range of about 1nm to about 3nm, such as between about 1nm and about 2nm, between about 2nm and about 3nm, or any other suitable thickness range. It should be noted that, in practical operation, it is necessary to avoid the dielectric layer being too thick, which may reduce the ferroelectric performance of the ferroelectric capacitor.
Next, a method for manufacturing a ferroelectric field effect transistor (FeFET) is described below with reference to fig. 7:
sequentially preparing a gate dielectric layer 24, a ferroelectric thin film layer 25 and a gate electrode 26 on the transistor substrate layer 21 to obtain a ferroelectric field effect transistor;
wherein the transistor substrate layer 21 includes a source region 22 and a drain region 23, and a gate dielectric layer 24 is located between the source region 22 and the drain region 23. The gate dielectric layer 24, ferroelectric thin film layer 25, and gate electrode 26 may be collectively referred to as a gate structure.
Specifically, a source region 22 and a drain region 23 are respectively located in the transistor substrate 21; a gate structure is located over the transistor substrate 21 and between the source region 22 and the drain region 23. A gate dielectric layer 24 in the gate structure is located over the transistor substrate 21; a ferroelectric thin film layer 25 is located over the gate dielectric layer 24; a gate electrode 26 is located over the ferroelectric thin film.
The transistor substrate layer 21 may be a doped or undoped semiconductor substrate (such as Ge) or may be a semiconductor-On-Insulator substrate (Silicon-On-Insulator, SOI, Silicon On an insulating substrate, which is a technique that introduces a buried oxide layer between the top Silicon and the backing substrate).
The semiconductor substrate may include other semiconductor materials, such as an elemental semiconductor, a compound semiconductor, or an alloy semiconductor, and may be a multilayer substrate or a gradient substrate. Wherein the compound semiconductor comprises SiC, GaAs, GaP, GaN, InP, InAs or InSb; alloy semiconductors including silicon germanium alloy SiGe, gallium arsenide phosphide GaAsP, indium aluminum arsenide AlInAs, aluminum gallium arsenide AlGaAs, gallium indium arsenide GaInAs, gallium indium phosphide GaInP or gallium indium arsenide phosphide GaInAsP.
Further, for an N-type semiconductor device, the source region 22 and the drain region 23 of the transistor substrate layer 21 may be doped with an N-type dopant such as arsenic or phosphorus. For P-type semiconductor devices, the source region 22 and the drain region 23 of the transistor substrate layer 21 may be doped with a P-type dopant, such as boron.
The ferroelectric thin film layer 25 is HfO2Doped ZrO2A film, wherein the atomic percentages between Hf, Zr, and O may be 0.7: 0.3: 2, but may be any other atomic percentage of Hf, Zr, and O that suitably induces ferroelectric properties.
After the ferroelectric thin film layer 25 is formed, a gate electrode 26 is formed over the ferroelectric thin film layer 25, and a thermal annealing process is performed at a temperature between about 400 ℃ to about 700 ℃. The gate electrode 26 may include a metal or metal-containing material such as TiN, TaN, W, copper Cu, or the like, and may be formed using a suitable formation method such as CVD, PVD, or ALD.
When the ferroelectric field effect transistor obtained in this embodiment is tested, the source region 22 is grounded, a dc voltage of-0.5V is applied to the drain region 23, and a dc voltage of +5V to-3V is applied to the gate electrode 26, so that an Id-Vg curve as shown in fig. 8 can be obtained. As can be seen from the Id-Vg curve shown in fig. 8, the ferroelectric field effect transistor prepared by using the scheme provided in this embodiment has better ferroelectric performance.
In summary, in the embodiment, the ferroelectric thin film layer 25 with good ferroelectric property and high reliability can be rapidly prepared by sputtering the hafnium dioxide target material and the zirconium dioxide target material, and the content of impurities in the ferroelectric thin film layer 25 can be reduced by sputtering the hafnium dioxide target material and the zirconium dioxide target material with high purity, so that the production efficiency of the ferroelectric field effect transistor with the ferroelectric thin film layer 25 is improved, and the prepared ferroelectric field effect transistor has good ferroelectric property.
Since the electronic device described in this embodiment is an electronic device used for implementing the method for processing information in this embodiment, a person skilled in the art can understand the specific implementation manner of the electronic device of this embodiment and various variations thereof based on the method for processing information described in this embodiment, and therefore, how to implement the method in this embodiment by the electronic device is not described in detail here. Electronic devices used by those skilled in the art to implement the method for processing information in the embodiments of the present application are all within the scope of the present application.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method of fabricating a semiconductor device, wherein the semiconductor device includes a ferroelectric thin film layer, the method comprising:
arranging a hafnium dioxide target material and a zirconium dioxide target material at the target material position;
and sputtering the hafnium dioxide target material and the zirconium dioxide target material simultaneously to obtain the ferroelectric thin film layer.
2. The method of claim 1, wherein the purity of the hafnium oxide target and the purity of the zirconium dioxide target are both at least 99%.
3. The method of claim 1, wherein sputtering the hafnium oxide target and the zirconium dioxide target comprises:
sputtering the hafnium dioxide target material and the zirconium dioxide target material in the process of introducing argon, oxygen and nitrogen; wherein, the range of the introducing rate of the argon is 10-50 standard milliliters per minute, the range of the introducing rate of the oxygen is 0-10 standard milliliters per minute, and the range of the introducing rate of the nitrogen is 0-10 standard milliliters per minute.
4. The method of claim 1, wherein the ferroelectric thin film layer has a thickness in a range of 3 to 70 nm.
5. The method of claim 1, wherein when the semiconductor device is a ferroelectric capacitor, the method further comprises:
and sequentially forming a first electrode, the ferroelectric film layer and a second electrode on the capacitor substrate layer to obtain the ferroelectric capacitor.
6. The method of claim 5, wherein the first electrode and the second electrode are made of at least one material selected from the group consisting of titanium nitride, tungsten, tantalum nitride, high conductivity silicon, iridium, ruthenium dioxide, platinum, and palladium.
7. The method of any of claims 5, wherein the method of preparing the first electrode and/or the second electrode comprises:
and sputtering the titanium nitride target under the conditions that the beam voltage is 700-900V, the beam current is 40-60 mA, the accelerating voltage is 150-170V, and the gas is argon and nitrogen to obtain an electrode layer, wherein the flow rate of the argon is 7-9 standard milliliters per minute, and the flow rate of the nitrogen is 4-6 standard milliliters per minute.
8. The method of claim 1, wherein when the semiconductor device is a ferroelectric field effect transistor, the method further comprises:
sequentially preparing a grid dielectric layer, the ferroelectric film layer and a grid electrode on a transistor substrate layer to obtain the ferroelectric field effect transistor;
wherein the transistor substrate layer includes a source region and a drain region, the gate dielectric layer being located between the source region and the drain region.
9. The method of claim 8, wherein the gate dielectric layer has a thickness in a range of 1nm to 3 nm.
10. The method of claim 8, wherein the gate dielectric layer is formed of a material having a dielectric constant in a range of 3.9 to 25.
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| CN115220141B (en) * | 2022-08-15 | 2024-05-17 | 安徽信息工程学院 | Wavelength division multiplexing optical filter and production method thereof |
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| CN115220141B (en) * | 2022-08-15 | 2024-05-17 | 安徽信息工程学院 | Wavelength division multiplexing optical filter and production method thereof |
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