CN114598174A - Active converter - Google Patents

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Publication number
CN114598174A
CN114598174A CN202210270218.3A CN202210270218A CN114598174A CN 114598174 A CN114598174 A CN 114598174A CN 202210270218 A CN202210270218 A CN 202210270218A CN 114598174 A CN114598174 A CN 114598174A
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China
Prior art keywords
switch
terminal
circuit
input
capacitor
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Granted
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CN202210270218.3A
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Chinese (zh)
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CN114598174B (en
Inventor
杨勇
陈胜伟
樊明迪
肖扬
陈蓉
何立群
杜贵府
谢门喜
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Suzhou University
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Suzhou University
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Priority to CN202210270218.3A priority Critical patent/CN114598174B/en
Priority to PCT/CN2022/086980 priority patent/WO2023173529A1/en
Publication of CN114598174A publication Critical patent/CN114598174A/en
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Publication of CN114598174B publication Critical patent/CN114598174B/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/70—Wind energy
    • Y02E10/76—Power conversion electric or electronic aspects

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The application discloses active converter relates to power electronics technical field. The input end of an input circuit of the active converter is connected with a direct-current power supply, a first output end of the input circuit is connected with a first switch, the first switch is connected with an output end of a T-shaped circuit, a second output end of the input circuit is connected with an input end of the T-shaped circuit, a third output end of the input circuit is connected with a second switch, the second switch is connected with an output end of the T-shaped circuit, an input end of a half-bridge circuit is connected with the input end of the input circuit and the output end of the T-shaped circuit, and ten output voltages are obtained at the output end of the half-bridge circuit. The input circuit consists of a plurality of 1/4 bridge arms, two switches connected in series are arranged on the bridge arms, and each bridge arm of the half-bridge circuit is provided with one switch. At the moment, the topological structure of the active converter uses few switching devices, so that the topological structure of the circuit is simple, and the voltage stress borne by the switch is smaller through the connection mode of the circuit, so that the active converter is free from loss.

Description

Active converter
Technical Field
The application relates to the technical field of power electronics, in particular to an active converter.
Background
With the development of new energy power generation, distributed power generation systems are more and more emphasized. Small power generating units, such as microturbines, roof-mounted photovoltaic and wind power systems, and commercially available fuel cells, are gaining widespread use at the electrical distribution level. Multilevel voltage-type converters (VSI) are gradually entering daily industrial production and life, and almost all small-sized generator sets use power electronic converters to achieve controlled and high-quality power exchange with single-phase power grids or local loads. The multilevel converter can be widely applied to high-power motor drive, high-voltage direct-current transmission, active power filters and distributed power generation systems. In the topology of the multilevel converter, the traditional topology structure includes a diode clamping type multilevel converter (NPC), a flying capacitor type multilevel converter (FC), and a cascade type multilevel Converter (CHB). However, as the output voltage level of the multilevel converter increases, the NPC and FC converters need to increase the number of clamping diodes and clamping capacitors on the one hand, and the CHB needs many isolated power supplies on the other hand, which makes the topology of the multilevel converter more and more complex.
The existing four-level active NPC converter (ANPC) is in the structure of a four-level hybrid clamping converter, and flying capacitors are removed. However, the topology structure still needs to use many switching devices, and the topology structure is complex. Meanwhile, when the four-level active converter is capable of outputting a higher level, the value of the input dc voltage needs to be increased, which causes the switching device to bear a very large voltage stress.
In view of the above problems, the search for an active converter with simple topology and less voltage stress to the switching device is a problem that those skilled in the art struggle to solve.
Disclosure of Invention
The aim of the application is to provide an active converter, the topological structure of which is simple and the switching devices in the active converter can bear less voltage stress.
In order to solve the above technical problem, the present application provides an active converter, including: the circuit comprises an input circuit, a T-shaped circuit, a first switch, a second switch and a half-bridge circuit.
The first input end of the input circuit is connected with the anode of the direct current power supply, the second input end of the input circuit is connected with the cathode of the direct current power supply, the first output end of the input circuit is connected with the first end of the first switch, the second end of the first switch is connected with the output end of the T-shaped circuit, the second output end of the input circuit is connected with the input end of the T-shaped circuit, the third output end of the input circuit is connected with the second end of the second switch, the first end of the second switch is connected with the output end of the T-shaped circuit, the first input end of the half-bridge circuit is connected with the first input end of the input circuit, the second input end of the half-bridge circuit is connected with the output end of the T-shaped circuit, the third input end of the half-bridge circuit is connected with the second input end of the input circuit, the output end of the half-bridge circuit is used for obtaining ten output voltages, the input circuit is composed of a plurality of 1/4 bridge arms, and two switches are arranged on the bridge arms in series connection, each bridge arm of the half-bridge circuit is provided with a switch.
Preferably, the input circuit comprises: the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor.
A first terminal of the third switch is connected to a first terminal of the first capacitor, a common terminal formed by the first terminal of the third switch and the first terminal of the first capacitor is used as a first input terminal of the input circuit, a second terminal of the third switch is connected to a first terminal of the fourth switch, a common terminal formed by the second terminal of the third switch and the first terminal of the fourth switch is used as a first output terminal of the input circuit, a second terminal of the fourth switch is connected to a common terminal formed by the second terminal of the first capacitor and the first terminal of the second capacitor, a second terminal of the second capacitor is connected to a common terminal formed by the first terminal of the third capacitor and the first terminal of the fifth switch, a second terminal of the fifth switch is connected to a first terminal of the sixth switch, a common terminal formed by the second terminal of the fifth switch and the first terminal of the sixth switch is used as a second output terminal of the input circuit, and a second terminal of the sixth switch is connected to a common terminal formed by the second terminal of the third capacitor and the first terminal of the fourth capacitor, the second end of the fourth capacitor is connected with a common end formed by the first end of the fifth capacitor and the first end of the seventh switch, the second end of the seventh switch is connected with the first end of the eighth switch, the common end formed by the second end of the seventh switch and the first end of the eighth switch is used as a third output end of the input circuit, the second end of the eighth switch is connected with the second end of the fifth capacitor, and the common end formed by the second end of the eighth switch and the second end of the fifth capacitor is used as a second input end of the input circuit.
Preferably, the T-type circuit comprises: ninth switch, tenth switch.
The first end of the ninth switch is used as the input end of the T-shaped circuit, the second end of the ninth switch is connected with the second end of the tenth switch, and the first end of the tenth switch is used as the output end of the T-shaped circuit.
Preferably, the half-bridge circuit comprises: an eleventh switch, a twelfth switch, and a load.
The first end of the eleventh switch is used as the first input end of the half-bridge circuit, the second end of the eleventh switch is connected with the first end of the twelfth switch, the common end formed by the second end of the eleventh switch and the first end of the twelfth switch is used as the second input end of the half-bridge circuit, the second end of the twelfth switch is used as the third input end of the half-bridge circuit, the second input end is connected with the first end of the load, and the second end of the load is used as the output end of the half-bridge circuit.
Preferably, the method further comprises the following steps: the inductance is compensated.
The first end of the compensation inductor is used as the second input end of the half-bridge circuit, the second end of the compensation inductor is connected with the first end of the load, and the second end of the load is used as the output end of the half-bridge circuit.
Preferably, the method further comprises the following steps: and a compensation capacitor.
The first end of the compensation capacitor is connected with the second end of the compensation inductor, and a common end formed by the second end of the compensation capacitor and the second end of the load is used as an output end of the half-bridge circuit.
Preferably, the first switch and the second switch are both MOS transistors.
Preferably, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch and the eighth switch are all MOS transistors.
Preferably, the ninth switch and the tenth switch are both MOS transistors.
Preferably, the eleventh switch and the twelfth switch are both MOS transistors.
The application provides an active converter, includes: the circuit comprises an input circuit, a T-shaped circuit, a first switch, a second switch and a half-bridge circuit. The input end of the input circuit is connected with a direct-current power supply, the first output end of the input circuit is connected with the first switch, the first switch is connected with the output end of the T-shaped circuit, the second output end of the input circuit is connected with the input end of the T-shaped circuit, the third output end of the input circuit is connected with the second switch, the second switch is connected with the output end of the T-shaped circuit, the input end of the half-bridge circuit is respectively connected with the input end of the input circuit and the output end of the T-shaped circuit, ten output voltages are obtained at the output end of the half-bridge circuit, the input circuit is composed of a plurality of 1/4 bridge arms, two switches connected in series are arranged on the bridge arms, and one switch is arranged on each bridge arm of the half-bridge circuit. At the moment, only a few switching devices are used in the topological structure of the active converter, so that the topological structure of the circuit is simple, and the voltage stress borne by the switches can be smaller through the connection mode of the input circuit, the first switch of the T-shaped circuit, the second switch and the half-bridge circuit, so that the active converter is protected from loss.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a circuit diagram of an active converter according to an embodiment of the present disclosure.
The input circuit 10 is a T-type circuit 11, and the half-bridge circuit 12.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
The core of the application is to provide an active converter, the topological structure of the active converter is simple, and the switching devices in the active converter can bear smaller voltage stress.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.
In actual production and life, at present, several current converters are a diode clamping type multi-level converter, a flying capacitor type multi-level converter, an active clamping converter (ANPC) and a three-level T-type converter (3L-T2I). The diode-clamped multilevel converter (NPC) mentioned above generates a multilevel ac voltage mainly through a clamping diode and a series dc capacitor. The topology of such a converter is generally capable of outputting three output voltages, four output voltages and five output voltages. However, in consideration of practical situations of production and life, only the three-level diode clamping type converter is practically applied to a medium-voltage high-power transmission system. The three-level diode clamped converter is typically an NPC converter. The output voltage of the NPC converter has smaller voltage change rate and Total Harmonic Distortion (THD) than that of the two-level converter. More importantly, the NPC converter can be applied to a medium-voltage transmission system with a certain voltage class without adopting devices connected in series. Wherein, it should be noted that the voltage value of the medium voltage transmission system is generally between 120V-10 kV.
The flying capacitor type multilevel converter is characterized in that a direct-current side capacitor in an NPC converter is unchanged, and a flying capacitor replaces a clamping diode. The working principle of the full-bridge three-phase inverter is similar to that of a diode clamping circuit, and 4 switching devices are arranged on one bridge arm of each full-bridge structure and are in a conducting or turning-off state at the same time to form 4 complementary switching device pairs. Due to the difference between the combination of the switching device pairs and the diode clamping type, the selection of the switching state is more flexible in terms of voltage synthesis.
An active clamp converter (ANPC) is an NPC converter and has the problems of inconsistent loss of bridge arm switching devices and unbalanced midpoint voltage, and the switching device generating the maximum loss in each phase of bridge arm determines the maximum switching frequency and the maximum output capacity of the active clamp converter. In order to solve the problem that the maximum loss switch determines the maximum switching frequency and the output capacity of the active clamp converter, a switching device is connected with an NPC diode in an inverse parallel mode. Compared with an NPC converter, the active clamp converter has more switching states and current conduction paths, so that the switching frequency or the output capacity of the converter is improved, and the quality of the output voltage waveform is further improved.
A three-level T-shaped converter (3L-T2I) is an improvement of a diode-clamped three-level converter, so that the advantages of good output waveform quality and high efficiency of the three-level converter are kept, and the number of power electronic devices and conduction loss are reduced.
In recent years, active converters have been developed to overcome the disadvantages of the conventional converters, and are gradually applied to industrial production. The path selector structure of the T-type three-level converter is integrated into a sub-circuit of the four-level active NPC converter, and a new topological structure is provided. When the novel topological structure is applied to medium-voltage application, even-numbered medium-output voltages are provided, a general mode of increasing output voltage types is correspondingly realized, and the number of switching devices is reduced compared with other topological structures of the same output voltage types. This topology can also be modified to higher even number output voltage active converters by increasing the number of switching devices, so this general structure is suitable for use in medium voltage applications where the utilization of higher dc voltages is increased.
Fig. 1 is a circuit diagram of an active converter according to an embodiment of the present disclosure. As shown in fig. 1, the active converter includes: the circuit comprises an input circuit 10, a T-shaped circuit 11, a first switch S1, a second switch S2 and a half-bridge circuit 12.
A first input end of the input circuit 10 is connected to an anode of the dc power supply, a second input end of the input circuit 10 is connected to a cathode of the dc power supply, a first output end of the input circuit 10 is connected to a first end of the first switch S1, a second end of the first switch S1 is connected to an output end of the T-type circuit 11, a second output end of the input circuit 10 is connected to an input end of the T-type circuit 11, a third output end of the input circuit 10 is connected to a second end of the second switch S2, a first end of the second switch S2 is connected to an output end of the T-type circuit 11, a first input end of the half-bridge circuit 12 is connected to a first input end of the input circuit 10, a second input end of the half-bridge circuit 12 is connected to an output end of the T-type circuit 11, a third input end of the half-bridge circuit 12 is connected to a second input end of the input circuit 10, an output end of the half-bridge circuit 12 is used for obtaining ten output voltages, the input circuit 10 is composed of a plurality of 1/4 legs, and the bridge arms are provided with two switches connected in series, and each bridge arm of the half-bridge circuit 12 is provided with one switch. Wherein, the first switch S1 and the second switch S2 may be both configured as MOS transistors.
When the first switch S1 and the second switch S2 are both configured as MOS transistors, the active transformer in this embodiment includes: the circuit comprises an input circuit 10, a T-shaped circuit 11, a first MOS tube, a second MOS tube and a half-bridge circuit 12. A first input end of the input circuit 10 is connected with an anode of a direct current power supply, a second input end of the input circuit 10 is connected with a cathode of the direct current power supply, a first output end of the input circuit 10 is connected with a drain electrode of a first MOS transistor, a source electrode of the first MOS transistor is connected with an output end of the T-type circuit 11, a second output end of the input circuit 10 is connected with an input end of the T-type circuit 11, a third output end of the input circuit 10 is connected with a source electrode of a second MOS transistor, a drain electrode of the second MOS transistor is connected with an output end of the T-type circuit 11, a first input end of the half-bridge circuit 12 is connected with the first input end of the input circuit 10, a second input end of the half-bridge circuit 12 is connected with an output end of the T-type circuit 11, a third input end of the half-bridge circuit 12 is connected with the second input end of the input circuit 10, an output end of the half-bridge circuit 12 is used for obtaining ten output voltages, the input circuit 10 is composed of a plurality of 1/4 bridge arms, and the bridge arms are provided with two switches connected in series, and each bridge arm of the half-bridge circuit 12 is provided with one switch.
At this time, the drain-source voltage difference of the first MOS transistor and the second MOS transistor can be obtained by controlling the voltages of the drains or the sources of the first MOS transistor and the second MOS transistor, and the conduction and the disconnection of the first MOS transistor and the second MOS transistor are controlled by the drain-source voltage difference. It should be noted that, the controller may also be configured to provide digital signals to the first switch S1 and the second switch S2 to control the on and off of the first switch S1 and the second switch S2, and the on and off states of the first switch S1 and the second switch S2 are represented by the digital signals. The digital signal mentioned here may be 1 bit, or 2 bits, 4 bits, 8 bits, 16 bits. When the digital signal is 1 bit, the digital signal is a high-low level signal, such as a high level signal "1" and a low level signal "0"; when the digital signal is 2 bits, the digital signal may have four representations, i.e., "00", "01", "10", "11", respectively; when the digital signal is 4 bits, the digital signal may be represented as a data string in the form of "0100"; when the digital signal is 8 bits, the digital signal may be represented as a data string in the form of "01001101"; when the digital signal is 16 bits, the digital signal may be represented as a data string in the form of "0100010001001101". The on and off of the first switch S1 and the second switch S2, the number of bits of the digital signal, and the representation of the digital signal are not limited, and may be implemented according to specific implementation scenarios. Meanwhile, the control modes of different MOS tubes can be the same or different, and the digital signals for controlling different MOS tubes can be the same or different. It can be understood that, only a few switching devices are used in the topology of the active converter, so that the topology of the circuit is simple, and the input circuit 10, the first switch S1, the second switch S2 and the half-bridge circuit 12 are connected in such a way that the voltage stress borne by the switches is small, thereby protecting the active converter from loss.
On the basis of the above-described embodiment, as a more preferred embodiment, the input circuit 10 includes: a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5.
A first terminal of the third switch S3 is connected to a first terminal of the first capacitor C1, a common terminal formed by the first terminal of the third switch S3 and the first terminal of the first capacitor C1 is used as a first input terminal of the input circuit 10, a second terminal of the third switch S3 is connected to a first terminal of the fourth switch S4, a common terminal formed by the second terminal of the third switch S3 and the first terminal of the fourth switch S4 is used as a first output terminal of the input circuit 10, a second terminal of the fourth switch S4 is connected to a common terminal formed by the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2, a second terminal of the second capacitor C2 is connected to a common terminal formed by the first terminal of the third capacitor C3 and the first terminal of the fifth switch S5, a second terminal of the fifth switch S5 is connected to a first terminal of the sixth switch S6, a second terminal of the fifth switch S5 and a first terminal of the sixth switch S6 are used as a second input terminal of the input circuit 10, a second terminal of the sixth switch S6 is connected to a common terminal formed by the second terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4, a second terminal of the fourth capacitor C4 is connected to a common terminal formed by the first terminal of the fifth capacitor C5 and the first terminal of the seventh switch S7, a second terminal of the seventh switch S7 is connected to the first terminal of the eighth switch S8, a common terminal formed by the second terminal of the seventh switch S7 and the first terminal of the eighth switch S8 serves as a third output terminal of the input circuit 10, a second terminal of the eighth switch S8 is connected to the second terminal of the fifth capacitor C5, and a common terminal formed by the second terminal of the eighth switch S8 and the second terminal of the fifth capacitor C5 serves as a second input terminal of the input circuit 10. The third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 may all be MOS transistors.
When the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 are all set as MOS transistors. The input circuit 10 includes: the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5. A drain of the third MOS transistor is connected to the first terminal of the first capacitor C1, a common terminal formed by the drain of the third MOS transistor and the first terminal of the first capacitor C1 is used as the first input terminal of the input circuit 10, a source of the third MOS transistor is connected to the drain of the fourth MOS transistor, a common terminal formed by the source of the third MOS transistor and the drain of the fourth MOS transistor is used as the first output terminal of the input circuit 10, a source of the fourth MOS transistor is connected to a common terminal formed by the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2, a second terminal of the second capacitor C2 is connected to a common terminal formed by the first terminal of the third capacitor C3 and the drain of the fifth MOS transistor, a source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, a common terminal formed by the source of the fifth MOS transistor and the drain of the sixth MOS transistor is used as the second output terminal of the input circuit 10, and a source of the sixth MOS transistor is connected to a common terminal formed by the second terminal of the third capacitor C3 and the common terminal of the fourth capacitor C4, a second terminal of the fourth capacitor C4 is connected to a common terminal formed by the first terminal of the fifth capacitor C5 and the drain of the seventh MOS transistor, a source of the seventh MOS transistor is connected to the drain of the eighth MOS transistor, a common terminal formed by the source of the seventh MOS transistor and the drain of the eighth MOS transistor serves as a third output terminal of the input circuit 10, a source of the eighth MOS transistor is connected to the second terminal of the fifth capacitor C5, and a common terminal formed by the source of the eighth MOS transistor and the second terminal of the fifth capacitor C5 serves as a second input terminal of the input circuit 10.
At this time, the drain-source voltage difference of the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor can be obtained by controlling the voltage of the drain or the source of the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor, and the conduction and the disconnection of the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor can be controlled by the drain-source voltage difference. It should be noted that, the controller may also be configured to provide digital signals to the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 to control the on and off of the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8, and the on and off states of the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 are represented by the digital signals. The digital signal mentioned here may be 1 bit, or 2 bits, 4 bits, 8 bits, 16 bits. When the digital signal is 1 bit, the digital signal is a high-low level signal, such as a high level signal "1" and a low level signal "0"; when the digital signal is 2 bits, the digital signal may have four representations, i.e., "00", "01", "10", "11", respectively; when the digital signal is 4 bits, the digital signal may be represented as a data string in the form of "0100"; when the digital signal is 8 bits, the digital signal may be represented as a data string in the form of "01001101"; when the digital signal is 16 bits, the digital signal may be represented as a data string in the form of "0100010001001101". The third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are not limited to be controlled to be turned on or off, the number of bits of the digital signal, and the representation form of the digital signal, and specific implementations thereof may be determined according to specific implementation scenarios. Meanwhile, the control modes of different MOS tubes can be the same or different, and the digital signals for controlling different MOS tubes can be the same or different. It can be understood that, on the basis of the above embodiments, compared with the topology of the input circuit 10 of the conventional active converter, fewer switching devices are used, so that the topology of the circuit is simple, and the input circuit 10, the T-shaped circuit 11, the first switch S1, the second switch S2, and the half-bridge circuit 12 are connected in such a way that the voltage stress borne by the switches is small, thereby protecting the active converter from loss. Meanwhile, it should be noted that the types and models of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 mentioned in this embodiment and the withstanding voltage that the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 can bear are not limited as long as the types and models can meet the normal operation of the input circuit 10, and a specific implementation manner of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 can be determined according to a specific implementation scenario.
On the basis of the above-described embodiment, as a more preferred embodiment, the T-type circuit 11 includes: ninth switch S9, tenth switch S10. A first terminal of the ninth switch S9 is used as an input terminal of the T-type circuit 11, a second terminal of the ninth switch S9 is connected to a second terminal of the tenth switch S10, and a first terminal of the tenth switch S10 is used as an output terminal of the T-type circuit 11. Wherein, the ninth switch S9 and the tenth switch S10 may be both configured as MOS transistors.
When the ninth switch S9 and the tenth switch S10 are both provided as MOS transistors, the T-type circuit 11 in the present embodiment includes: ninth MOS pipe, tenth MOS pipe. The drain of the ninth MOS transistor is used as the input terminal of the T-type circuit 11, the source of the ninth MOS transistor is connected to the source of the tenth MOS transistor, and the drain of the tenth MOS transistor is used as the output terminal of the T-type circuit 11.
At this time, the drain-source voltage difference between the ninth MOS transistor and the tenth MOS transistor can be obtained by controlling the voltages of the drains or the sources of the ninth MOS transistor and the tenth MOS transistor, and the ninth MOS transistor and the tenth MOS transistor are controlled to be turned on and off by the drain-source voltage difference. It should be noted that, the controller may also be configured to provide digital signals to the ninth switch S9 and the tenth switch S10 to control the on and off of the ninth switch S9 and the tenth switch S10, and the on and off states of the ninth switch S9 and the tenth switch S10 are represented by the digital signals. The digital signal mentioned here may be 1 bit, or 2 bits, 4 bits, 8 bits, 16 bits. When the digital signal is 1 bit, the digital signal is a high-low level signal, such as a high level signal "1" and a low level signal "0"; when the digital signal is 2 bits, the digital signal may have four representations, i.e., "00", "01", "10", "11", respectively; when the digital signal is 4 bits, the digital signal may be represented as a data string in the form of "0100"; when the digital signal is 8 bits, the digital signal may be represented as a data string in the form of "01001101"; when the digital signal is 16 bits, the digital signal may be represented as a data string in the form of "0100101001001101". The on and off of the ninth switch S9 and the tenth switch S10, the number of bits of the digital signal, and the representation of the digital signal are not limited, and may be implemented according to specific implementation scenarios. Meanwhile, the control modes of different MOS tubes can be the same or different, and the digital signals for controlling different MOS tubes can be the same or different.
It can be understood that, on the basis of the above embodiments, compared with the topology of the T-shaped circuit 11 of the conventional active converter, fewer switching devices are used, so that the topology of the circuit is simple, and the input circuit 10, the T-shaped circuit 11, the first switch S1, the second switch S2, and the half-bridge circuit 12 are connected in such a way that the voltage stress borne by the switches is small, thereby protecting the active converter from loss.
On the basis of the above-described embodiment, as a more preferred embodiment, the half-bridge circuit 12 includes: an eleventh switch S11, a twelfth switch S12, and a load R. A first terminal of the eleventh switch S11 is used as a first input terminal of the half-bridge circuit 12, a second terminal of the eleventh switch S11 is connected to a first terminal of the twelfth switch S12, a common terminal formed by the second terminal of the eleventh switch S11 and the first terminal of the twelfth switch S12 is used as a second input terminal of the half-bridge circuit 12, a second terminal of the twelfth switch S12 is used as a third input terminal of the half-bridge circuit 12, a second input terminal is connected to a first terminal of the load R, and a second terminal of the load R is used as an output terminal of the half-bridge circuit 12. The eleventh switch S11 and the twelfth switch S12 may be both provided as MOS transistors.
When the eleventh switch S11 and the twelfth switch S12 are both configured as MOS transistors, the half-bridge circuit 12 in the present embodiment includes: an eleventh MOS tube, a twelfth MOS tube and a load R. The drain of the eleventh MOS transistor is used as the first input terminal of the half-bridge circuit 12, the source of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, the common terminal formed by the source of the eleventh MOS transistor and the drain of the twelfth MOS transistor is used as the second input terminal of the half-bridge circuit 12, the source of the twelfth MOS transistor is used as the third input terminal of the half-bridge circuit 12, the second input terminal is connected to the first terminal of the load R, and the second terminal of the load R is used as the output terminal of the half-bridge circuit 12.
At this time, the drain-source voltage difference between the eleventh MOS transistor and the twelfth MOS transistor can be obtained by controlling the voltages of the drains or the sources of the eleventh MOS transistor and the twelfth MOS transistor, and the turn-on and turn-off of the eleventh MOS transistor and the twelfth MOS transistor are controlled by the drain-source voltage difference. It should be noted that, the controller may also provide digital signals to the eleventh switch S11 and the twelfth switch S12 to control the on and off of the eleventh switch S11 and the twelfth switch S12, and the on and off states of the eleventh switch S11 and the twelfth switch S12 are represented by the digital signals. The digital signal mentioned here may be 1 bit, or 2 bits, 4 bits, 8 bits, 16 bits. When the digital signal is 1 bit, the digital signal is a high-low level signal, such as a high level signal "1" and a low level signal "0"; when the digital signal is 2 bits, the digital signal may have four representations, i.e., "00", "01", "10", "11", respectively; when the digital signal is 4 bits, the digital signal may be represented as a data string in the form of "0100"; when the digital signal is 8 bits, the digital signal may be represented as a data string in the form of "01001101"; when the digital signal is 16 bits, the digital signal may be represented as a data string in the form of "0100010001001101". The on/off control of the eleventh switch S11 and the twelfth switch S12, the number of bits of the digital signal, and the representation of the digital signal are not limited, and the specific implementation may be determined according to specific implementation scenarios. Meanwhile, the control modes of different MOS tubes can be the same or different, and the digital signals for controlling different MOS tubes can be the same or different.
It can be understood that, on the basis of the above-mentioned embodiments, compared with the topology of the half-bridge circuit 12 of the conventional active converter, fewer switching devices are used, so that the topology of the circuit is simple, and the input circuit 10, the T-shaped circuit 11, the first switch S1, the second switch S2, and the half-bridge circuit 12 are connected in such a way that the voltage stress borne by the switches is small, thereby protecting the active converter from loss.
On the basis of the above embodiment, as a more preferred embodiment, the method further includes: the inductance Lf is compensated.
The first end of the compensation inductor Lf serves as the second input end of the half-bridge circuit 12, the second end of the compensation inductor Lf is connected with the first end of the load R, and the second end of the load R serves as the output end of the half-bridge circuit 12.
It should be noted that, the type and model of the compensation inductor Lf mentioned in this embodiment and the tolerable withstand voltage thereof are not limited, as long as the compensation inductor Lf can satisfy the normal operation of the active converter, and the specific implementation manner thereof may be determined according to specific implementation scenarios.
It can be understood that compared with the topology of the conventional active converter, fewer switching devices are used, so that the topology of the circuit is simple, the compensation inductance Lf is added on the basis of the above embodiment, and the voltage stress borne by the switches can be smaller through the connection manner of the input circuit 10, the T-shaped circuit 11, the first switch S1, the second switch S2 and the half-bridge circuit 12, so as to protect the active converter from loss, and at the same time, due to the existence of the compensation inductance Lf, the coupling and transmission efficiency of the system are improved.
On the basis of the above embodiment, as a more preferred embodiment, the method further includes: a compensation capacitor Cf.
A first terminal of the compensation capacitor Cf is connected to a second terminal of the compensation inductor Lf, and a common terminal formed by the second terminal of the compensation capacitor Cf and the second terminal of the load R serves as an output terminal of the half-bridge circuit 12.
It should be noted that, the type and model of the compensation capacitor Cf mentioned in this embodiment and the withstanding voltage of the compensation capacitor Cf are not limited, as long as the compensation capacitor Cf can satisfy the normal operation of the active converter, and the specific implementation manner of the compensation capacitor Cf may be determined according to the specific implementation scenario.
It can be understood that compared with the topology structure of the conventional active converter, fewer switching devices are used, so that the topology structure of the circuit is simple, the compensation capacitor Cf is added on the basis of the above embodiment, and the voltage stress borne by the switches can be smaller through the connection mode of the input circuit 10, the T-shaped circuit 11, the first switch S1, the second switch S2 and the half-bridge circuit 12, so as to protect the active converter from loss, and at the same time, due to the existence of the compensation capacitor Cf, the coupling and transmission efficiency of the system are improved.
Note that all the switches mentioned in the above embodiments constitute the plurality of arms of the input circuit 10, the T-shaped circuit 11, and the arms of the half-bridge circuit 12, respectively. The input circuit 10 includes three arms, which may be referred to as a first arm, a second arm, and a third arm, respectively; the half-bridge circuit 12 includes two arms, which may be referred to as a fourth arm and a fifth arm, respectively. And the third switch S3 and the fourth switch S4 constitute a first leg of the input circuit 10; fifth switch S5 and sixth switch S6 form a second leg of input circuit 10; the seventh switch S7 and the eighth switch S8 constitute a third leg of the input circuit 10. The ninth switch S9 and the tenth switch S10 constitute a T-type circuit 11. The eleventh switch S11 forms the fourth leg of the half bridge circuit 12; the twelfth switch S12 constitutes the fifth leg of the half bridge circuit 12.
The topology structure of the active converter totally adopts 12 switches: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, and 5 capacitors: the capacitor comprises a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5. Wherein, the first switch S1 and the tenth switch S10, the second switch S2 and the ninth switch S9, the third switch S3 and the fourth switch S4, the fifth switch S5 and the sixth switch S6, the seventh switch S7 and the eighth switch S8, and the eleventh switch S11 and the twelfth switch S12 are 6 sets of switches with complementary digital logic respectively. The logic relationships are shown in table 1, and since all the switches mentioned above have complementary logic relationships with the corresponding switches, table 1 shows only the digital logic states of the first switch S1, the third switch S3, the fifth switch S5, the seventh switch S7, the ninth switch S9 and the eleventh switch S11, and the digital signal indicating the conduction of all the switches mentioned above is a high-level signal with "1" bit; the off digital signal of all the switches is a low level signal of "0" 1 bit.
Table 1: digital logic states of active NPC converters
S1 S3 S5 S7 S9 S10 Output voltage On-off state
0 0 0 0 0 0 0 V1
0 0 0 0 0 1 0 V2
1 1 1 1 1 1 0 V3
0 0 0 1 0 0 Vdc/5 V4
1 0 1 1 1 1 -Vdc/5 V5
0 0 0 1 1 0 2Vdc/5 V6
0 0 1 1 1 1 -2Vdc/5 V7
0 0 1 1 1 0 3Vdc/5 V8
0 0 0 1 1 1 -3Vdc/5 V9
1 0 1 1 1 0 4Vdc/5 V10
0 0 0 1 0 1 -4Vdc/5 V11
1 1 1 1 1 0 Vdc V12
Note that, the digital logic states of the first switch S1, the third switch S3, the fifth switch S5, the seventh switch S7, the ninth switch S9, and the eleventh switch S11 shown in table 1. When the active converter is applied to be converted from the V4 switching state corresponding to the output voltage value of Vdc/5 to the switching state corresponding to the output voltage value of Vdc/5, the switch which is required to be converted into the minimum on and off is required to save the power loss of the active converter, so that the active converter can be selectively converted into the V1 switching state, and at this time, the seventh switch S7 is only required to be controlled to be switched off, and the eighth switch S8 is only required to be controlled to be switched on. Compared with the existing active converter which can only output three, four or five output voltages, the active converter can realize ten output voltages and has six switching states, and can select the switch-on and switch-off of the switch which is least changed when the switching states are switched.
The active converter provided by the application reduces the total number of used switches to twelve by integrating the T-shaped structure into the four-level active converter and compared with other topological structures with the same output voltage number, the active converter does not use any flying capacitor or clamping diode. The method can obtain better performance under the condition of being applied to medium-voltage application with higher working voltage, and generates lower voltage step and harmonic voltage distortion of output voltage.
The active converter provided by the present application is described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, without departing from the principle of the present application, the present application can also make several improvements and modifications, and those improvements and modifications also fall into the protection scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

Claims (10)

1. An active current transformer, comprising: an input circuit (10), a T-shaped circuit (11), a first switch, a second switch and a half-bridge circuit (12);
the first input end of the input circuit (10) is connected with the positive pole of a direct current power supply, the second input end of the input circuit (10) is connected with the negative pole of the direct current power supply, the first output end of the input circuit (10) is connected with the first end of the first switch, the second end of the first switch is connected with the output end of the T-shaped circuit (11), the second output end of the input circuit (10) is connected with the input end of the T-shaped circuit (11), the third output end of the input circuit (10) is connected with the second end of the second switch, the first end of the second switch is connected with the output end of the T-shaped circuit (11), the first input end of the half-bridge circuit (12) is connected with the first input end of the input circuit (10), the second input end of the half-bridge circuit (12) is connected with the output end of the T-shaped circuit (11), the third input end of the half-bridge circuit (12) is connected with the second input end of the input circuit (10), the output end of the half-bridge circuit (12) is used for obtaining ten kinds of output voltage, the input circuit (10) is composed of a plurality of 1/4 bridge arms, two switches connected in series are arranged on the bridge arms, and one switch is arranged on each bridge arm of the half-bridge circuit (12).
2. Active converter according to claim 1, characterized in that said input circuit (10) comprises: the first switch, the second switch, the third switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor;
a first terminal of the third switch is connected to a first terminal of the first capacitor, a common terminal formed by the first terminal of the third switch and the first terminal of the first capacitor is used as the first input terminal of the input circuit (10), a second terminal of the third switch is connected to a first terminal of the fourth switch, a common terminal formed by the second terminal of the third switch and the first terminal of the fourth switch is used as the first output terminal of the input circuit (10), a second terminal of the fourth switch is connected to a common terminal formed by the second terminal of the first capacitor and the first terminal of the second capacitor, a second terminal of the second capacitor is connected to a common terminal formed by the first terminal of the third capacitor and the first terminal of the fifth switch, a second terminal of the fifth switch is connected to the first terminal of the sixth switch, and a common terminal formed by the second terminal of the fifth switch and the first terminal of the sixth switch is used as the input circuit (b) 10) The second terminal of the sixth switch is connected to a common terminal formed by the second terminal of the third capacitor and the first terminal of the fourth capacitor, the second terminal of the fourth capacitor is connected to a common terminal formed by the first terminal of the fifth capacitor and the first terminal of the seventh switch, the second terminal of the seventh switch is connected to the first terminal of the eighth switch, the common terminal formed by the second terminal of the seventh switch and the first terminal of the eighth switch serves as the third output terminal of the input circuit (10), the second terminal of the eighth switch is connected to the second terminal of the fifth capacitor, and the common terminal formed by the second terminal of the eighth switch and the second terminal of the fifth capacitor serves as the second input terminal of the input circuit (10).
3. Active converter according to claim 1, characterized in that said T-circuit (11) comprises: a ninth switch and a tenth switch;
the first end of the ninth switch is used as the input end of the T-shaped circuit (11), the second end of the ninth switch is connected with the second end of the tenth switch, and the first end of the tenth switch is used as the output end of the T-shaped circuit (11).
4. Active converter according to claim 1, characterized in that said half-bridge circuit (12) comprises: an eleventh switch, a twelfth switch, a load;
a first terminal of the eleventh switch serves as the first input terminal of the half-bridge circuit (12), a second terminal of the eleventh switch is connected to a first terminal of the twelfth switch, a common terminal formed by the second terminal of the eleventh switch and the first terminal of the twelfth switch serves as the second input terminal of the half-bridge circuit (12), a second terminal of the twelfth switch serves as the third input terminal of the half-bridge circuit (12), the second input terminal is connected to a first terminal of the load, and the second terminal of the load serves as an output terminal of the half-bridge circuit (12).
5. The active current transformer of claim 4, further comprising: compensating the inductance;
the first end of the compensation inductance is used as the second input end of the half-bridge circuit (12), the second end of the compensation inductance is connected with the first end of the load, and the second end of the load is used as the output end of the half-bridge circuit (12).
6. The active current transformer of claim 5, further comprising: a compensation capacitor;
the first end of the compensation capacitor is connected with the second end of the compensation inductor, and a common end formed by the second end of the compensation capacitor and the second end of the load is used as an output end of the half-bridge circuit (12).
7. The active current transformer of claim 1, wherein the first switch and the second switch are both MOS transistors.
8. The active power converter according to claim 2, wherein the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch and the eighth switch are all MOS transistors.
9. The active power converter of claim 3, wherein the ninth switch and the tenth switch are both MOS transistors.
10. The active converter according to claim 4, wherein the eleventh switch and the twelfth switch are both MOS transistors.
CN202210270218.3A 2022-03-18 2022-03-18 Active current transformer Active CN114598174B (en)

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CN208539800U (en) * 2018-04-13 2019-02-22 江苏固德威电源科技股份有限公司 Single-phase 11 electrical level inverter

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JP5780907B2 (en) * 2011-09-30 2015-09-16 株式会社東芝 Power converter
CA3006344C (en) * 2015-11-13 2024-01-02 Marquette University A fault-tolerant topology for multilevel t-type converters
CN107994794B (en) * 2017-12-29 2019-11-08 重庆大学 The double-T shaped four level inverse conversions unit of one kind and its application circuit and modulator approach

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Publication number Priority date Publication date Assignee Title
CN104767392A (en) * 2014-01-06 2015-07-08 通用电气公司 System and method of power conversion
CN105337521A (en) * 2014-08-11 2016-02-17 通用电气能源电能变换科技有限公司 Multi-level converter
CN208539800U (en) * 2018-04-13 2019-02-22 江苏固德威电源科技股份有限公司 Single-phase 11 electrical level inverter

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