CN114597134A - Semiconductor packaging device and preparation method thereof - Google Patents

Semiconductor packaging device and preparation method thereof Download PDF

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Publication number
CN114597134A
CN114597134A CN202210056460.0A CN202210056460A CN114597134A CN 114597134 A CN114597134 A CN 114597134A CN 202210056460 A CN202210056460 A CN 202210056460A CN 114597134 A CN114597134 A CN 114597134A
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China
Prior art keywords
layer
chip
protective layer
main surface
plastic packaging
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Chinese (zh)
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李尚轩
仇阳阳
庄佳铭
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Nantong Tongfu Microelectronics Co ltd
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Nantong Tongfu Microelectronics Co ltd
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Priority to CN202210056460.0A priority Critical patent/CN114597134A/en
Publication of CN114597134A publication Critical patent/CN114597134A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application discloses a semiconductor packaging device and a preparation method thereof, and belongs to the technical field of semiconductor packaging. The preparation method comprises the steps of firstly providing a first packaging body, wherein the first packaging body comprises a chip, a first conductive column and a protective layer, the chip is provided with a first main surface and a second main surface which are oppositely arranged, the first main surface is provided with a plurality of chip electrodes, the first conductive column is positioned at the position of the chip electrodes and is electrically connected with the corresponding chip electrodes, and the protective layer covers the first conductive column; forming a first plastic packaging layer, wherein the first plastic packaging layer covers the first packaging body from one side of the first main surface, and the second main surface is exposed from the first plastic packaging layer; removing part of the first plastic packaging layer and part of the protective layer from one side of the first main surface so that one end, away from the chip, of the first conductive post is exposed from the protective layer and the first plastic packaging layer; and the flatness of the surface of one side, which deviates from the chip, of the protective layer is greater than the flatness of the surface of one side, which deviates from the chip, of the first plastic packaging layer. The reliability of the semiconductor packaging device can be improved.

Description

Semiconductor packaging device and preparation method thereof
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor package device and a method for manufacturing the same.
Background
In packaging semiconductor chips, a plastic molding process is generally used, i.e., the chips are embedded in an Epoxy Molding Compound (EMC). However, the plastic package layer formed by the epoxy molding compound is rough in material and low in surface flatness, and when the plastic package body is further processed subsequently, the interface stability of the combination of other functional layers and the plastic package layer is not enough, so that the other functional layers and the plastic package layer are easily layered, the electric connection between the chip and the other functional layers is influenced, and the reliability of the semiconductor package device is reduced.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a semiconductor packaging device and a preparation method thereof, which can improve the reliability of the semiconductor packaging device.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a method for manufacturing a semiconductor package device, including:
providing a first packaging body, wherein the first packaging body comprises a chip, a first conductive column and a protective layer, the chip is provided with a first main surface and a second main surface which are arranged oppositely, the first main surface is provided with a plurality of chip electrodes, the first conductive column is positioned at the position of the chip electrodes and is electrically connected with the corresponding chip electrodes, and the protective layer covers the first conductive column;
forming a first plastic packaging layer, wherein the first plastic packaging layer covers the first packaging body from the side of the first main surface, and the second main surface is exposed out of the first plastic packaging layer;
removing a part of the first plastic packaging layer and a part of the protective layer from the first main surface side, so that one end, far away from the chip, of the first conductive pillar is exposed from the protective layer and the first plastic packaging layer; the flatness of the surface of one side, which deviates from the chip, of the protective layer is greater than the flatness of the surface of one side, which deviates from the chip, of the first plastic packaging layer.
Optionally, the step of providing the first package body includes:
providing a wafer, wherein the wafer comprises a plurality of chips arranged in an array, cutting channels are arranged between the adjacent chips, and sacrificial layers are covered in the cutting channels;
forming a plurality of first conductive columns on one side of the wafer, which is provided with the chip electrodes;
forming the protective layer on one side of the wafer, which is provided with the chip electrode, wherein the protective layer continuously covers all the first conductive columns;
removing the protective layer and the sacrificial layer at the position corresponding to the cutting channel to expose the cutting channel;
and cutting the wafer along the cutting channels to obtain a plurality of first packaging bodies.
Optionally, the step of removing the protection layer and the sacrificial layer at the position corresponding to the scribe line includes:
removing the protective layer at the position corresponding to the cutting channel by using a laser grooving process to form a first through groove exposing the sacrificial layer;
removing the sacrificial layer exposed by the first through groove by using a laser grooving process to expose the cutting channel; the size of one end, close to the cutting channel, of the first through groove is larger than or equal to that of the cutting channel.
Optionally, the step of forming a first molding layer includes:
attaching the first package body to a carrier plate, wherein the second main surface faces the carrier plate;
forming the first plastic package layer on the surface of one side of the carrier plate, to which the first package body is attached, wherein the first plastic package layer covers the first package body;
and removing the carrier plate.
Optionally, the number of the first package bodies is plural, the first molding compound layer continuously covers all the first package bodies, and the plurality of chips included in the plurality of first package bodies have at least two different functions.
Optionally, after the step of removing a portion of the first molding layer and a portion of the protective layer from the first main surface side, the method further includes:
forming a first insulating layer on one side, close to the first conductive pillars, of the first plastic packaging layer and patterning the first insulating layer to form a plurality of first through holes exposing the first conductive pillars;
forming a first metal layer on one side, away from the first plastic packaging layer, of the first insulating layer and patterning the first metal layer to form a first rewiring layer; wherein in response to the number of the first packages being one, the first rewiring layer includes a plurality of first rewiring electrodes, one of the first rewiring electrodes being electrically connected to one of the first conductive pillars through one of the first connection holes; in response to the number of the first packages being a plurality, the first redistribution layer further includes at least one series electrode connecting two adjacent chips in series.
Optionally, the first insulating layer and the protection layer are made of the same material.
In order to solve the above technical problem, another technical solution adopted by the present application is: the semiconductor packaging device is prepared by the preparation method of the semiconductor packaging device in the technical scheme, and comprises the following steps:
a chip having first and second oppositely disposed major surfaces, the first major surface having a plurality of chip electrodes;
the first conductive columns are positioned at the positions of the chip electrodes and are electrically connected with the corresponding chip electrodes;
a protective layer on the first main surface and covering only the side surfaces of the first conductive posts;
the first plastic packaging layer only covers the side face of the chip and the side face of the protective layer; the flatness of the surface of one side, which deviates from the chip, of the protective layer is greater than the flatness of the surface of one side, which deviates from the chip, of the first plastic packaging layer.
Optionally, the semiconductor package device further comprises:
the first plastic packaging layer is positioned on one side, close to the first conductive column, of the first insulating layer, and a plurality of first connecting holes exposing the first conductive column are formed in the first insulating layer;
the first rewiring layer is positioned on one side, away from the first plastic packaging layer, of the first insulating layer; in response to the number of the chips being one, the first rewiring layer includes a plurality of first rewiring electrodes, one of the first rewiring electrodes being electrically connected to one of the first conductive pillars through one of the first connection holes; in response to the number of the chips being plural, the first rewiring layer further includes at least one series electrode connecting adjacent two of the chips in series.
Optionally, the first insulating layer and the protection layer are made of the same material.
The beneficial effect of this application is: the preparation method of the semiconductor packaging device includes the steps that a first packaging body is provided, the first packaging body comprises a chip, a first conductive column and a protective layer, the chip is provided with a first main surface and a second main surface which are arranged oppositely, the first main surface is provided with a plurality of chip electrodes, the first conductive column is located at the position of the chip electrodes and is electrically connected with the corresponding chip electrodes, and the protective layer covers the first conductive column; then forming a first plastic packaging layer, wherein the first plastic packaging layer covers the first packaging body from one side of the first main surface, and the second main surface is exposed from the first plastic packaging layer; then removing part of the first plastic packaging layer and part of the protective layer from the first main surface side, so that one end, away from the chip, of the first conductive pillar is exposed from the protective layer and the first plastic packaging layer; the flatness of the surface of one side, which deviates from the chip, of the protective layer is greater than the flatness of the surface of one side, which deviates from the chip, of the first plastic packaging layer. It can be seen that, a side surface of the device is formed by the surface of the protective layer and the surface of the first plastic packaging layer, and the surface of the protective layer is smoother, when other functional layers are subsequently formed, other functional layers are simultaneously combined with the protective layer and the first plastic packaging layer, the binding force between other functional layers and the surface of the device can be improved, the probability of surface layering of other functional layers and the device is reduced, the electric connection between the chip and other functional layers is more stable, and the reliability of the semiconductor packaging device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating one embodiment of a method for fabricating a semiconductor package device according to the present application;
FIG. 2a is a schematic structural diagram illustrating an embodiment of step S11 in FIG. 1;
FIG. 2b is a schematic structural diagram illustrating an embodiment of step S12 in FIG. 1;
FIG. 2c is a schematic structural diagram of another embodiment of step S12 in FIG. 1;
FIG. 2d is a schematic structural diagram illustrating an embodiment of step S13 in FIG. 1;
FIG. 2e is a schematic structural diagram illustrating another embodiment of step S13 in FIG. 1;
FIG. 3 is a flowchart illustrating an embodiment of step S11 in FIG. 1;
FIG. 4a is a schematic structural diagram illustrating an embodiment of step S22 in FIG. 3;
FIG. 4b is a schematic structural diagram illustrating an embodiment of step S23 in FIG. 3;
FIG. 4c is a schematic structural diagram illustrating an embodiment of step S24 in FIG. 3;
FIG. 5 is a flowchart illustrating an embodiment of step S12 in FIG. 1;
FIG. 6 is a schematic structural diagram illustrating an embodiment of step S32 in FIG. 5;
FIG. 7 is a schematic flow chart diagram illustrating another embodiment of a method for fabricating a semiconductor package device according to the present application;
FIG. 8 is a schematic structural diagram illustrating an embodiment of step S41 in FIG. 7;
FIG. 9 is a schematic structural diagram of one embodiment of a semiconductor package device according to the present application;
fig. 10 is a schematic structural diagram of another embodiment of a semiconductor package device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a manufacturing method of a semiconductor package device according to an embodiment of the present invention, the manufacturing method includes the following steps.
Step S11, providing a first package body, where the first package body includes a chip, a first conductive pillar, and a protection layer, the chip has a first main surface and a second main surface that are arranged oppositely, the first main surface has a plurality of chip electrodes, the first conductive pillar is located at a position of the chip electrode and electrically connected to the corresponding chip electrode, and the protection layer covers the first conductive pillar.
Referring to fig. 2a, fig. 2a is a schematic structural diagram corresponding to the embodiment of step S11 in fig. 1, in which the embodiment first provides a first package body 111, the first package body 111 includes a chip 11, a first conductive pillar 12 and a protection layer 13, the chip 11 has a first main surface and a second main surface that are oppositely disposed, the first main surface has a plurality of chip electrodes 110, the first conductive pillar 12 is located at a position of the chip electrode 110 and electrically connected to the corresponding chip electrode 110, and the protection layer 13 covers the first conductive pillar 12. A specific process of providing the first package body 111 will be described below.
Step S12, a first molding compound layer is formed, the first molding compound layer covers the first package body from the first main surface side, and the second main surface is exposed from the first molding compound layer.
Referring to fig. 2b in conjunction with fig. 2a, fig. 2b is a schematic structural diagram corresponding to the embodiment of step S12 in fig. 1, and after providing the first package body 111, a first molding compound layer 112 is formed on the first package body 111, wherein the first molding compound layer 112 covers the first package body 111 from a side of the first main surface of the chip 11, and the second main surface of the chip 11 is exposed from the first molding compound layer 112. A specific process of forming the first molding layer 112 will be described below.
With the improvement of functions and requirements of end products, in a large number of application scenarios, a plurality of chips 11 with different functions need to be packaged together to form a semiconductor package device, please refer to fig. 2c, where fig. 2c is a schematic structural diagram corresponding to another embodiment of step S12 in fig. 1, in which two first packages 111 are schematically illustrated, two chips 11 included therein have different functions, and a first molding compound layer 112 is formed to continuously cover all the first packages 111. In other embodiments, there may be a greater number of first packages 111, and it is understood that the plurality of chips 11 included therein have at least two different functions.
Step S13, removing a part of the first molding compound layer and a part of the protection layer from the first main surface side, so that one end of the first conductive pillar away from the chip is exposed from the protection layer and the first molding compound layer; the flatness of the surface of one side, which deviates from the chip, of the protective layer is greater than the flatness of the surface of one side, which deviates from the chip, of the first plastic packaging layer.
Referring to fig. 2d in conjunction with fig. 2b, referring to fig. 2e in conjunction with fig. 2c, fig. 2d is a schematic structural diagram corresponding to an embodiment of step S13 in fig. 1, and fig. 2e is a schematic structural diagram corresponding to another embodiment of step S13 in fig. 1, after the first molding layer 112 is formed, a portion of the first molding layer 112 and a portion of the protection layer 13 are removed from the first main surface side of the chip 11, so that one end of the first conductive pillar 12 away from the chip 11 is exposed from the protection layer 13 and the first molding layer 112. The flatness of the surface of the protection layer 13 facing away from the chip 11 is greater than the flatness of the surface of the first plastic package layer 112 facing away from the chip 11. Specifically, the first conductive pillars 12 may be exposed by a grinding or etching process, so as to further perform fan-out packaging on the chip 11.
The surface of one side of the semiconductor packaging device prepared by the embodiment is formed by the surface of the protective layer 13 and the surface of the first plastic packaging layer 112, and the surface of the protective layer 13 is smoother, so that when other functional layers are formed subsequently, other functional layers are simultaneously combined with the protective layer 13 and the first plastic packaging layer 112, the binding force between other functional layers and the surface of the device can be improved, the probability of layering of other functional layers and the surface of the device is reduced, the electric connection between the chip 11 and other functional layers is more stable, and the reliability of the semiconductor packaging device is improved.
In one embodiment, referring to fig. 3, fig. 3 is a flowchart illustrating an embodiment of step S11 in fig. 1, and the first package may be provided through the following steps.
Step S21, providing a wafer, where the wafer includes a plurality of chips arranged in an array, and a scribe line is formed between adjacent chips, and a sacrificial layer covers the scribe line.
Referring to fig. 4a, fig. 4a is a schematic structural view corresponding to the step S22 in fig. 3, first, a wafer 100 is provided, the wafer 100 is a wafer having completed a chip manufacturing process and includes a plurality of chips 11 arranged in an array, two chips 11 are schematically illustrated in the figure, a plurality of chip electrodes 110 are formed on a first main surface of each chip 11, a scribe line S is formed between adjacent chips 11, and a sacrificial layer (not shown) covers the scribe line S, wherein the scribe line S and the sacrificial layer are formed simultaneously in the chip manufacturing process.
In step S22, a plurality of first conductive pillars are formed on the side of the wafer having the chip electrodes.
Further, a plurality of first conductive pillars 12 are formed on one side of the wafer 100 having the chip electrodes 110, and the first conductive pillars 12 correspond to the chip electrodes 110 one to one. The first conductive pillar 12 is, for example, a copper pillar grown by an electroplating process.
In step S23, a passivation layer is formed on the side of the wafer having the chip electrodes, and the passivation layer continuously covers all the first conductive pillars.
Referring to fig. 4a and fig. 4b in combination, fig. 4b is a schematic structural view corresponding to the embodiment of step S23 in fig. 3, after the first conductive pillars 12 are formed, a protective layer 13 is further formed on one side of the wafer 100 having the chip electrodes 110, and the protective layer 13 continuously covers all the first conductive pillars 12. The protective layer 13 is made of an insulating material, such as polyimide, photoresist, or the like.
In step S24, the passivation layer and the sacrificial layer at the position corresponding to the scribe line are removed to expose the scribe line.
Referring to fig. 4c with reference to fig. 4b, fig. 4c is a schematic structural diagram corresponding to the step S24 in fig. 3, after the protective layer 13 is formed, the protective layer 13 at the position corresponding to the scribe line S and the sacrificial layer in the scribe line S are further removed to expose the scribe line S.
Specifically, the protective layer 13 at the position corresponding to the scribe line S may be removed by a laser grooving process to form a first through trench exposing the sacrificial layer; and then, removing the sacrificial layer exposed by the first through groove by utilizing a laser grooving process so as to expose the cutting channel S. The longitudinal section of the first through groove is in an inverted trapezoid shape, and the size of one end, close to the cutting channel S, of the first through groove is larger than or equal to the size of the cutting channel S.
Step S25, the wafer is diced along the scribe lines to obtain a plurality of first packages.
Referring to fig. 2a with reference to fig. 4c, after the scribe lines S are exposed, the wafer 100 may be diced along the scribe lines S by using a physical dicing saw (Blade saw) method to obtain a plurality of first packages 111 shown in fig. 2 a.
The embodiment can fully expose the cutting path S, improve the yield of the cutting process, and improve the reliability of the first package 111.
In one embodiment, referring to fig. 5, fig. 5 is a flowchart illustrating an embodiment of step S12 in fig. 1, the first molding layer may be formed through the following steps, and the embodiment takes the structure shown in fig. 2c as an example for description.
Step S31, attaching the first package to the carrier with the second main surface facing the carrier.
Referring to fig. 6, fig. 6 is a schematic structural view corresponding to the step S32 in fig. 5, after the first package body 111 is obtained, the first package body 111 is attached to the carrier 200, wherein the second main surface of the chip 11 faces the carrier 200. Specifically, the first package body 111 can be attached to the carrier 200 by using a removable adhesive such as a double-sided adhesive. When the number of the first packages 111 is multiple, the multiple first packages 111 are arranged on the carrier 200 at intervals, and fig. 6 schematically illustrates two first packages 111.
Step S32, a first molding compound layer is formed on the surface of the carrier on which the first package is attached, and the first molding compound layer covers the first package.
Further, a first molding compound layer 112 is formed on the surface of the carrier 200 where the first package body 111 is attached, and the first molding compound layer 112 covers the first package body 111. When the number of the first package bodies 111 is plural, the first molding compound layer 112 continuously covers all the first package bodies 111, as shown in fig. 6. The specific process of forming the first molding layer 112 is a common molding process in the prior art, and Epoxy Molding Compound (EMC) is used for molding.
Step S33, removing the carrier board.
Referring to fig. 2c with reference to fig. 6, after the first molding compound layer 112 is formed, the carrier 200 is removed, so as to obtain the structure shown in fig. 2c, wherein the second main surface of the chip 11 is exposed from the first molding compound layer 112.
In the embodiment, the first package body 111 including the protection layer 13 is subjected to plastic package, so that the surface of the device is formed by the protection layer 13 and the surface of the first plastic package layer 112, the bonding force between other functional layers and the surface of the device can be improved, the probability of layering between other functional layers and the surface of the device is reduced, the electrical connection between the chip 11 and other functional layers is more stable, and the reliability of the semiconductor package device is improved.
In one embodiment, referring to fig. 7, fig. 7 is a schematic flow chart illustrating a method for manufacturing a semiconductor package device according to another embodiment of the present application, where the method includes steps S11-S13, and further includes the following steps after step S13.
In step S41, a first insulating layer is formed on one side of the first plastic package layer close to the first conductive pillars and patterned to form a plurality of first through holes exposing the first conductive pillars.
Referring to fig. 8 with reference to fig. 2e, fig. 8 is a schematic structural diagram corresponding to the embodiment of step S41 in fig. 7, after one end of the first conductive pillar 12 away from the chip 11 is exposed from the protective layer 13 and the first molding compound layer 112, taking the structure shown in fig. 2e as an example, on the basis of the structure shown in fig. 2e, a first insulating layer 113 is further formed on one side of the first molding compound layer 112 close to the first conductive pillar 12 and is patterned to form a plurality of first through holes (not shown) exposing the first conductive pillar 12. Specifically, the first insulating layer 113 having a plurality of first vias may be formed by performing a full-area deposition and then performing a selective etching.
The first insulating layer 113 may be made of an inorganic insulating material, such as silicon oxide or silicon nitride, or an organic insulating material, such as polyurethane, photoresist, or the like. Preferably, the first insulating layer 113 and the protection layer 13 are made of the same material, for example, both made of polyamine, so that the bonding interface between the first insulating layer 113 and the device shown in fig. 2e is mostly the bonding interface between the first insulating layer 113 and the protection layer 13 made of the same material, and only a small part of the bonding interface between the first insulating layer 113 and the first molding compound layer 112 made of different materials is stronger in the interface bonding force than the case of the prior art where all the first insulating layer 113 and the first molding compound layer 112 are made of different materials.
In step S42, a first metal layer is formed on the side of the first insulating layer away from the first molding layer and patterned to form a first redistribution layer.
Referring to fig. 9 in conjunction with fig. 8, fig. 9 is a schematic structural diagram of an embodiment of a semiconductor package device according to the present application, after patterning the first insulating layer 113, a first metal layer is further formed on a side of the first insulating layer 113 away from the first molding compound layer 112 and patterned to form a first redistribution layer 114. Specifically, a first metal layer may be formed by full-surface deposition, and then the first redistribution layer 114 may be formed by selective etching.
In the device shown in fig. 9, the number of the first packages 111 is plural, and the first redistribution layer 114 includes a plurality of first redistribution electrodes 1141 and at least one series electrode 1142. One first redistribution electrode 1141 is electrically connected to one first conductive pillar 12 through one first connection hole, and the series electrode 1142 connects two adjacent chips 11 in series, that is, the series electrode 1142 is electrically connected to the first conductive pillars 12 belonging to two adjacent chips 11 at the same time.
It is understood that, when the number of the first packages 111 is one, the first redistribution layer 114 includes only the plurality of first redistribution electrodes 1141.
The first redistribution electrode 1141 is electrically connected to the chip electrode 110 of the chip 11 through the first conductive pillar 12, so as to implement fan-out packaging of the chip 11.
In the semiconductor package device prepared in the embodiment, the first insulating layer 113 is mainly combined with the protective layer 13 with a smoother surface, so that the bonding force between the two layers can be improved, the probability of layering between the two layers is reduced, the electrical connection between the chip 11 and the first redistribution layer 114 is more stable, and the reliability of the semiconductor package device is improved.
Based on the same inventive concept, the present application further provides a semiconductor package device, please continue to refer to fig. 9, which includes a chip 11, a first conductive pillar 12, a protection layer 13, and a first molding compound 112. The chip 11 has a first main surface and a second main surface that are disposed opposite to each other, the first main surface has a plurality of chip electrodes 110, the first conductive pillars 12 are located at the positions of the chip electrodes 110 and electrically connected to the corresponding chip electrodes 110, the passivation layer 13 is located on the first main surface, and the passivation layer 13 covers only the side surfaces of the first conductive pillars 12. The first plastic packaging layer 112 covers only the side face of the chip 11 and the side face of the protection layer 13, and the flatness of the surface of the protection layer 13 on the side away from the chip 11 is greater than that of the surface of the first plastic packaging layer 112 on the side away from the chip 11.
Further, with reference to fig. 9, the semiconductor package device further includes a first insulating layer 113 and a first redistribution layer 114. The first insulating layer 113 is located on one side of the first plastic packaging layer 112 close to the first conductive pillars 12, and a plurality of first through holes exposing the first conductive pillars 12 are formed on the first insulating layer 113. The first redistribution layer 114 is located on a side of the first insulation layer 113 away from the first molding compound layer 112. In response to the number of the chips 11 being one, the first redistribution layer 114 includes a plurality of first redistribution electrodes 1141, one first redistribution electrode 1141 being electrically connected to one first conductive pillar 12 through one first connection hole; in response to the number of the chips 11 being plural, the first redistribution layer 114 further includes at least one series electrode 1142, and the series electrode 1142 connects two adjacent chips 11 in series.
Preferably, the materials of the first insulating layer 113 and the protection layer 13 are the same, so that the bonding interface between the first insulating layer 113 and the device shown in fig. 2e is mostly the bonding interface between the first insulating layer 113 and the protection layer 13 of the same material, and only a small part of the bonding interface between the first insulating layer 113 and the first molding compound layer 112 of different materials is stronger in interface bonding force.
The embodiment can improve the reliability of the semiconductor package device.
In some embodiments, the above steps S41-S42 may be further repeated on the basis of the device shown in fig. 9, as shown in fig. 10, fig. 10 is a schematic structural diagram of another embodiment of the semiconductor package device of the present application, that is, a combination of a plurality of insulating layers and redistribution layers is formed, and the position of the first redistribution electrode 1141 may be set as required. Second conductive posts 115 and solder balls 116 are then formed on the outermost surface for electrical connection with other devices.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims (10)

1. A method for manufacturing a semiconductor package device, comprising:
providing a first packaging body, wherein the first packaging body comprises a chip, a first conductive column and a protective layer, the chip is provided with a first main surface and a second main surface which are arranged oppositely, the first main surface is provided with a plurality of chip electrodes, the first conductive column is positioned at the position of the chip electrodes and is electrically connected with the corresponding chip electrodes, and the protective layer covers the first conductive column;
forming a first plastic packaging layer, wherein the first plastic packaging layer covers the first packaging body from the side of the first main surface, and the second main surface is exposed out of the first plastic packaging layer;
removing a part of the first plastic packaging layer and a part of the protective layer from the first main surface side, so that one end, away from the chip, of the first conductive pillar is exposed from the protective layer and the first plastic packaging layer; the flatness of the surface of one side, which deviates from the chip, of the protective layer is greater than the flatness of the surface of one side, which deviates from the chip, of the first plastic packaging layer.
2. The method of manufacturing a semiconductor package device according to claim 1, wherein the step of providing the first package body comprises:
providing a wafer, wherein the wafer comprises a plurality of chips arranged in an array, cutting channels are arranged between the adjacent chips, and sacrificial layers are covered in the cutting channels;
forming a plurality of first conductive columns on one side of the wafer, which is provided with the chip electrodes;
forming the protective layer on one side of the wafer, which is provided with the chip electrode, wherein the protective layer continuously covers all the first conductive columns;
removing the protective layer and the sacrificial layer at the position corresponding to the cutting channel to expose the cutting channel;
and cutting the wafer along the cutting channels to obtain a plurality of first packaging bodies.
3. The method of manufacturing a semiconductor package device according to claim 2, wherein the step of removing the protective layer and the sacrificial layer at the position corresponding to the scribe line comprises:
removing the protective layer at the position corresponding to the cutting channel by using a laser grooving process to form a first through groove exposing the sacrificial layer;
removing the sacrificial layer exposed by the first through groove by using a laser grooving process to expose the cutting channel; the size of one end, close to the cutting channel, of the first through groove is larger than or equal to the size of the cutting channel.
4. The method of manufacturing a semiconductor package device according to claim 1, wherein the step of forming the first molding layer comprises:
attaching the first package body to a carrier plate, wherein the second main surface faces the carrier plate;
forming the first plastic package layer on the surface of one side of the carrier plate, to which the first package body is attached, wherein the first plastic package layer covers the first package body;
and removing the carrier plate.
5. The method for manufacturing a semiconductor package device according to claim 4, wherein the number of the first package bodies is plural, the first molding compound continuously covers all the first package bodies, and the plurality of chips included in the plurality of first package bodies have at least two different functions.
6. The method of manufacturing a semiconductor package device according to claim 1, further comprising, after the step of removing a portion of the first molding layer and a portion of the protective layer from the first main surface side:
forming a first insulating layer on one side, close to the first conductive pillars, of the first plastic packaging layer and patterning the first insulating layer to form a plurality of first through holes exposing the first conductive pillars;
forming a first metal layer on one side, away from the first plastic packaging layer, of the first insulating layer and patterning the first metal layer to form a first rewiring layer; wherein in response to the number of the first packages being one, the first rewiring layer includes a plurality of first rewiring electrodes, one of the first rewiring electrodes being electrically connected to one of the first conductive pillars through one of the first connection holes; in response to the number of the first packages being a plurality, the first redistribution layer further includes at least one series electrode connecting two adjacent chips in series.
7. The method of claim 6, wherein the first insulating layer and the protective layer are made of the same material.
8. A semiconductor package device prepared by the method for manufacturing a semiconductor package device according to any one of claims 1 to 7, comprising:
a chip having first and second oppositely disposed major surfaces, the first major surface having a plurality of chip electrodes;
the first conductive columns are positioned at the positions of the chip electrodes and are electrically connected with the corresponding chip electrodes;
a protective layer on the first main surface and covering only the side surfaces of the first conductive posts;
the first plastic packaging layer only covers the side face of the chip and the side face of the protective layer; the flatness of the surface of one side, which deviates from the chip, of the protective layer is greater than the flatness of the surface of one side, which deviates from the chip, of the first plastic packaging layer.
9. The semiconductor package device of claim 8, further comprising:
the first plastic packaging layer is positioned on one side, close to the first conductive column, of the first insulating layer, and a plurality of first connecting holes exposing the first conductive column are formed in the first insulating layer;
the first rewiring layer is positioned on one side, away from the first plastic packaging layer, of the first insulating layer; in response to the number of the chips being one, the first rewiring layer includes a plurality of first rewiring electrodes, one of the first rewiring electrodes being electrically connected to one of the first conductive pillars through one of the first connection holes; in response to the number of the chips being plural, the first rewiring layer further includes at least one series electrode connecting adjacent two of the chips in series.
10. The semiconductor package device of claim 9, wherein the first insulating layer and the protective layer are the same material.
CN202210056460.0A 2022-01-18 2022-01-18 Semiconductor packaging device and preparation method thereof Pending CN114597134A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210056460.0A CN114597134A (en) 2022-01-18 2022-01-18 Semiconductor packaging device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210056460.0A CN114597134A (en) 2022-01-18 2022-01-18 Semiconductor packaging device and preparation method thereof

Publications (1)

Publication Number Publication Date
CN114597134A true CN114597134A (en) 2022-06-07

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Country Link
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