CN114597126A - Slicing method for processing wafer cutting abnormity - Google Patents
Slicing method for processing wafer cutting abnormity Download PDFInfo
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- 238000005520 cutting process Methods 0.000 title claims abstract description 410
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- 230000002159 abnormal effect Effects 0.000 claims abstract description 28
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- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 11
- 238000009432 framing Methods 0.000 claims description 9
- 239000002313 adhesive film Substances 0.000 claims description 3
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Abstract
The invention discloses a slicing and cutting method for processing abnormal cutting of a wafer in the field of semiconductor manufacturing, which comprises the following steps: the wafer is framed, and the cutting knife carries out cutting operation according to the sequence of firstly cutting the long edge cutting channels of the ICs on the wafer and then cutting the short edge cutting channels of the ICs; when the cutting machine has vacuum abnormity or clamping jaw abnormity, and the long and short side cutting channels of the IC are dislocated and deviated, the deviation abnormity of the long and short side cutting channels of the IC caused by the cutting abnormity is processed by a cutting mode combining slicing and reverse frame combining technologies, so that the IC is smoothly separated from the wafer, and the loss is reduced. The invention is suitable for processing various wafer cutting abnormalities and realizing the separation of the IC from the wafer.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, and particularly relates to a slicing and cutting method for processing abnormal wafer cutting.
Background
In the prior art, a cutting machine firstly fixes a framed wafer in a chuck table (working disc) vacuum adsorption and Clamping claw (Clamping Jaw) grabbing mode; the vacuum adsorption mode is as follows: carrying and placing the wafer after being closed to the central position of a working disc, and starting vacuum adsorption on the working disc; the Clamping Jaw gripping mode is as follows: the wafer after the frame is closed is carried and is placed to the central position of the working disc, the clamping jaw grabs four areas of the iron ring, namely the upper area, the lower area, the left area and the right area, and presses down, and the horizontal height of the iron ring is smaller than the height of the working disc by more than 1mm (the cutter is prevented from being cut to the iron ring to break the cutter in the cutting process).
Then, cutting by using a double-knife cutting mode according to the size of the IC in the uncut wafer, and performing unified processing on the long-edge cutting channels of each row of ICs and then performing unified processing on the short-edge cutting channels of each row of ICs; the double-knife cutting mode is as follows: the double-cutter synchronous cutting is carried out, a certain distance is reserved between the Z1 cutter shaft and the Z2 cutter shaft, a groove is firstly formed in the Z1 cutter shaft (the cutting depth is generally 1/3-1/5 wafer thickness), the Z2 cutter shaft is separated (the cutting depth is generally wafer thickness plus lower cutting glue film 30-50 um), the long edge cutting of the whole wafer IC is firstly completed, the working disc rotates 90 degrees, and the short edge cutting of the whole wafer IC is then completed;
the whole wafer is completely fixed on the working disc in the cutting process, and the IC long and short side cutting channels of the cut and uncut parts of the wafer have no shift (play) abnormity in the cutting process, so that the cutting machine can be ensured to normally execute full-automatic operation.
If the abnormity occurs in the cutting process and the vacuum abnormity of the machine table or the abnormity of the clamping jaw is not involved, the product in the machine table still keeps a fixed state before full-automatic operation, the wafer is cut and the IC cutting channels with the long and short edges are not cut to have play abnormity, and after the abnormity processing is finished, the semi-automatic cutting processing can be carried out on the part of the wafer which is not cut;
but has the disadvantages that: if the abnormity occurs in the cutting process and relates to the vacuum abnormity of a machine table or the abnormity of a clamping jaw, a product in the machine table is required to be unloaded, after the abnormity is processed, the product is reloaded, the blue film of the cut part of the wafer has expansion phenomenon, so that the movement abnormity exists between the IC long and short side cutting channels of the cut part and the IC short side cutting channels of the uncut part of the wafer, and the uncut part of the wafer can not be processed by semi-automatic cutting, therefore, the abnormity causes the great loss of the wafer, the resource waste and the production cost is increased invisibly.
Disclosure of Invention
The invention aims to provide a slicing and cutting method for processing abnormal cutting of a wafer, which is suitable for processing various abnormal cutting conditions of the wafer, realizing separation of an IC from the wafer and smoothly finishing cutting operation, is suitable for 8-inch and 12-inch wafers and various cutting machines and reduces loss.
The purpose of the invention is realized as follows: a slicing method for processing wafer cutting abnormity comprises the following steps:
(1) the method comprises the following steps of (1) combining a wafer to fix the wafer on an outer frame through a blue film, placing the combined wafer on a vacuum working disc in a cutting machine, fixing the outer frame through a plurality of clamping jaws distributed at intervals along the circumferential direction, and carrying out cutting operation by a cutting knife according to the sequence of cutting long-edge cutting channels of ICs on the wafer and then cutting short-edge cutting channels of the ICs;
(2) when the cutting of the long-edge cutting channels of the ICs on the wafer is completed, the short-edge cutting channels of the ICs are not cut, and the cutting machine has vacuum abnormity or clamping jaw abnormity, the cutting machine carries out the following operations when the cut long-edge cutting channels of the ICs are dislocated and deviated:
s11, detecting the lateral offset of the long-edge cutting channel of the IC through a CCD focusing lens;
s12, calculating the minimum value of n according to a formula [ (d-t/n) -m ]/2 is more than or equal to 5um, wherein d is the width of the cutting channel, t is the lateral offset, n is the number of equally spaced chips, and m is the width of the tool mark of the front cutting knife, so as to obtain the number of equally spaced chips on the wafer part which is cut by the cutting channel with the long edge of each IC;
s13, placing a piece of Taiweike paper inside a microscope detection platform jig, then placing the outer frame on the microscope detection platform jig with the front side of the wafer facing downwards, fixing the outer frame by using a positioning PIN and a buckle, jacking up a whole row of ICs at the boundary of each IC long-edge cutting channel cut by the wafer and each IC long-edge cutting channel not cut by using a thimble jig from the back side of the blue film to separate the ICs from the blue film, enabling a whole row of ICs at the boundary to fall on the Taiweike paper, enabling blue films to be left at the boundary of each IC long-edge cutting channel cut by the wafer and each IC long-edge cutting channel not cut, taking out a whole row of ICs at the boundary, and then re-framing through the blue films and the outer frame to perform semi-automatic cutting;
s14, cutting the blue film and the arc-shaped peripheral blue film of the part of the wafer which is not subjected to the cutting of the IC long-edge cutting channel by using a blade along the hollow blue film in the S13, separating the part of the wafer which is not subjected to the cutting of the IC long-edge cutting channel from an iron frame, taking out the part of the wafer which is not subjected to the cutting of the IC long-edge cutting channel, reversely combining the frames, and then carrying out semi-automatic cutting;
s15, according to the number n of equally spaced slices obtained from S12, equally spaced slices are performed on the wafer part which is cut through each IC long edge cutting channel, n-1 whole rows of ICs which enable the wafer part which is cut through each IC long edge cutting channel to be equally spaced into n slices are found, the whole rows of ICs are transversely arranged, the n-1 whole rows of ICs are respectively positioned at corresponding junctions of the n equally spaced slices, marks are made on the blue films on the outer edges of the (n-1) whole rows of ICs on the outer frame (the back surfaces of the blue films are all provided with tool marks which cannot be distinguished), a piece of Taivik paper is placed inside a microscope detection platform tool, then the wafer part which is cut through each IC long edge cutting channel is placed on the microscope detection platform tool with the front surface facing downwards, the marked (n-1) whole rows of ICs are jacked up by a thimble tool from the back surface to enable the marked ICs to be separated from the blue films and fall on the Taivik paper, taking out (n-1) whole-line ICs, re-framing through (n-1) groups of blue films and outer frames, and then respectively carrying out semi-automatic cutting;
and S16, cutting the outer edges of the blue film and the residual blue film on the outer frame along the whole row of IC positions at the intersection of the (n-1) equidistant sub-frames by using a blade, so that the n equidistant sub-frames are separated from the outer frame, and semi-automatically cutting the n equidistant sub-frames after reversely closing the frames.
According to the invention, the cutting mode of combining the slicing and reverse frame combination technology is used for processing the lateral deviation abnormity of the IC long and short side cutting channels caused by the abnormal cutting, so that the separation of the IC from the wafer is realized, and the loss is reduced. The single-side reservation quantity required by the normal cutting path is more than or equal to 10 um; the abnormal cutting path firstly considers the reduction of the product loss quantity, and secondly considers the influence of the reserved quantity after cutting, so that the single-side reserved quantity is required to be more than or equal to 5 um; and (3) normally cutting a street: the unilateral allowance = [ (cutting path width-lateral offset) -front cutting knife mark width ]/2 is more than or equal to 10um (the lateral offset is 0 under the normal cutting condition); after the lateral deviation, the cutting path is in an arch shape or an S shape, and for the arch shape and the S shape cutting path: the unilateral reservation quantity = [ (d-t/n) -m ]/2 is more than or equal to 5um, wherein d is the cutting path width, t is the lateral offset, n is the equal-interval slicing quantity, m is the tool mark width of the front cutting knife, and the tool mark width of the front cutting knife is larger than that of the rear cutting knife; the tool mark width of preceding cutting knife receives the width influence of test pattern on the product cutting way, and there is certain restriction in the tool mark width of cutting knife before the change, but the tool mark width of cutting knife before the condition allows down to reduce equidistance burst quantity. Compared with the prior art, the invention has the beneficial effects that: the long-edge cutting channels and the short-edge cutting channels of the ICs on the blue film have the characteristic of consistent overall trend during twisting, the laterally offset wafer part is efficiently sliced, the laterally offset wafer part is divided into a plurality of slices which do not influence the cutting operation through the least-frequency cutting, and the slices are semi-automatically cut independently to smoothly complete the cutting operation; the wafer loss caused by the abnormal cutting channels of the long and short edges of the IC is reduced, the company cost is saved, and the customer complaints are avoided; the slicing cutting mode is combined with the semi-automatic cutting mode, and the cutting abnormity processing mode is unlimited.
As a further improvement of the present invention, in the step (2), when all the long-side streets on the wafer are completely cut, none of the short-side streets on the wafer is cut, and the cutting machine has a vacuum anomaly or a clamping jaw anomaly, causing the displacement of all the long-side streets on the wafer, the following operations are performed:
s21, detecting the lateral offset of each IC long-edge cutting channel through a CCD focusing lens, calculating the minimum value of n according to a formula [ (d-t/n) -m ]/2 is more than or equal to 5um, and obtaining the quantity of equally-spaced slicing of the whole wafer which is completely cut through each IC long-edge cutting channel;
s22, according to the obtained equal-spacing slicing number n of S21, performing equal-spacing slicing on the whole wafer, finding (n-1) whole-row ICs which enable the whole wafer to be equally divided into n pieces, transversely arranging the whole-row ICs, marking blue films on the outer edges of the (n-1) whole-row ICs on an outer frame, placing Taivke paper inside a microscope detection platform jig, then enabling the front side of the whole wafer with cut long-edge cutting channels of the ICs to face downwards to enable the outer frame to be placed on the microscope detection platform jig, jacking the marked (n-1) whole-row ICs from the back side by using an ejector pin jig to enable the marked (n-1) whole-row ICs to be separated from the blue films and fall on the Taivke paper, taking out the (n-1) whole-row ICs, respectively re-framing through the (n-1) group blue films and the outer frame, and then respectively performing semi-automatic cutting;
and S23, cutting the outer edges of the blue film and the residual blue film on the outer frame along the whole row of IC positions at the intersection of the (n-1) equidistant sub-frames by using a blade, so that the n equidistant sub-frames are separated from the outer frame, and semi-automatically cutting the n equidistant sub-frames after reversely closing the frames.
The abnormal wafer cutting causes the situation that the wafer is not completely cut to have 3, and this technical scheme corresponds 2 nd circumstances, and after the whole wafer that will cut the lateral deviation of road, to single burst semi-automatic cutting again.
As a further improvement of the present invention, in the step (2), when the cutting of all the long-side streets on the wafer is completed, the cutting of part of each short-side street on the wafer is completed, and the cutting machine has vacuum anomaly or clamping jaw anomaly, causing the wafer part which is not cut through each short-side street to have dislocation offset, the following operations are performed:
s31, cutting the wafer part with each IC short edge cutting channel completely, picking each IC with a crystal picking machine, and making the blue film of the area where the wafer part with each IC short edge cutting channel is located;
s32, detecting the lateral offset of the long-edge cutting channels of the IC of the wafer part of each IC short-edge cutting channel which is not cut through a CCD focusing lens, and calculating the minimum value of n according to a formula [ (d-t/n) -m ]/2 is more than or equal to 5um to obtain the quantity of equally-spaced slicing of the wafer part of each IC short-edge cutting channel which is not cut;
s33, according to the equal-spacing slicing number n obtained from S32, the wafer part which is not cut by each IC short edge cutting channel is sliced at equal spacing, so as to find (n-1) whole rows of ICs which are equally divided by the wafer part which is not cut by each IC short edge cutting channel, the whole rows of ICs are transversely arranged, marking blue films on the outer edges of (n-1) whole rows of ICs on the outer frame, placing a piece of taverk paper inside a microscope detection platform jig, then, the front side of the wafer part which is not cut through the short-edge cutting channels of the ICs is downward, so that the outer frame is placed on a microscope detection platform jig, a thimble jig is used for jacking the marked (n-1) whole-row ICs from the back side to enable the marked (n-1) whole-row ICs to be separated from the blue film and fall on the Taivik paper, the (n-1) whole-row ICs are taken out and then respectively subjected to semi-automatic cutting after being re-framed through the (n-1) group blue film and the outer frame;
and S34, cutting the outer edges of the blue film and the residual blue film on the outer frame along the whole row of IC positions at the intersection of the (n-1) equidistant sub-frames by using a blade, so that the n equidistant sub-frames are separated from the outer frame, and semi-automatically cutting the n equidistant sub-frames after reversely closing the frames.
The technical scheme corresponds to the situation of the 3 rd condition that the wafer is not completely cut due to abnormal wafer cutting, the part of the wafer which is cut by each IC short-edge cutting channel is cut, and only after the part of the wafer which is not cut by each IC short-edge cutting channel is sliced, the single slice is semi-automatically cut.
As a further improvement of the invention, in the step (1), 4 iron rings are uniformly distributed along the circumferential direction, two cutters are used for synchronously cutting when the cutters cut, the front cutter and the rear cutter are arranged at intervals, the front cutter slots the wafer, the depth of the front cutter for cutting the wafer is 1/3-1/5 of the thickness of the wafer, the rear cutter separates the wafer, the depth of the rear cutter for cutting the wafer is the depth of cutting the wafer to 30-50 um of a blue film, the front cutter and the rear cutter firstly cut the long-edge cutting channels of each IC of the wafer on the working disc, and after the working disc rotates 90 degrees, the front cutter and the rear cutter cut the short-edge cutting channels of each IC of the wafer on the working disc. The IC long-edge cutting channel and the IC short-edge cutting channel are cut completely: the rear cutting knife finishes the cutting operation on the corresponding cutting path.
As a further improvement of the present invention, in the step (2), when detecting the lateral offset of the long-side scribe line of the IC: after the abnormal wafer is reloaded, the CCD focusing lens of the cutting machine is moved to the leftmost side of the wafer lateral offset area, so that the horizontal correction electronic wire is aligned with the end part of the leftmost IC cutting channel, the CCD focusing lens of the cutting machine is moved to the rightmost side of the wafer lateral offset area, the horizontal correction electronic wire is also aligned with the end part of the rightmost IC cutting channel, the CCD focusing lens moves from left to right in a stepping jumping mode, the highest point and the lowest point of the whole cutting channel of the wafer lateral offset area are confirmed, and the longitudinal distance between the two points is the lateral offset.
As a further improvement of the invention, the reverse framing step is as follows:
a) firstly, placing a wafer part needing reverse frame combination on a frame combination working disc in a way that the front side of the wafer part is upward, and carrying out frame combination to ensure that the front side of the wafer part is attached with a circular blue film and the circular blue film is fixed on the upper side of an outer frame;
b) turning over the part of the wafer with the front surface stuck with the blue film and placing the part of the wafer on a frame-combining working disc;
c) manually tearing off the residual blue film on the back of the wafer part;
d) placing the back of the wafer part upwards on a frame-closing working disc for film pasting, so that the back of the wafer part is pasted with a blue film;
e) placing the wafer part with the front side and the back side both stuck with the blue film on a frame-combined working disc with the front side facing upwards;
f) and manually tearing off the adhesive film on the front surface of the wafer part to finish reverse frame combination treatment.
As a further improvement of the invention, the semi-automatic cutting steps are as follows:
step one, calibrating that a rotating main shaft of a cutting knife is parallel to a long-edge cutting channel of an IC
Step two, aligning the lower cutter position of the calibration cutter with the center of the IC short edge cutting path;
setting a cutting starting position and setting the number of cutting knives;
and step four, performing semi-automatic cutting and machining operation. When the sliced wafer or the whole IC at the boundary is semi-automatically cut, a horizontal correction electronic line is found through a CCD focusing lens, then the cutting direction of a cutting knife is controlled to be vertical to the horizontal correction electronic line, the wafer is cut along a cutting path of the short edge of the first IC from the initial position, and the uncut wafer is divided into a plurality of ICs; when the wafer part which is not subjected to the cutting of the long-side cutting streets of the IC in the step S14 is cut, the horizontal correction electronic lines are found through the CCD focus lens, then the cutting direction of the cutting knife is controlled to be parallel to the horizontal correction electronic lines, the wafer is cut along the long-side cutting streets of the first IC from the initial position, and after the cutting of the long-side cutting streets of the IC is completed, the short-side cutting streets of the IC are cut, and the uncut wafer is divided into a plurality of ICs.
As a further improvement of the invention, the number of the IC long-edge cutting channels on the wafer is 100-400, and the number of the IC short-edge cutting channels is 10-40.
Drawings
FIG. 1 is a front view of a wafer mounted on a work plate during dicing.
Fig. 2 is a top view of fig. 1.
FIG. 3 is a top view of the wafer cutting the long-side scribe lines of the IC.
FIG. 4 is a top view of the wafer cutting the long-side scribe lines of the IC.
FIG. 5 is a diagram of a wafer state under the abnormal cutting condition of type 1.
FIG. 6 is a diagram of a wafer state under the abnormal situation of the 2 nd dicing.
FIG. 7 is a diagram illustrating a state of a wafer during abnormal dicing condition of type 3.
FIG. 8 is a diagram illustrating a state where a scribe line is S-shaped due to an abnormal dicing of a wafer.
FIG. 9 is a diagram illustrating a situation where the scribe lines are arched due to abnormal dicing of the wafer.
FIG. 10 is a diagram showing the cutting marks of the front and rear cutters in a normal cutting line state.
FIG. 11 is a diagram illustrating the CCD focusing lens moving to the leftmost side of the wafer lateral shift area.
Fig. 12 is a diagram illustrating the state when the CCD focus lens is moved to the rightmost side of the wafer lateral shift area.
FIG. 13 is a diagram of the cutting marks of the front cutter of the normal cutting line.
FIG. 14 is a cut mark view of the front cutter of the arcuate street.
FIG. 15 is a view of the cutting marks of the front cutter of the S-shaped cutting path.
Fig. 16 is a cross-sectional view of a wafer placed on a microscope inspection stage fixture.
Fig. 17 is a top view of the microscope testing platform fixture.
Fig. 18 is a top view of a framed work tray.
The device comprises a wafer 1, a silicon layer 1a, a circuit layer 1b, a blue film 2, an outer frame 3, a vacuum working disc 4, a clamping jaw 5, a long-edge cutting channel 6 IC, a short-edge cutting channel 7 IC, a CCD focusing lens 8, a cutting channel 9, a t lateral offset, a tool mark of a front cutting knife 10, a tool mark of a rear cutting knife 10a, a microscope detection platform jig 11, a front cutting knife 12, a rear cutting knife 13, an IC cutting channel end part on the leftmost side 14, an IC cutting channel end part on the rightmost side 15, a horizontal correction electronic wire 16, a highest point 17, a lowest point 18, a frame-closing working disc 19, an IC functional area 20 and an IC 21.
Detailed Description
As shown in fig. 1-18, a dicing method for handling cutting abnormality of a wafer 1 includes the following steps:
(1) the method comprises the following steps of (1) framing a wafer 1, enabling the wafer 1 to be fixed on an outer frame 3 through a blue film 2, enabling the wafer 1 to be composed of a silicon layer 1a below and a circuit layer 1b above, placing the framed wafer 1 on a vacuum working disc 4 in a cutting machine, fixing the outer frame 3 through a plurality of clamping jaws 5 distributed at intervals along the circumferential direction, and carrying out cutting operation by a cutting knife according to the sequence of firstly cutting long-edge cutting channels 6 of ICs on the wafer 1 and then cutting short-edge cutting channels 7 of the ICs; the hoop is provided with 4 along circumference equipartition, adopt the double knives to carry out synchronous cutting during the cutting knife cutting, preceding cutting knife 12 sets up with back cutting knife 13 interval, preceding cutting knife 12 slots wafer 1, the degree of depth of preceding cutting knife 12 cutting wafer 1 is 1/3~1/5 of 1 thickness of wafer, back cutting knife 13 separates wafer 1, the degree of depth of back cutting knife 13 cutting is for cutting open wafer 1 and cut to the degree of depth of blue membrane 230~50um, each IC long edge cutting way 6 of wafer 1 on preceding cutting knife and the earlier cutting working disc of back cutting knife, the rotatory 90 degrees backs of working disc, each IC short edge cutting way 7 of wafer 1 on preceding cutting knife and the back cutting knife cutting working disc again. The IC long edge cutting path 6 and the IC short edge cutting path 7 are cut completely: the rear cutter completes cutting operation on the corresponding cutting path 9; as shown in fig. 10, the tool mark 10 of the front cutter and the tool mark 10a of the rear cutter do not affect the IC functional regions 20 on both sides;
(2) when the cutting of the long-edge cutting channels 6 of the ICs on the wafer 1 is completed, the short-edge cutting channels 7 of the ICs are not cut, and the cutting machine has abnormal vacuum or abnormal clamping jaw 5, so that the long-edge cutting channels 6 of the ICs which are cut are dislocated and deviated, the following operations are carried out:
s11, detecting the lateral offset of the long-edge cutting channel 6 of the IC through the CCD focusing lens 8;
s12, calculating the minimum value of n according to a formula [ (d-t/n) -m ]/2 is more than or equal to 5um, wherein d is the width of the cutting channel 9, t is the lateral offset, n is the number of equally spaced chips, and m is the width of a tool mark 10 of a front cutting knife, so as to obtain the number of equally spaced chips on the part of the wafer 1 which is cut by the cutting channel 6 with the long edge of each IC; if the width d of the cutting path 9 is 80um, the width m of the tool mark 10 of the front cutting knife is 60um, the lateral offset t is 30um, the minimum n is 3 by the formula of [ (80-30/n) -60]/2 is more than or equal to 5, and if the width of the tool mark 10 of the front cutting knife is allowed to be narrowed to 50um under the condition, n can be reduced to 2;
s13, placing a piece of Taiweike paper inside a microscope detection platform jig 11, then placing the outer frame 3 on the microscope detection platform jig 11 with the front side of the wafer 1 facing downwards and fixing the outer frame by using a positioning PIN and a buckle, jacking up an entire row of ICs at the boundary of each IC long-edge cutting channel 6 cut by the wafer 1 and each IC long-edge cutting channel 6 not cut from the blue film 2 by using a thimble jig from the back side of the blue film 2, enabling the entire row of ICs at the boundary to fall on the Taiweike paper, leaving the blue film 2 at the boundary of each IC long-edge cutting channel 6 cut by the wafer 1 and each IC long-edge cutting channel 6 not cut, taking out the entire row of ICs at the boundary, and then re-framing the whole row of ICs through the blue film 2 and the outer frame 3 to perform semi-automatic cutting;
s14, cutting the blue film 2 along the arc-shaped periphery of the part of the wafer 1 which is not cut by the IC long-edge cutting street 6 and the blue film 2 which is hollow in the S13 by using a blade, separating the part of the wafer 1 which is not cut by the IC long-edge cutting street 6 from an iron frame, taking out the part of the wafer 1 which is not cut by the IC long-edge cutting street 6, reversely combining the frames, and then performing semi-automatic cutting;
s15, according to the equal-interval slicing number n obtained in S12, equally-interval slicing is conducted on the wafer 1 part cut through each IC long-edge cutting channel 6, an (n-1) whole-row IC which enables the wafer 1 part cut through each IC long-edge cutting channel 6 to be equally divided into n pieces is found, if the longitudinal widths of the n sliced wafers 1 are not completely equal, semi-automatic cutting of the wafer 1 part after subsequent slicing is not affected, and the longitudinal width deviation of 1-2 ICs is allowed to exist among the n wafer 1 parts; arranging the whole row of ICs transversely, (n-1) respectively positioning the whole row of ICs at corresponding junctions of n equidistant slices, marking the blue film 2 on the outer edge of the (n-1) whole row of ICs on the outer frame 3 (the back of the blue film 2 has tool marks which can not be distinguished), placing a piece of Taivik paper in the microscope detection platform jig 11, then placing the outer frame 3 on the microscope detection platform jig 11 with the front of the wafer 1 which is cut by the long-edge cutting channels 6 of the ICs facing downwards, jacking the marked (n-1) whole row of ICs from the back by using a thimble jig to separate the ICs from the blue film 2 and fall on the Taivik paper, taking out the (n-1) whole row of ICs, re-framing the ICs respectively through the (n-1) group of blue film 2 and the outer frame 3, and then respectively carrying out semi-automatic cutting;
and S16, cutting the outer edges of the blue film 2 and the residual blue film 2 on the outer frame 3 along the whole row of IC positions at the intersection of the (n-1) equidistant slicing by using a blade, so that the n equidistant sliced partial wafers 1 are separated from the outer frame 3, and semi-automatically cutting the n equidistant sliced partial wafers 1 after reversely combining the frames respectively.
In the step (2), when all the IC long-side streets 6 on the wafer 1 are completely cut, all the IC short-side streets 7 are not cut, and the cutting machine is abnormal in vacuum or abnormal in the clamping jaw 5, so that all the IC long-side streets 6 which are completely cut are misaligned, the following operations are performed:
s21, detecting the lateral offset of each IC long-edge cutting channel 6 through the CCD focusing lens 8, calculating the minimum value of n according to a formula [ (d-t/n) -m ]/2 is more than or equal to 5um, and obtaining the quantity of equally-spaced slicing of the whole wafer 1 which is completely cut through each IC long-edge cutting channel 6;
s22, according to the obtained equal-spacing slicing number n of S21, the whole wafer 1 is sliced at equal spacing, so as to find (n-1) whole rows of ICs which enable the whole wafer 1 to be equally divided into n pieces, the whole rows of ICs are transversely arranged, marking blue films 2 on the outer edges of (n-1) whole rows of ICs on the outer frame 3, placing a piece of taverk paper inside a microscope detection platform jig 11, then, the whole wafer 1 with the cut long-edge cutting channels 6 of the ICs faces downwards, the outer frame 3 is placed on a microscope detection platform jig 11, a thimble jig is used for jacking the marked (n-1) whole-row ICs from the back to enable the marked (n-1) whole-row ICs to be separated from the blue film 2 and fall on the Taivik paper, after the (n-1) whole-row ICs are taken out, the (n-1) whole-row ICs are respectively re-framed through the (n-1) group blue film 2 and the outer frame 3, and then semi-automatic cutting is respectively carried out;
and S23, cutting the outer edges of the blue film 2 and the residual blue film 2 on the outer frame 3 along the whole row of IC positions at the intersection of the (n-1) equidistant slicing by using a blade, so that the n equidistant sliced partial wafers 1 are separated from the outer frame 3, and semi-automatically cutting the n equidistant sliced partial wafers 1 after reversely combining the frames respectively.
The situation that the wafer 1 is not completely cut due to abnormal cutting of the wafer 1 is 3, the technical scheme corresponds to the situation 2, and after the whole wafer 1 with the cutting channel laterally deviated is sliced, the single slice is semi-automatically cut.
In the step (2), when all the IC long-side streets 6 on the wafer 1 are cut, and part of the IC short-side streets 7 is cut, and the cutting machine is abnormal in vacuum or abnormal in the clamping jaw 5, so that the part of the wafer 1 which is not cut through each IC short-side street 7 is misaligned, the following operations are performed:
s31, completely cutting the wafer 1 part cut by each IC short edge cutting channel 7, and picking each IC by using a crystal picking machine to empty the blue film 2 in the area where the wafer 1 part cut by each IC short edge cutting channel 7 is located;
s32, detecting the lateral offset of the long IC side cutting channels 6 of the wafer 1 part of each short IC side cutting channel 7 which is not cut through the CCD focusing lens 8, calculating the minimum value of n according to a formula [ (d-t/n) -m ]/2 is not less than 5um, and obtaining the quantity of equally spaced slicing of the wafer 1 part of each short IC side cutting channel 7 which is not cut through;
s33, according to the obtained equal-interval slicing number n of S32, equally-interval slicing is carried out on the part of the wafer 1 which is not cut through each IC short-edge cutting channel 7, n-1 whole-row ICs which enable the part of the wafer 1 which is not cut through each IC short-edge cutting channel 7 to be equally-divided into n pieces are found, the whole-row ICs are transversely arranged, the blue films 2 on the outer edges of the (n-1) whole-row ICs on the outer frame 3 are marked, Tayvale paper is placed inside the microscope detection platform jig 11, then the part of the wafer 1 which is not cut through each IC short-edge cutting channel 7 is placed with the front side facing downwards to enable the outer frame 3 to be placed on the microscope detection platform jig 11, the marked (n-1) whole-row ICs are jacked up from the back side by using a thimble jig to be separated from the blue films 2 and fall on the Tayvale paper, and the (n-1) whole-row ICs are taken out and respectively pass through the blue films 2, Respectively carrying out semi-automatic cutting after the outer frame 3 is closed again;
and S34, cutting the outer edges of the blue film 2 and the residual blue film 2 on the outer frame 3 along the whole row of IC positions at the intersection of the (n-1) equidistant slicing by using a blade, so that the n equidistant sliced partial wafers 1 are separated from the outer frame 3, and semi-automatically cutting the n equidistant sliced partial wafers 1 after reversely combining the frames respectively.
The technical scheme corresponds to the 3 rd condition that the wafer 1 is not completely cut due to abnormal cutting of the wafer 1, the part of the wafer 1 which is cut through each IC short-edge cutting channel 7 is cut, and only after the part of the wafer 1 which is not cut through each IC short-edge cutting channel 7 is sliced, the single slice is semi-automatically cut.
In the step (2), when the lateral offset of the long-edge cutting street 6 of the IC is detected: after the abnormal wafer is reloaded, the CCD focusing lens 8 of the cutting machine is moved to the leftmost side of the lateral offset area of the wafer 1, so that the horizontal correction electronic wire 16 is aligned with the end part 14 of the leftmost IC cutting channel, the CCD focusing lens 8 of the cutting machine is moved to the leftmost side of the lateral offset area of the wafer 1, the horizontal correction electronic wire 16 is also aligned with the end part 15 of the rightmost IC cutting channel, the CCD focusing lens 8 moves from left to right in a stepping jumping mode, the highest point 17 and the lowest point 18 of the whole cutting channel of the lateral offset area of the wafer 1 are confirmed, and the longitudinal distance between the two is the lateral offset.
The reverse frame combination steps are as follows:
a) firstly, placing a part of a wafer 1 needing reverse frame combination on a frame combination working disc 19 with the front face facing upwards, carrying out frame combination, attaching a circular blue film 2 to the front face of the part of the wafer 1 and fixing the circular blue film 2 on the upper side of an outer frame 3;
b) turning over the part of the wafer 1 with the blue film 2 attached to the front surface and placing the part on a frame-combining working disc 19;
c) manually tearing off the residual blue film 2 on the back surface of the part of the wafer 1;
d) placing the back of the part of the wafer 1 upwards on a frame-closing working disc 19 for film pasting, so that the back of the part of the wafer 1 is pasted with a blue film 2;
e) placing the part of the wafer 1 with the front and back surfaces both stuck with the blue film 2 on a frame-closing working disc 19 with the front surface facing upwards;
f) and manually tearing off the adhesive film on the front surface of the wafer 1 part to finish reverse frame combination treatment.
The semi-automatic cutting method comprises the following steps:
step one, calibrating that a rotating main shaft of a cutting knife is parallel to an IC long-edge cutting channel 6
Step two, aligning the lower cutter position of the calibration cutter with the center of the IC short edge cutting path 7;
setting a cutting starting position and setting the number of cutting knives;
and step four, performing semi-automatic cutting and machining operation. When the sliced wafer 1 or the whole IC at the boundary is semi-automatically cut, a horizontal correction electronic wire 16 is found through a CCD focusing lens 8, then the cutting direction of a cutting knife is controlled to be vertical to the horizontal correction electronic wire 16, the wafer is cut along a first IC short edge cutting channel 7 from an initial position, and the uncut wafer 1 is divided into a plurality of ICs; when the wafer 1 which is not cut by the long-side IC scribe lines 6 in step S14 is partially cut, the CCD focus lens 8 is used to find the horizontal correction electron line 16, then the cutting direction of the cutting blade is controlled to be parallel to the horizontal correction electron line 16, the wafer is cut along the first long-side IC scribe line 6 from the initial position, and after the long-side IC scribe lines 6 are cut, the wafer 1 is cut into a plurality of ICs.
The number of the IC long-edge cutting channels 6 on the wafer 1 is 100-400, and the number of the IC short-edge cutting channels 7 is 10-40.
According to the invention, the cutting mode of combining the slicing and reverse frame-combining technologies is used for processing the lateral deviation abnormity of the IC long and short side cutting channels caused by the abnormal cutting, so that the IC21 is separated from the wafer 1, and the loss is reduced. The single-side reservation quantity required by the normal cutting path is more than or equal to 10 um; the abnormal cutting path firstly considers the reduction of the product loss quantity, and secondly considers the influence of the reserved quantity after cutting, so that the single-side reserved quantity is required to be more than or equal to 5 um; and (3) normally cutting a street: the unilateral allowance = [ (cutting path width-lateral offset) -front cutting knife mark width ]/2 is more than or equal to 10um (the lateral offset is 0 under the normal cutting condition); after the lateral deviation, the cutting path is in an arch shape or an S shape, and for the arch shape and the S shape cutting path: the unilateral reservation quantity = [ (d-t/n) -m ]/2 is larger than or equal to 5um, wherein d is the width of a cutting path, t is the lateral offset, n is the number of equally spaced fragments, m is the width of a cutter mark 10 of a front cutting knife, and the width of the cutter mark 10 of the front cutting knife is larger than the width of a cutter mark 10a of a rear cutting knife; the width of the tool mark 10 of the front cutting knife is influenced by the width of a test pattern on a product cutting path, the width of the tool mark 10 of the front cutting knife is limited to a certain extent before changing, and the width of the tool mark 10 of the front cutting knife can be narrowed under the condition so as to reduce the quantity of equally spaced fragments. The invention has the advantages that: the long-edge cutting channels 6 and the short-edge cutting channels 7 of the ICs on the blue film 2 have the characteristic of consistent overall trend during twisting, the laterally-offset wafer 1 is efficiently sliced, the laterally-offset wafer 1 is divided into a plurality of slices which do not influence the cutting operation through the least-frequency division, and the slices are cut in a semi-automatic mode independently to smoothly complete the cutting operation; the loss of the wafer 1 caused by the abnormal cutting paths of the long and short sides of the IC21 is reduced, the company cost is saved, and the customer complaints are avoided; the slicing cutting mode is combined with the semi-automatic cutting mode, and the cutting abnormity processing mode is unlimited.
Claims (8)
1. A slicing and cutting method for processing abnormal cutting of a wafer is characterized by comprising the following steps:
(1) the method comprises the following steps of (1) combining a wafer, fixing the wafer on an outer frame through a blue film, placing the combined wafer on a vacuum working disc in a cutting machine, fixing the outer frame through a plurality of clamping jaws distributed at intervals along the circumferential direction, and performing cutting operation by a cutting knife according to the sequence of cutting long-edge cutting channels of ICs on the wafer and then cutting short-edge cutting channels of the ICs;
(2) when the cutting of the long-edge cutting channels of the ICs on the wafer is completed, the short-edge cutting channels of the ICs are not cut, and the cutting machine has vacuum abnormity or clamping jaw abnormity, the cutting machine carries out the following operations when the cut long-edge cutting channels of the ICs are dislocated and deviated:
s11, detecting the lateral offset of the long-edge cutting channel of the IC through a CCD focusing lens;
s12, calculating the minimum value of n according to a formula [ (d-t/n) -m ]/2 is more than or equal to 5um, wherein d is the width of the cutting channel, t is the lateral offset, n is the number of equally spaced chips, and m is the width of the tool mark of the front cutting knife, so as to obtain the number of equally spaced chips on the wafer part which is cut by the cutting channel with the long edge of each IC;
s13, placing a piece of Taiweike paper inside a microscope detection platform jig, then placing and fixing an outer frame on the microscope detection platform jig with the front side of a wafer facing downwards, jacking up a whole row of ICs at the boundary of each IC long-edge cutting channel cut by the wafer and each IC long-edge cutting channel not cut by using an ejector pin jig from the back side of a blue film to separate the ICs from the blue film, and enabling a whole row of ICs at the boundary to fall on the Taiweike paper, so that a blue film is left at the boundary of each IC long-edge cutting channel cut by the wafer and each IC long-edge cutting channel not cut, taking out a whole row of ICs at the boundary, re-framing the whole row of ICs through the blue film and the outer frame, and then carrying out semi-automatic cutting;
s14, cutting the blue film and the arc-shaped periphery blue film of the wafer part which is not cut by the IC long-edge cutting channel in the hollow S13 by using a blade, separating the wafer part which is not cut by the IC long-edge cutting channel from the iron frame, taking out the wafer part which is not cut by the IC long-edge cutting channel, and performing semi-automatic cutting after reversely closing the frame;
s15, according to the number n of equally spaced slices obtained from S12, equally spaced slices are carried out on the wafer part which is cut by each IC long edge cutting channel, n-1 whole rows of ICs which are used for equally dividing the wafer part which is cut by each IC long edge cutting channel are found, the whole rows of ICs are transversely arranged, the n-1 whole rows of ICs are respectively positioned at corresponding junctions of the n equally spaced slices, a mark is made on the outer edge blue film of the (n-1) whole rows of ICs on an outer frame, a piece of Taivik paper is placed in a microscope detection platform tool, then the wafer part which is cut by each IC long edge cutting channel is placed on the microscope detection platform tool with the front side facing downwards, the marked (n-1) whole rows of ICs are jacked from the back side by using a thimble tool to be separated from the blue film and fall on the Taivik paper, and the (n-1) whole rows of ICs are taken out and pass through the (n-1) groups of blue films respectively, Respectively carrying out semi-automatic cutting after the outer frame is closed again;
and S16, cutting the outer edges of the blue film and the residual blue film on the outer frame along the whole row of IC positions at the intersection of the (n-1) equidistant sub-frames by using a blade, so that the n equidistant sub-frames are separated from the outer frame, and semi-automatically cutting the n equidistant sub-frames after reversely closing the frames.
2. The dicing method according to claim 1, wherein in the step (2), when all the long-side streets on the wafer are completely diced, none of the short-side streets on the wafer are diced, and the dicing machine has a vacuum anomaly or a clamping jaw anomaly, which causes a misalignment of all the diced long-side streets on the wafer, the following operations are performed:
s21, detecting the lateral offset of each IC long-edge cutting channel through a CCD focusing lens, calculating the minimum value of n according to a formula [ (d-t/n) -m ]/2 is more than or equal to 5um, and obtaining the quantity of equally-spaced slicing of the whole wafer which is completely cut through each IC long-edge cutting channel;
s22, performing equidistant slicing on the whole wafer according to the equidistant slicing number n obtained in S21, finding (n-1) whole-row ICs which enable the whole wafer to be equidistantly sliced into n pieces, transversely arranging the whole-row ICs, marking blue films on the outer edges of the (n-1) whole-row ICs on an outer frame, placing Taivk paper in a microscope detection platform jig, enabling the front side of the whole wafer with the long-edge cutting channels of the ICs cut to face downwards to enable the outer frame to be placed on the microscope detection platform jig, jacking the marked (n-1) whole-row ICs from the back side by using a thimble jig so as to be separated from the blue films and fall on the Taivk paper, taking out the (n-1) whole-row ICs, respectively re-framing through the (n-1) blue films and the outer frame, and then respectively performing semi-automatic cutting;
and S23, cutting the outer edges of the blue film and the residual blue film on the outer frame along the whole row of IC positions at the intersection of the (n-1) equidistant sub-frames by using a blade, so that the n equidistant sub-frames are separated from the outer frame, and semi-automatically cutting the n equidistant sub-frames after reversely combining the n equidistant sub-frames.
3. The dicing method according to claim 1, wherein in the step (2), when the whole cutting of the long-side streets, the partial cutting of the short-side streets, and the vacuum anomaly or the clamping jaw anomaly of the dicing machine on the wafer result in the misalignment of the wafer part which has not been cut through the short-side streets, the following operations are performed:
s31, completely cutting the wafer part cut by each IC short edge cutting way, and picking out each IC by using a wafer picking machine to empty the blue film in the area where the wafer part cut by each IC short edge cutting way is located;
s32, detecting the lateral offset of the long-edge cutting channels of the IC of the wafer part of each IC short-edge cutting channel which is not cut through a CCD focusing lens, and calculating the minimum value of n according to a formula [ (d-t/n) -m ]/2 is more than or equal to 5um to obtain the quantity of equally-spaced slicing of the wafer part of each IC short-edge cutting channel which is not cut;
s33, according to the equal-spacing slicing number n obtained from S32, the wafer part which is not cut by each IC short edge cutting channel is sliced at equal spacing, so as to find (n-1) whole rows of ICs which are equally divided by the wafer part which is not cut by each IC short edge cutting channel, the whole rows of ICs are transversely arranged, marking blue films on the outer edges of n-1 whole rows of ICs on the outer frame, placing a piece of Taivin paper inside a microscope detection platform jig, then, the front side of the wafer part which is not cut through the short-edge cutting channels of the ICs is downward, so that the outer frame is placed on a microscope detection platform jig, a thimble jig is used for jacking the marked (n-1) whole-row ICs from the back side to enable the marked (n-1) whole-row ICs to be separated from the blue film and fall on the Taivik paper, the (n-1) whole-row ICs are taken out and then respectively subjected to semi-automatic cutting after being re-framed through the (n-1) group blue film and the outer frame;
and S34, cutting the outer edges of the blue film and the residual blue film on the outer frame along the whole row of IC positions at the intersection of the (n-1) equidistant sub-frames by using a blade, so that the n equidistant sub-frames are separated from the outer frame, and semi-automatically cutting the n equidistant sub-frames after reversely closing the frames.
4. The dicing method according to any one of claims 1 to 3, wherein in the step (1), the number of the iron rings is 4, the cutting knives are used for cutting synchronously with two knives, the front cutting knife and the rear cutting knife are spaced, the front cutting knife slots the wafer, the depth of the front cutting knife cutting the wafer is 1/3-1/5 of the thickness of the wafer, the rear cutting knife separates the wafer, the depth of the rear cutting knife cutting the wafer is the depth of cutting the wafer and cutting the wafer to 30-50 μm of the blue film,
the long edge cutting channels of the ICs of the wafers on the working disc are cut by the front cutter and the rear cutter firstly, and after the working disc rotates by 90 degrees, the short edge cutting channels of the ICs of the wafers on the working disc are cut by the front cutter and the rear cutter again.
5. The dicing method according to any one of claims 1 to 3, wherein in the step (2), when detecting the lateral offset of the long-side scribe line of the IC: the method comprises the steps of moving a CCD focusing lens of a cutting machine to the leftmost side of a wafer lateral offset area to enable a horizontal correction electronic wire to be aligned with the end part of a leftmost IC cutting channel, moving the CCD focusing lens of the cutting machine to the rightmost side of the wafer lateral offset area to enable the horizontal correction electronic wire to be aligned with the end part of the rightmost IC cutting channel, moving the CCD focusing lens from left to right in a stepping jumping mode to confirm the highest point and the lowest point of the whole cutting channel of the wafer lateral offset area, wherein the longitudinal distance between the CCD focusing lens and the bottommost IC cutting channel is the lateral offset.
6. The dicing method according to any one of claims 1 to 3, wherein the step of reversely closing the frame comprises:
a) firstly, placing a wafer part needing reverse frame combination on a frame combination working disc in a way that the front side of the wafer part is upward, and carrying out frame combination to ensure that the front side of the wafer part is attached with a circular blue film and the circular blue film is fixed on the upper side of an outer frame;
b) turning over the part of the wafer with the front surface stuck with the blue film and placing the part of the wafer on a frame-combining working disc;
c) manually tearing off the residual blue film on the back of the wafer part;
d) placing the back of the wafer part upwards on a frame-closing working disc for film pasting, so that the back of the wafer part is pasted with a blue film;
e) placing the wafer part with the front side and the back side both stuck with the blue film on a frame-combined working disc with the front side facing upwards;
f) and manually tearing off the adhesive film on the front surface of the wafer part to finish reverse frame combination treatment.
7. The dicing method according to any one of claims 1 to 3, wherein the semi-automatic dicing step comprises:
step one, calibrating that a rotating main shaft of a cutting knife is parallel to a long-edge cutting channel of an IC
Step two, aligning the lower cutter position of the calibration cutter with the center of the IC short edge cutting path;
setting a cutting starting position and setting the number of cutting knives;
and step four, performing semi-automatic cutting and machining operation.
8. The dicing method according to any one of claims 1 to 3, wherein the number of the IC long side streets on the wafer is 100 to 400, and the number of the IC short side streets is 10 to 40.
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| JP2009158648A (en) * | 2007-12-26 | 2009-07-16 | Disco Abrasive Syst Ltd | Method for dicing wafer |
| CN104183476A (en) * | 2013-05-28 | 2014-12-03 | 松下电器产业株式会社 | Cutting residual removing device |
| US20190035689A1 (en) * | 2017-07-28 | 2019-01-31 | Disco Corporation | Wafer processing method |
| CN110676219A (en) * | 2019-10-31 | 2020-01-10 | 江苏汇成光电有限公司 | Wafer cutting processing method for coping with vacuum abnormity |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009158648A (en) * | 2007-12-26 | 2009-07-16 | Disco Abrasive Syst Ltd | Method for dicing wafer |
| CN104183476A (en) * | 2013-05-28 | 2014-12-03 | 松下电器产业株式会社 | Cutting residual removing device |
| US20190035689A1 (en) * | 2017-07-28 | 2019-01-31 | Disco Corporation | Wafer processing method |
| CN110676219A (en) * | 2019-10-31 | 2020-01-10 | 江苏汇成光电有限公司 | Wafer cutting processing method for coping with vacuum abnormity |
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