CN114586145A - 凸起结构的形成 - Google Patents
凸起结构的形成 Download PDFInfo
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- CN114586145A CN114586145A CN202080071173.6A CN202080071173A CN114586145A CN 114586145 A CN114586145 A CN 114586145A CN 202080071173 A CN202080071173 A CN 202080071173A CN 114586145 A CN114586145 A CN 114586145A
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- bump
- layer
- substrate
- pads
- solder
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Abstract
公开了一种凸起结构的制造技术。制备包括形成在其表面上的衬垫的组的衬底,衬垫包括第一导电材料。在每个衬垫上涂覆金属粘合层。通过使用模制层烧结导电颗粒来在每个衬垫上形成凸起基底,导电颗粒包括与所述第一导电材料不同的第二导电材料。
Description
技术领域
本发明涉及凸起形成(bumping)技术,尤其涉及一种凸起(bump)结构的制造方法、凸起结构、包括凸起结构的电子装置及电子装置的制造方法。
背景技术
3D和2.5D芯片封装是能够实现宽带信号传输和短布线长度的技术,并且它已经吸引了在未来对改进计算机***性能的注意。由于与传统的倒装芯片封装相比,3D和2.5D封装中的凸起间距和凸起尺寸变得精细,所以出现了由于焊点及其界面处的应力集中而引起的可靠性问题以及由于高电流密度而引起的电迁移。
IMS(注射成型焊料)技术是一种凸起形成技术,其中通过将熔融焊料直接注入抗蚀剂掩模中的开口中而在衬底上形成焊料凸起。IMS技术具有焊料合金组合物的灵活性的优点,这导致机械特性和抗电迁移性以及细间距能力的改善。
高密度互连的最近趋势已经导致使用铜柱(或柱)凸起。然而,需要昂贵的镀铜工艺来制造焊料帽下面的铜柱。存在另一种能够在不使用昂贵的电镀工艺的情况下来制造柱状凸起的技术,其中,通过烧结通常以膏糊状形式提供的导电颗粒来制造柱状物。当在由相同材料制成的接触衬垫(pad)上制造柱时,即在铜衬垫上制造烧结铜柱时,烧结柱显示出良好的可靠性。
然而,当使用不同于柱的导电材料,尤其是铝作为接触衬垫时,即使在凸起形成之前去除铝衬垫的表面氧化物,柱和接触衬垫之间的粘附力也会降低。
因此,需要一种新颖的凸起形成技术,其能够制造包括形成在衬底上的一组凸起的凸起结构,其中通过烧结导电颗粒而制成的凸起紧密地接合到由不同于导电颗粒的导电材料制成的衬垫。
发明内容
根据本发明的实施例,提出一种凸起结构的制造方法。该方法包括制备包括形成在其表面上的衬垫的组的衬底,其中衬垫包括第一导电材料。该方法还包括在每个衬垫上涂覆金属粘合层。该方法还包括通过使用模制(mold)层烧结导电颗粒,来在每个衬垫上形成凸起,其中导电颗粒包括不同于第一导电材料的第二导电材料。
这使得能够在衬底上制造包括凸起的组的凸起结构,其中即使衬垫由不同于导电颗粒的导电材料制成,通过烧结导电颗粒所制成的凸起也紧密地接合到衬底的衬垫。
在实施例中,模制层具有开口的组,开口中的每一个与衬垫中的一个相对准。该方法包括,在每个衬垫上形成凸起时,将模制层设置在衬底上,并将导电颗粒填充到模制层的开口中。烧结填充在模制层的开口中的导电颗粒以在每个衬垫上形成凸起基底。该方法还包括将焊料材料填充到凸起基底上方的模制层的每个开口中的剩余空间中,以在每个凸起基底上形成焊料帽。
在实施例中,第一导电材料包括Al,第二导电材料包括Cu。由于半导体器件通常在最外层使用Al衬垫,因此可以制造与衬垫紧密接合的被烧结的凸起基底以用于实际使用。
在实施例中,导电颗粒以膏糊的形式提供。形成于每个焊垫上的凸起基底具有与模制层的开口轮廓相一致的杯状物形状,且具有由金属粘合层而接合于焊垫的底部。因此,即使凸起尺寸与平顶柱形相比变得精细,它也允许我们在凸起基底上保持足够的焊料体积。此外,具有杯状物形状的凸起基底在抗电迁移方面具有优点,因为电流的流动在这种成形的凸起中分散。
在实施例中,该方法还包括在衬底的表面上施加抗蚀剂层。该方法还包括图案化抗蚀剂层以制造模制层。该方法还包括在衬垫和模制层上沉积金属粘合材料,以便与模制层的轮廓相符,并提供涂覆在每个衬垫上的金属粘合层。由于在抗蚀剂剥离之后去除抗蚀剂层下面的金属层的工艺被消除,所以防止了在凸起的根部处的底切(undercut)。
在实施例中,该方法包括在填充焊料材料时,将沉积在模制层的顶表面上的金属粘合材料溶解到焊料材料中。由此,能够在充分地除去多余的金属粘合材料的同时,省略多余的金属粘合材料的除去工艺。在该优选实施例中,金属粘合材料可以从由Cu、Ni、Au及其任意组合组成的组中选择。在焊料材料的填充过程中,Cu、Ni和Au将容易地溶解到诸如熔融焊料的焊料材料中。
在实施例中,该方法还包括从衬底剥离模制层,以便将模制层清洗掉,其中在模制层的顶表面上的金属粘合材料连同模层一起被剥离并被清洗。因此,其允许省略额外金属粘合材料的去除工艺,而不管金属粘合材料的组成。因此,即使该材料不溶于焊接材料(如熔融焊料),它也允许我们使用其它功能材料(如Ti阻挡层)作为金属粘合材料。此外,与模制层轮廓一致的金属粘合材料将用作防止由于离子迁移引起的凸起之间的短路的侧壁阻挡物。
在一个实施例中,该方法还包括通过选自化学机械抛光(CMP)、机械抛光、飞切和化学蚀刻的技术来去除沉积在模制层的顶表面上的金属粘合材料。尽管执行了额外金属粘合材料的去除工艺,但是,消除了在抗蚀剂剥离之后的金属层的去除工艺,该去除工艺将在凸起的根部处引起底切。即使该材料不溶于焊接材料(如熔融焊料),它也允许我们使用其它功能材料(如Ti阻挡层)作为金属粘合材料。此外,与模制层轮廓一致的金属粘合材料将用作防止由于离子迁移引起的凸起之间的短路的侧壁阻挡物。
在实施例中,该方法还包括在衬底的表面上沉积金属粘合材料,以具有对应于涂覆在衬垫中的每一个上的金属粘合层的第一部份以及形成在焊垫的***区域上的第二部份。该方法包括在金属粘合材料上施加抗蚀剂层。该方法还包括图案化抗蚀剂层以制造模制层。该方法包括从衬底上剥离模制层,从而在衬底上留下凸起,其中每一个凸起包括焊料帽及形成在衬垫上的凸起基座。该方法还包括移除从所述凸起暴露的所述金属粘合材料的第二部分。即使该材料不溶于焊接材料(如熔融焊料),它也允许我们使用其它功能材料(如Ti阻挡层)作为金属粘合材料。在该实施例中,金属粘合材料可以从由Cu、Ti、Ni、Au及其任意组合组成的组中选择。
在实施例中,填充焊料材料包括将熔融焊料注入模制层的开口中的每一个中。在本实施例中,不需要电镀和无电解电镀来制造该凸起的组,从而避免了昂贵的柱和焊料帽制造工艺、昂贵的设备和电镀工艺的复杂管理。
在实施例中,该方法包括在涂覆金属粘合层之前,通过反溅射来从衬垫去除表面氧化物,金属粘合层被通过溅射而涂覆在每个衬垫上。反溅射和金属粘合层的溅射的组合优选地减少从表面氧化物去除到衬垫的表面涂覆的时间间隔。
在实施例中,衬底包括半导体器件,且衬垫的组至少形成在半导体器件的有源表面上。该方法还包括利用凸起将半导体器件互连到外部电路,所述方法是电子器件的制造方法。烧结的高温条件将有助于增强烧结的柱和衬垫之间的结合。然而,半导体器件通常在这样的高温条件下劣化。这使得能够在不使用高温条件的情况下增强凸起基底和衬垫之间的接合。
根据本发明的另一实施例,提供一种凸起结构。该凸起结构包括衬底,衬底包括形成在其表面上的衬垫的组,其中衬垫包括第一导电材料。凸起结构包括凸起的组,凸起中的每一个形成在衬垫中的一个上。每个凸起包括形成在衬垫上的金属粘合层和形成在金属粘合层上的凸起基底。凸起基底为包括与第一导电材料不同的第二导电材料的导电颗粒的烧结体。
由于通过烧结导电颗粒而制成的凸起紧密地接合到衬垫,所以即使衬垫由不同于导电颗粒的导电材料制成,根据本发明实施例的凸起结构也显示出良好的可靠性。此外,其使得能够在不使用高温条件的情况下,增强凸起基底与衬垫之间的接合。因此,可以防止由于凸起工艺而导致的半导体器件的劣化。
在实施例中,每个凸起进一步包含形成在凸起基底上的焊料帽。凸起基底具有杯状形状,杯状物具有经由金属粘合层而接合到衬垫的底部,并且杯状物填充有焊料帽的焊料材料。在特定实施例中,第一导电材料可包括Al,第二导电材料可包括Cu,且金属粘合层可包括选自Cu、Ti、Ni、Au及其组合的材料。
在实施例中,金属粘合层覆盖凸起基底的侧表面作为侧壁阻挡物。因此,侧壁阻挡物防止了由于离子迁移引起的凸起之间的短路。
在本发明的另一实施例中,提供了一种电子设备。该电子器件包括半导体器件,该半导体器件包括形成在其有源表面上的衬垫的组,其中衬垫包括第一导电材料。该电子器件还包括凸起的组,每个凸起形成在衬垫中的一个上。每个凸起包括形成在衬垫上的金属粘合层和形成在金属粘合层上的凸起基底,并且凸起基底是包括不同于第一导电材料的第二导电材料的导电颗粒的烧结体。该电子器件还包括通过凸起的组与半导体器件互连的电路。
根据本发明实施例的电子器件表现出良好的耐久性,因为即使衬垫由与用于凸起基底的导电颗粒不同的导电材料制成,通过烧结导电颗粒而制成的凸起也紧密地接合到衬垫。
在实施例中,金属粘合层覆盖凸起基底的侧表面作为侧壁阻挡物。侧壁阻挡物的提供防止了由于离子迁移引起的凸起之间的短路。
在本发明的另一实施例中,提供了一种制造电子器件的方法。该方法包括制备凸起化半导体器件。该凸起化半导体器件包括衬底,该衬底包括形成在其表面上的衬垫的组,其中衬垫包括第一导电材料。该凸起化半导体器件还包括凸起的组,每个凸起形成在衬垫中的一个上,其中每个凸起包括形成在衬垫上的金属粘合层和形成在金属粘合层上的凸起基底,并且凸起基底是包括不同于第一导电材料的第二导电材料的导电颗粒的烧结体。该方法还包括通过凸起的组将凸起化半导体器件互连到外部电路。
根据本发明实施例的方法提供的电子器件表现出良好的耐久性,因为即使衬垫由与用于凸起基底的导电颗粒不同的导电材料制成,通过烧结导电颗粒制成的凸起也紧密地接合到衬垫。
通过本发明的技术实现了附加的特征和优点。本发明的其它实施例和方面在这里被详细描述,并且被认为是所要求保护的发明的一部分。
附图说明
面结合附图的详细描述中,本发明的前述和其它特征和优点是显而易见的。注意,附图中的元件和层的尺寸和相对位置不一定按比例绘制。这些元件或层中的一些被任意放大和定位以提高附图的易读性。在附图中:
图1A与图1B分别为本发明的实施例的凸起结构的剖面图与顶视图;
图2A-2E是在根据本发明实施例的凸起形成工艺的每个步骤获得的结构的截面图(1/2);
图3A-3D是在根据本发明实施例的凸起形成工艺的每个步骤获得的结构的截面图(2/2);
图4A-4D是在根据本发明另一实施例的凸起形成工艺的每个步骤获得的结构的截面图(1/2);
图5A-5D是根据本发明另一实施例的在凸起形成工艺的每个步骤获得的结构的截面图(2/2);
图6A-6C是在根据本发明另一实施例的凸起形成工艺的每个步骤处获得的结构的截面图;
图7A-7D是在根据本发明另一实施例的凸起形成工艺的每个步骤获得的结构的截面图;
图8A和8B是在根据本发明实施例的倒装结合工艺的每个步骤中获得的结构的截面图;
图9A-9E示出了包括柱和焊料帽的电镀的相关凸起形成工艺;
图10A-10E示出了包括柱的电镀和焊料帽的IMS的另一相关凸起形成工艺;
图11A-11D示出了包括柱的无电镀和焊料帽的IMS的另一相关凸起形成工艺;
图12A-12D示出了另一种相关的凸起形成工艺(1/2),其基于不使用金属粘合层的导电膏糊烧结;以及
图13A-13C示出了基于烧结工艺而不使用金属粘合层的另一相关凸起形成工艺(2/2)。
具体实施方式
以下,将参照特定实施例描述本发明,但是本领域技术人员将理解,以下描述的实施例仅通过示例的方式提及,而不是要限制本发明的范围
根据本发明的一个或多个实施例涉及一种制造凸起结构的方法、相关凸起结构、包括凸起结构的相关电子器件以及制造包括凸起结构的电子器件的相关方法,其中实现了紧密接合到衬底的相应衬垫的一组凸起。在下文中,参照图1A和图1B,描述根据本发明示例性实施例的凸起结构。图1A示出了凸起结构100的截面图。图1B显示凸起结构100的顶视图。注意,图1A所示的截面图对应于图1B的顶视图中由“A”表示的截面。
图1所示的凸起结构100包括具有焊垫112的组的衬底110以及形成于衬底110表面的钝化层114。凸起结构100还包括凸起120的组,每个凸起形成在衬垫112中的对应一个衬垫上。注意,为了方便起见,与凸起120相关的附图标记仅针对图中的一个代表性凸起而不是所有元件来指示。
衬底110可以是由半导体材料制成的任何衬底。在特定实施例中,衬底110是其中内置有多个电子装置的晶片(或面板)。在该特定实施例中,晶片可以最终被分成多个芯片(或管芯)。在其它特定实施例中,衬底110是与晶片分离的芯片。在所述实施例中,晶片和芯片都是半导体器件。晶圆与晶片可由硅、III-V或II-VI族化合物半导体材料或其他半导体材料制成。晶片和芯片可以通过任何标准半导体工艺来制造,包括FEOL(前端工艺)和BEOL(后端工艺)工艺。尽管在所述实施例中,将衬底110描述为半导体器件,然而,可以使用诸如陶瓷衬底和玻璃衬底、印刷电路板的任何其它衬底作为衬底110。
衬垫112由导电材料制成。导电材料的示例通常可以包括诸如铝(Al)、铜(Cu)、钴(Co)和其它金属材料的金属。以下,将主要描述衬垫112由Al制成的情况,作为本凸起形成技术适用的示例。衬垫112可以一定间距(例如20~300微米)设置于衬底110的表面上。如图1B所示,该组衬垫112以2维阵列形成。钝化层114可以包括绝缘材料,例如氧化硅(SiO2)。
尽管图1A-1B中未示出,除了凸起120的组之外,衬底110可以包括电子元件、诸如光电二极管(PD)和发光二极管(LED)的光电子元件和/或连接到凸起120的多个布线层。衬底110也可具有半导体衬底的叠层。图1A还描绘了每个凸起120的更详细的结构。如图1A所示,每一凸起120包括形成于衬垫112上的金属粘着层126以及通过金属粘着层126形成于衬垫112上的凸起基底122。每个凸起120还可包括形成在凸起基底122上的焊料帽124。注意,金属粘合层126是一种凸起下金属(UBM)。
凸起基底122由导电材料制成,其通常可包括铜(Cu)、镍(Ni)、银(Ag)、金(Au)或其它金属材料。通过使用设置在衬底110上的模制层或抗蚀剂层烧结导电颗粒来制造每个凸起基底122。因此凸起基底122是包括与衬垫112的导电材料不同的导电材料的导电颗粒的烧结体。在下文中,将主要描述凸起基底122由铜制成的情况作为本凸起形成技术适用的示例。因此,导电粒子为铜粒子,而凸起基底122为铜粒子的烧结体。
在优选的实施方式中,铜纳米颗粒、铜微米颗粒及其混合物用于凸起基底形成。导电颗粒的烧结体将具有多孔形态。颗粒的尺寸可以在1nm至15μm的范围内。
凸起基底122具有杯状形状,其底部经由金属粘合层126接合到衬垫112。凸起基底122的杯状物填充有焊料帽124的焊料材料。
金属粘合层126由从由Cu、Ti、Ni、Au和上述元素的组合所组成的组中而选择的金属材料制成。金属粘合层126可以包括单层或多层(或叠层),其中每一层都包括作为纯金属的上述元素或作为合金的两种或更多种上述元素。在特定实施例中,金属粘合层126是Ti/Cu的叠层、Cu、Au和/或Ni的层或叠层。
焊料帽124的焊料材料可以具有任何适当的成分。在一个或多个实施方案中,任何无铅焊料合金可以用作焊料材料,所述无铅焊料合金包括选自包括下来的组:锡、铋、银、铟、锑、铜、锌、镍、铝、锰和钯的一种或多种元素的二元、三元和四元体系。无铅焊料合金的例子可以包括Bi-Sn、Sn-Ag、Sn-Ag-Bi、Sn-Ag-Cu、Sn-Cu合金,仅举几个例子。在焊料的成分方面具有高自由度的情况下,可以选择适合于凸起形成的任何成分。
以下,请参照图2A至图2E以及图3A至图3D系列,其绘示本发明一实施例的凸起结构的形成过程。图2A-2E和图3A-3D示出了在凸起形成工艺的每个步骤获得的结构的截面图,该凸起形成工艺制造了图1A和1B中所示的凸起结构100。
如图2A所示,凸起形成工艺可包括制备衬底110的步骤,该衬底110包括衬垫112的组和形成在衬底110的表面110A上的钝化层114。在特定实施例中,凸起形成工艺作为晶片级工艺进行,且衬底110是其中内置多个集成电路的晶片。每个衬垫112可以包括导电材料。当衬垫112由诸如Al的易于氧化的金属形成时,凸起形成工艺还可以包括从衬垫112去除表面氧化物的步骤。表面氧化物的去除实际上可以通过任何标准方法来完成,包括例如反溅射、用酸性溶液蚀刻。
如图2B所示,凸起形成工艺可以包括在准备好的衬底110的表面110a上沉积金属粘合材料128的步骤。沉积的金属粘合材料128可以包括第一部分128a和第二部分128b。第一部分对应于涂覆在衬垫112上的金属粘合层126。第二部分128b是形成在衬垫112的外部区域上的部分,其中通常可以形成钝化层114。任何已知的通常用于电镀柱体的晶种层都可以用作金属粘合材料128。金属粘合材料选自Cu、Ti、Ni、Au及其组合。在特定实施例中,金属粘合层126是Ti/Cu的叠层、Cu、Au和/或Ni的层或叠层。金属粘合材料128的沉积实际上可以通过任何标准方法进行,包括例如溅射、无电镀。注意,溅射可以在整个区域上给出金属粘合层,而无电镀可以在包括衬垫112的有限区域上给出金属粘合层。
尽管表面氧化物的去除和金属粘合材料128的沉积实际上通过任何标准方法来执行,但是当衬垫112由容易且持久氧化的金属(例如Al)形成时,优选地采用反溅射和金属粘合材料的溅射的组合来减少从衬垫112的表面氧化物去除到表面保护的时间间隔。长时间间隔将导致Al衬垫的接合的劣化。此外,从消除电镀工艺的观点来看,这种组合是有利的,电镀工艺本身通常是昂贵的,并且需要昂贵的设备和电镀工艺的复杂管理。
如图2C所示,凸起形成工艺还可以包括在金属粘合材料128上施加抗蚀剂层130的步骤。可以使用任何已知的正性或负性液体或薄膜光致抗蚀剂。抗蚀剂层130实际上可以通过任何标准方法施加,包括旋涂、薄膜层压。
如图2D所示,凸起形成工艺还可以包括图案化抗蚀剂层130以具有穿过抗蚀剂层130而形成的开口130a的组的步骤。每个开口130a与相应的衬垫112对准。开口130a暴露衬垫112上的金属粘合材料128的表面。图案化的抗蚀剂层130可以用作用于使填充在开口130a中的材料成形的模制层。开口130a可具有任何形状,其可包括但不限于圆形、正方形、圆角正方形,仅举几个例子。注意,当采用化学镀来沉积金属粘合材料128时,可以在该抗蚀剂图案化之后进行化学镀。抗蚀剂层130可以通过包括光刻的几乎任何标准手段来图案化。在特定实施例中,图案化的步骤可包含用光掩模131曝光光致抗蚀剂材料且显影经曝光的光致抗蚀剂材料以便在与衬垫112对准的位置处打开开口130a的子步骤。在图2D所示的实施例中,光掩模131是暗场掩模,抗蚀剂材料是正型的,没有限制。
抗蚀剂层130可以具有设计的厚度,该厚度可以提供用于凸起形成的足够高度。开口130a的直径可影响最终获得的凸起120的尺寸。在一个实施例中,开口130a的直径可以在5微米至150微米的范围内。而且,开口130a的空间可提供空间以容纳将由后续填充步骤填充的导电材料。
如图2E所示,凸起形成工艺还可包括将导电颗粒132填充到抗蚀剂层130的开口130a中的步骤。导电颗粒132可以包括与衬垫112的导电材料不同的导电材料。导电颗粒的实例可以包括例如铜(Cu)、镍(Ni)、银(Ag)和金(Au)。在优选的实施方式中,导电颗粒可以是铜(Cu)颗粒。纳米颗粒、微米颗粒及其混合物可以用作导电颗粒132。
导电颗粒的直径可以在1nm至15μm的范围内。
在所述的实施例中,导电颗粒以膏糊的形式提供。导电颗粒(在下文中也称为导电膏糊)132的填充可以通过实际上任何标准手段来完成,包括例如丝网印刷和注射技术。导电颗粒可以浸入有机溶剂中。导电膏糊132的粘度和导电膏糊132中的颗粒比例可以考虑膏糊收缩来确定,换句话说,通过下一步骤的烧结获得的导电层的厚度。
如图3A所示,凸起形成工艺还可以包括烧结导电膏糊132的步骤。将填充在抗蚀剂层130的每个开口130a中的导电膏糊132烧结,以在每个衬垫112上形成凸起基底122。进行开口130a中的导电膏糊132的烧结,以在氮气或甲酸的气氛中在100至250摄氏度下加热导电膏糊132 0.1至2.0小时,以防止烧结之后金属表面的氧化。如果在空气中进行烧结,则可以去除金属表面上的氧化层。
烧结是通过加热和/或加压形成材料的固体块而不将材料熔化至液化点的过程。在烧结工艺中,导电膏糊132收缩,使得凸起基底122被形成以覆盖抗蚀剂层130的开口130A的侧壁以及衬垫112(即金属粘合材料128)的表面,如图3A所示。结果,形成在每个衬垫112上的凸起基底122将具有与开口130a的轮廓一致的杯形形状,并且具有经由金属粘合材料128而紧密结合到衬垫112的底部。由于在下一步骤中执行焊料填充而无需另外的导电膏糊涂覆,因此优化了烧结之后导电膏糊132的体积收缩。导电膏糊132的体积收缩率取决于凸起直径/高度的设计值,并且例如优选为50%或更大。
凸起基底122对应于金属柱(或支柱)。空间136b保留在到达开口130a的上端的凸起基底122上。凸起基底122具有锥形表面,如图3A所示。凸起底部122的横截面具有共形的形状。
在所述实施例中,填充导电膏糊132的步骤和烧结导电膏糊132的步骤分别同时执行。然而,当凸起基底122的中心部分的厚度比预定厚度薄时,例如,该预定厚度可以在1至50μm的范围内,交替地多次执行导电膏糊填充步骤和烧结步骤,以形成一个或多个附加导电层,从而确保凸起基底122的预定厚度。
如图3B所示,凸起形成工艺还可包括将焊料材料填充到凸起基底122上方的每个开口130a中的剩余空间130B中以在每个凸起基底122上形成焊料帽124的步骤。在优选实施例中,可以通过将熔融焊料注入到抗蚀剂层130的每个开口130a中来填充焊料材料。熔融焊料的注入例如可以通过IMS工艺来完成。覆盖抗蚀剂层130的开口130a的侧壁的凸起基底122的存在将便于用焊料材料填充开口130a。在IMS工艺中,通过使用填充头,在真空或减压条件下,将熔融焊料注入每个开口130a中。注入的熔融焊料在每个开口130a中固化。填充头包括熔融焊料的容器和熔融焊料通过其注入的槽。焊料帽124可以具有凸形顶表面。
如图3C所示,凸起形成工艺还可包括从衬底110剥离抗蚀剂层130的步骤,从而在衬底110上留下凸起120。
如图3D所示,凸起工艺还可以包括去除从凸起120暴露的金属粘合材料128的第二部分128b的步骤。金属粘合材料128的去除可以通过包括湿法或干法蚀刻的任何标准方法来完成。
图3D的凸起结构100可用作本发明的实施例。当衬底110是晶片时,在衬底110被分成多个芯片之后,凸起结构100可用于倒装芯片接合。
本发明的凸起形成工艺使得能够在衬底110上制造包括凸起120的组的凸起结构,其中,即使衬垫112由与用于烧结的导电颗粒(即,所述实施例中的Cu)不同的导电材料(即,所述实施例中的Al)制成,通过烧结导电膏糊132制成的凸起120也紧密地接合到衬底110的衬垫112。通常,半导体器件包括在最外层的Al衬垫。因此,可以制造紧密结合到衬垫112的烧结凸起基底122以用于实际使用。
此外,由于凸起基底122通过烧结导电颗粒132来制造,而焊料帽124通过注入熔融焊料来制造,所以不需要电镀和无电镀工艺来制造凸起的主结构,从而避免了昂贵的柱和焊料帽制造工艺、昂贵的设备以及电镀工艺的复杂管理。
在上述实施例中,在抗蚀剂剥离之后进行额外金属粘合材料的去除。然而,在其它实施例中,可以省略金属粘合材料的去除。
在下文中,参考一系列图4A-4D和图5A-5D,描述根据本发明的另一实施例的改进的凸起形成工艺,其中省略了金属粘合材料的去除。图4A-4D和图5A-5D示出了在改进的凸起形成工艺的每个步骤中获得的结构的截面图。
如图4A所示,凸起形成工艺可以包括制备其上形成有衬垫112的组和钝化层114的衬底110的步骤。如图2B所示,凸起形成工艺还可包括在衬底110的表面110a上施加抗蚀剂层130的步骤。
如图2C所示,凸起工艺还可以包括图案化抗蚀剂层130以具有与相应衬垫112对准的开口130a的组的步骤。开口130a暴露衬垫112的表面。用光掩模131曝光光致抗蚀剂材料并显影,以在与衬垫112对准的位置处打开开口130a。当衬垫112由诸如Al的易于氧化的金属形成时,凸起形成工艺还可以包括从衬垫112去除表面氧化物的步骤。
如图4D所示,凸起形成工艺可以包括在衬垫112的表面和抗蚀剂层130的顶表面上沉积金属粘合材料128的步骤。沉积金属粘合材料128以便符合抗蚀剂层130的轮廓。在该实施例中,金属粘合材料从由Cu、Ni、Au及其组合所组成的组中选择。在特定实施例中,金属粘合层126是Cu、Au和/或Ni的层或叠层。
与上述实施例类似,当衬垫112由容易且持久氧化的金属(例如Al)形成时,优选采用反溅射和金属粘合材料的溅射的组合。
如图5A所示,凸起形成工艺可以包括将导电膏糊132填充到抗蚀剂层130的开口130A中的步骤。如图5B所示,凸起形成工艺可以包括烧结导电膏糊132的步骤。填充在开口130a中的导电膏糊132被烧结以在每个衬垫112上形成凸起基底122。在烧结工艺中,导电膏糊132收缩,使得凸起基底122被形成以覆盖开口130a的侧壁以及衬垫112的表面,其中两表面现在被金属粘合材料128所覆盖,如图5B所示。
如图5C所示,凸起形成工艺可包括将焊料填充到凸起基底122上方的每个开口130a中的剩余空间130b中的步骤。在所述实施例中,将熔融焊料注入抗蚀剂层130的每个开口130a中,以在每个凸起基底122上形成焊料帽124。熔融焊料的注入例如可以通过IMS工艺来完成。在本实施例中,在IMS工艺中,沉积于抗蚀剂层130顶表面的金属粘合材料128会溶解于熔融焊料中,因为金属粘合材料128并不包括任何不溶于熔融焊料的金属,例如Ti。在IMS工艺之后,沉积在抗蚀剂层130的开口130a的侧壁上的金属粘合材料128的部分(称为侧壁金属129)可保留。在本实施例中,侧壁金属129围绕凸起基底122,并覆盖凸起基底122的侧表面。侧壁金属129可以用作防止由于离子迁移引起的凸起之间的短路的侧壁阻挡层(例如,Ni)。
如图5D所示,凸起形成工艺还可包括从衬底110剥离抗蚀剂层130的步骤,从而在衬底110上留下凸起120。省略了在图2A-2E和图3A-3D所示的工艺中执行的去除金属粘合材料128的步骤。
注意,如果采用非剥离类型的抗蚀剂来形成抗蚀剂层130,则可以省略剥离步骤。因此,图5C所示的结构也可用于随后的倒装芯片接合工艺,而无需去除抗蚀剂层130。
在图2A-2E和图3A-3D所示的实施例中,由于引入了金属粘合材料的去除,因此即使材料不溶于诸如熔融焊料的焊料材料,其也具有能够采用诸如Ti阻挡层的其它功能材料作为金属粘合材料的优点。另一方面,在图4A-4D和图5A-5D所示的实施例中,当不使用不溶于熔融焊料的材料(如Ti)时,可以省略金属粘合材料的去除,同时充分去除额外的金属粘合材料。由于在抗蚀剂剥离之后去除抗蚀剂层下面的金属层的工艺被消除,所以优选地防止了在凸起的根部处的底切。还可以降低相关的工艺成本。在焊料材料的填充过程中,Cu、Ni和Au将容易地溶解到诸如熔融焊料的焊料材料中。
在下文中,参考一系列图6A-6C,描述根据本发明的另一实施例的替代凸起形成工艺。图6A-6C示出了在替代的凸起形成工艺的每个步骤获得的结构的截面图。
注意,该凸起形成工艺还包括与上述实施例类似的图4A-4D和图5A中描述的步骤。因此,将在图5A的步骤完成之后进行描述。
如图6A所示,凸起形成工艺可以包括烧结导电膏糊132的步骤。如图6B所示,凸起工艺可包括将焊料填充到凸起基底122上方的每个开口130a的剩余空间130b中以在每个凸起基底122上形成焊料帽124的步骤。在此实施例中,即使在IMS工艺之后,沉积在抗蚀剂层130的顶表面上的金属粘合材料128仍保留。
如图6C所示,凸起形成工艺可以包括从衬底110剥离抗蚀剂层130的步骤。在该步骤中,当抗蚀剂层130被洗掉时,抗蚀剂层130的顶表面上的金属粘合材料被剥离并与下面的抗蚀剂层130一起被清洗。省略了去除金属粘合材料128的单独步骤。在本实施例中,金属粘合材料128是选自由Cu、Ti、Ni、Au及其组合所组成的组。
在图4A-4D、图5A和图6A-6C所示的实施例中,与图4A-4D和图5A-5D所示的实施例类似,可以省略金属粘合材料的去除而不管金属粘合材料的成分。因此,优选地防止了在凸块的根部的底切。还可以降低相关的工艺成本。因此,允许我们采用其它功能材料如Ti阻挡层作为金属粘合材料。此外,在本实施例中,与模制层的轮廓一致的金属粘合材料可以用作防止由于离子迁移导致的凸起之间的短路的侧壁阻挡物。
在下文中,参考一系列图7A-7D,将描述根据本发明另一实施例的另一替代凸起形成工艺。图7A-7D示出了在凸起形成工艺的每个步骤中获得的结构的截面图。
注意,该凸起形成工艺还包括与上述实施例类似的图4A-4D和图5A中描述的步骤。因此,将在图5A的步骤完成之后进行描述。
如图7A所示,与上述实施例类似,凸起形成工艺可以包括烧结导电膏糊132以在每个衬垫112上形成凸起基底122的步骤。如图7B所示,凸起形成工艺可以包括去除沉积在抗蚀剂层130的顶表面上的金属粘合材料128的步骤。金属粘合材料128的去除可以通过选自下来的组的技术来完成:化学机械抛光(CMP)、机械抛光、飞切和化学蚀刻。
如图7C所示,凸起形成工艺可包括将焊料填充到每个开口130a中的剩余空间130b中以在每个凸起基底122上形成焊料帽124的步骤。如图7D所示,凸起形成工艺还可以包括从衬底110剥离抗蚀剂层130的步骤。在本实施例中,金属粘着材料128选自由Cu、Ti、Ni、Au及其组合所组成的组。
在图4A-4D、图5A和图7A-7D所示的实施例中,即使在抗蚀剂剥离之前执行额外金属粘合材料的去除工艺,然而,在抗蚀剂剥离之后的金属层的去除工艺被消除,该去除工艺将在凸状根部引起底切。它还允许我们采用其它功能材料如Ti阻挡层作为金属粘合材料。此外,在本实施例中,与模制层的轮廓一致的金属粘合材料可以用作防止由于离子迁移导致的凸起之间的短路的侧壁阻挡物。
在下文中,参照图8A和8B,描述根据本发明示例性实施例的电子器件和用于制造该电子器件的倒装芯片结合工艺。图8A和8B示出了在倒装结合工艺的每个步骤中获得的结构的横截面图。
如图8A所示,倒装芯片工艺可以包括制备凸起的半导体芯片310的步骤,该芯片包括在其有源(active)表面上形成的凸起320的组。倒装芯片工艺还可以包括制备有机衬底350的步骤,该有机衬底包括和形成在其表面上的阻焊层354和接触衬垫352的组。倒装芯片工艺还可以包括在有机衬底350的表面上施加底部填充剂356的步骤。
在该步骤中制备的凸起化半导体芯片310通过前述凸起形成工艺中的任何一种来制造,如果凸起工艺在晶片级执行,则随后通过切割工艺来制造。如已经参照图1A和1B描述的,每个凸起320包括形成在衬垫312上的金属粘合层326、经由金属粘合层326形成在衬垫312上的凸起基底322和形成在凸起基底322上的焊料帽324。
如图8B所示,倒装芯片工艺可以包括将凸起的半导体芯片310安装到有机衬底350上,使得芯片侧的凸起320分别与衬底侧的接触衬垫352接触的步骤。半导体芯片310被翻转,使得其有源表面朝下,并且被设置成使得凸起320与有机衬底350上的相应衬垫352对准。如图8B所示,倒装芯片工艺还可以包括将凸起320接合到衬垫352以获得倒装接头(joint)360的步骤。可以根据接头的期望尺寸和间距的方式来进行安装和回流方法以及热压缩方法中的适当的一个。倒装芯片工艺还可以包括固化底部填充356以将半导体芯片310刚性地固定到有机衬底350的步骤。
通过执行安装凸起的半导体芯片310的步骤和将凸起320键合到衬垫352的步骤,凸起的半导体芯片310互连到包括外部电路的有机衬底350。
通过上述倒装芯片接合工艺制造的电子器件表现出良好的耐久性,因为即使衬垫312由不同于用于形成凸起的导电颗粒的导电材料制成,通过烧结导电颗粒而制成的凸起320也紧密地接合到衬垫312。
在下文中,参考一系列图9A-9E、图10A-10E、图11A-11D、图12A-12D和图13A-13C,将描述各种相关的凸起形成工艺。
图9A-9E示出了在包括柱和焊料帽的电镀的相关凸起形成工艺的每个步骤获得的结构的截面图。
如图9A所示,在准备好的晶片510的表面上形成诸如Ti/Cu层的晶种层516。如图9B所示,在晶片510上构图具有孔530a的组的抗蚀剂掩模530。如图9C所示,在孔530a中的晶种层516上电镀Cu,以形成直到孔530a的中间的Cu柱。还如图9C所示,通过在抗蚀剂掩模530的孔530b的上边界上电镀焊料材料,将焊料层524沉积在Cu柱522上。如图9D所示,从晶片510剥离抗蚀剂掩模530,并蚀刻晶种层516。如图9E所示,焊料层524然后经受使用焊剂(flux)的回流以在晶片810上形成焊料覆盖的凸起520。
尽管图9A-9E所示的相关凸起形成工艺可以制造Cu柱凸起,然而,难以以高自由度调整电镀焊料的成分。已知通过电镀方法可以稳定地制造纯Sn或二元焊料组合物。而且,对于柱和焊料帽两者,都需要昂贵的电镀、昂贵的设备和电镀工艺的复杂管理。而且,在抗蚀剂剥离之后去除晶种层516将在凸起520的根部引起底切。
图10A-10E示出了在包括柱的电镀和焊料帽的IMS的其它相关凸起形成工艺的每个步骤获得的结构的截面图。
如图10A所示,在晶片610的表面上形成诸如Ti/Cu层的晶种层616。如图10B所示,在晶片610上构图具有孔630a的组的抗蚀剂掩模630。如图10C所示,在孔630a中的晶种层616上电镀Cu,以形成直到孔630a的中间的Cu柱。如图10D所示,通过IMS工艺用焊接材料填充抗蚀剂掩模630中的孔630a的剩余空间,以在Cu柱622上形成焊料帽624。如图10E所示,从晶片610剥离抗蚀剂掩模630,并蚀刻晶种层616。
尽管在图10A-10E所示的凸起形成工艺中可以省略昂贵的焊料电镀,但是仍然需要昂贵的铜柱电镀、昂贵的设备和复杂的电镀工艺管理。而且,在抗蚀剂剥离之后去除晶种层616将导致在凸起620的根部处的底切。
图11A-11D示出了在包括柱的无电镀和焊料帽的IMS的其它相关凸起形成工艺的每个步骤获得的结构的截面图。
如图11A所示,在包括衬垫712的组和钝化层714的晶片710上构图具有孔730a的组的抗蚀剂掩模730。如图11B所示,通过无电镀将Ni沉积在孔730a中的衬垫712上,以形成直到孔730a中间的Ni柱722,并且将Au金属层728沉积在Ni柱722上。如图11C所示,通过IMS工艺用焊接材料填充抗蚀剂掩模730中的孔730a的剩余空间,以在Ni柱722上形成焊料帽724。如图11D所示,从晶片710剥离抗蚀剂掩模730,在晶片710上留下包括Ni柱722和焊料帽724的Ni柱凸块720的组。
尽管可以省略在抗蚀剂剥离之后去除晶种层,但是仍然需要Ni柱的昂贵的无电镀、昂贵的设备和复杂的电镀工艺管理。
图12A-12D和图13A-13C示出了在不使用金属粘合层的情况下基于导电膏糊烧结的相关凸起工艺的每个步骤获得的结构的横截面图。
如图12A所示,在相关的凸起形成工艺中,提供包括焊垫812的组及钝化层814的晶片810。如图12B所示,然后,在晶片810的表面上形成抗蚀剂掩模830。如图12C所示,使用光掩模831将抗蚀剂掩模830图案化以具有孔830a的组。每个孔830a与对应的一个垫812相对准。
如图12D所示,将Cu膏糊832填充到抗蚀剂掩模830的孔830a中,直到孔830a的上边界。如图13A所示,填充在孔830a中的Cu膏糊832固化,以形成作为Cu颗粒的烧结体的杯形柱822。注意,由于该工艺采用烧结工艺来制造铜柱,因此电镀铜所需的晶种层是不必要的。相反,从成本的观点来看,可以避免包括晶种层沉积和抗蚀剂剥离之后的晶种层去除的这些不必要的步骤。此外,在抗蚀剂剥离之后的晶种层去除可能在凸状根部引起底切。
如图13B所示,然后,通过IMS工艺用焊接材料填充杯状支柱822上方的抗蚀剂掩模830中的孔830a的剩余空间,以在杯状支柱822上形成焊料帽824。如图13C所示,从晶片810上剥离抗蚀剂掩模830,在晶片810上留下Cu柱凸起820的组,每个Cu柱凸起包括杯形柱822和焊料帽824。
通过图12A-12E和图13A-13C所示的凸起工艺,可以避免对两个铜柱焊料帽的昂贵电镀、昂贵的设备和电镀工艺的复杂管理。
然而,该工艺限于衬垫812和柱822由相同材料制成的情况,尤其是铜。本发明人等进行了深入研究,结果发现,即使在通过反溅射除去自然氧化膜之后,在大气压下,也难以将导电膏糊的烧结体接合在由与导电膏糊不同的导电材料构成的衬垫上,例如难以将烧结铜接合在Al衬垫上。烧结的高温条件预期有助于增强烧结的柱和衬垫之间的结合。然而,半导体器件通常在高于典型回流工艺的温度的这种高温条件下退化,例如>300摄氏度。
与图12A-12D和图13A-13C中所示的上述相关凸起形成工艺相比,根据本发明的一个或多个实施例的技术使得能够在不使用高温条件的情况下增强凸起基底和衬垫之间的接合。即使采用不同于导电颗粒的导电材料作为衬垫材料,在衬垫112和导电膏糊132(或烧结凸起基底122)之间制造的金属粘合层或UBM层也保持良好的接合性。因此,可以防止由于凸起形成工艺而导致的半导体器件的劣化。
同样与图9A-9E、图10A-10E、图11A-11D、图中所示的前述相关凸起形成工艺相反,根据本发明的一个或多个实施例的凸起形成工艺消除了凸起基底和焊料帽的昂贵电镀的必要性以及电镀工艺的复杂管理,从而降低了凸起的生产成本。
如上所述,根据本发明的一个或多个实施例,提供了一种能够制造包括形成在衬底上的凸起的组的凸起结构的新颖凸起形成技术,其中通过烧结导电颗粒制成的凸起紧密接合到由不同于导电颗粒的导电材料制成的衬垫。
本文所用的术语仅是为了描述特定实施例的目的,而不是要限制本发明。如本文所用,单数形式“一”、“一个”和“该”旨在也包括复数形式,除非上下文另有明确指示。还应当理解,当在本说明书中使用时,术语“包括”和/或“包含”指定所述特征、步骤、层、元件和/或部件的存在,但是不排除一个或多个其它特征、步骤、层、元件、部件和/或其组合的存在或添加。
如果存在,下面的权利要求中的所有装置或步骤加功能元件的对应结构、材料、动作和等同物旨在包括用于与具体要求保护的其它要求保护的元件组合执行功能的任何结构、材料或动作。为了说明和描述的目的,已经给出了本发明的一个或多个方面的描述,但是不是旨在穷举或将本发明限制为所公开的形式。
在不背离所描述的实施例的范围的情况下,许多修改和变化对于本领域的普通技术人员将是显而易见的。选择本文所使用的术语以最好地解释实施例的原理、实际应用或对市场上存在的技术改进,或使本领域的其他普通技术人员能够理解本文所公开的实施例。
Claims (21)
1.一种制造凸起结构的方法,所述方法包括:
制备包括形成在其表面上的衬垫的组的衬底,所述衬垫包括第一导电材料;
在所述衬垫中的每一个上涂覆金属粘合层;以及
通过使用模制层烧结导电颗粒来在所述衬垫中的每一个上形成凸起,所述导电颗粒包括与所述第一导电材料不同的第二导电材料。
2.根据权利要求1所述的方法,其中,所述模制层具有开口的组,所述开口中的每一个与所述衬垫中的一个相对准,并且在所述衬垫中的每一个上形成所述凸起包括:
在所述衬底上设置所述模具层;
将导电颗粒填充到所述模制层的所述开口中,填充在所述模制层的所述开口中的所述导电颗粒被烧结,以在所述衬垫中的每一个上供给凸起基底;以及
将焊料材料填入所述凸起基底上方的所述模制层的所述开口钟的每一个中的剩余空间,以在每个凸起基底上形成焊料帽。
3.根据权利要求1所述的方法,其中所述第一导电材料包括Al,并且所述第二导电材料包括Cu。
4.根据权利要求2所述的方法,其中,所述导电颗粒以膏糊的形式而提供,并且形成在所述衬垫中的每一个上的所述凸起基底具有与所述模制层的所述开口的轮廓相一致的杯的形状并且具有通过所述金属粘合层而结合到所述衬垫的底部。
5.根据权利要求2所述的方法,其中所述方法进一步包括:
在所述衬底的所述表面上施加抗蚀剂层;
图案化所述抗蚀剂层以制造所述模制层;以及
在所述衬垫和所述模制层上沉积金属粘合材料,以便符合所述模制层的轮廓并且提供涂覆在所述衬垫中的每一个上的所述金属粘合层。
6.根据权利要求5所述的方法,其中填充所述焊料材料包括:
将沉积在所述模制层的顶表面上的金属粘合材料溶解到焊料材料中。
7.根据权利要求6所述的方法,其中所述金属粘合材料选自由Cu、Ni、Au及其任意组合组成的组。
8.根据权利要求5所述的方法,其中所述方法进一步包括:
将所述模制层从所述衬底上剥离,以便将所述模制层清洗掉,其中在所述模制层的顶表面上的金属粘合材料连同所述模层一起被剥离并被清洗。
9.根据权利要求5所述的方法,其中所述方法进一步包括:
通过选自化学机械抛光(CMP)、机械抛光、飞切和化学蚀刻组成的组的技术,去除沉积在所述模制层的顶表面上的金属粘合材料。
10.根据权利要求2所述的方法,其中所述方法进一步包括:
在所述衬底的所述表面上沉积金属粘合材料,以具有对应于涂覆在所述衬垫中的每一个上的所述金属粘合层的第一部份以及形成在所述焊垫的***区域上的第二部份,
在所述金属粘合材料上施加抗蚀剂层;
图案化所述抗蚀剂层以制造所述模制层;
将所述模制层从所述衬底上剥离,以使所述凸起留于所述衬底上,每一个凸起包括所述焊料帽及形成在所述衬垫上的所述凸起基座;以及
移除从所述凸起暴露的所述金属粘合材料的所述第二部分。
11.根据权利要求10所述的方法,其中所述金属粘合材料选自由Cu、Ti、Ni、Au及其任意组合组成的组。
12.根据权利要求2所述的方法,其中填充所述焊料材料包括:
将熔融焊料注入所述模制层的所述开口中的每一个中。
13.根据权利要求1所述的方法,其中所述方法进一步包括:
在涂覆所述金属粘合层之前,通过反溅射来从所述衬垫去除表面氧化物,所述金属粘合层被通过溅射而涂覆在所述衬垫中的每一个上。
14.根据权利要求1所述的方法,其中所述衬底包括半导体器件,所述衬垫的组至少形成在所述半导体器件的有源表面上,并且所述方法还包括:
利用所述凸起将所述半导体器件互连到外部电路,所述方法是电子器件的制造方法。
15.一种凸起结构,包括:
衬底,所述衬底包括形成在其表面上的衬垫的组,其中所述衬垫包括第一导电材料;以及
凸起的组,所述凸起中的每一个形成在所述衬垫中的一个上,其中,所述凸起中的每一个包括形成在所述衬垫上的金属粘合层和形成在所述金属粘合层上的凸起基底,并且所述凸起基底为包括与所述第一导电材料不同的第二导电材料的导电颗粒的烧结体。
16.根据权利要求15所述的凸起结构,其中所述凸起中的每一个进一步包含形成在所述凸起基底上的焊料帽,所述凸起基底具有杯状形状,所述杯状物具有经由所述金属粘合层而接合到所述衬垫的底部,并且所述杯状物填充有所述焊料帽的焊料材料。
17.根据权利要求15所述的凸起结构,其中所述金属粘合层覆盖所述凸起底部的侧表面作为侧壁阻挡物。
18.根据权利要求15所述的凸起结构,其中所述第一导电材料包括Al,所述第二导电材料包括Cu,并且所述金属粘合层包括选自由Cu、Ti、Ni、Au及其组合组成的组的材料。
19.一种电子设备,包括:具有根据权利要求15至18中任一项所述的凸起结构的半导体器件;以及通过所述凸起的组而与所述衬底互连的电路。
20.根据权利要求19所述的电子装置,其中所述凸起中的每一个进一步包含将每一凸起基底连接到所述电路的端子触点的焊料接头,所述凸起基底具有杯状形状,所述杯状物形状具有经由所述金属粘合层而接合到所述衬垫的底部,并且所述杯状物填充有所述焊料帽的焊料材料。
21.一种制造电子器件的方法,所述方法包括:
制备凸起化半导体器件,制备所述凸起化半导体器件包括根据权利要求1至14中任一项所述的制造凸起化结构的方法;以及
通过所述凸起的组将所述凸起化半导体器件互连到外部电路。
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US20210125950A1 (en) | 2021-04-29 |
DE112020004228T5 (de) | 2022-06-15 |
JP2022553666A (ja) | 2022-12-26 |
US11329018B2 (en) | 2022-05-10 |
WO2021079209A1 (en) | 2021-04-29 |
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