CN114567292A

CN114567292A - Static latch and processor and computing device including the same

Info

Publication number: CN114567292A
Application number: CN202210455592.0A
Authority: CN
Inventors: 田文博; 龚川; 范志军; 杨作兴; 郭海丰
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2022-04-28
Filing date: 2022-04-28
Publication date: 2022-05-31
Anticipated expiration: 2042-04-28
Also published as: CN114567292B

Abstract

The present disclosure relates to static latches and processors and computing devices including static latches. There is provided a static latch comprising: an input stage for receiving a latch input (D); an output stage for outputting a latch output (Q); an intermediate node (B) arranged between an output of the input stage and an input of the output stage, wherein the output stage receives as input a signal at the intermediate node; and a feedback stage receiving the latch output and providing feedback to the intermediate node, wherein the feedback stage and input stage have a logic high state, a logic low state, and a high impedance state.

Description

Static latch and processor and computing device including the same

Technical Field

The present disclosure relates to static latches and processors and computing devices including static latches.

Background

In recent years, digital money has received increasing attention. There is a need in the relevant art for improved processors and computing devices for digital currency.

Processors for digital currency require a large number of repetitive logic computations during operation, which requires a large number of latches for data storage. Therefore, the performance of the latch will directly affect the performance of the processor, including chip area, power consumption, operation speed, and the like.

Compared with a static latch, the dynamic latch has the advantages that a positive feedback circuit for keeping the working state is reduced, and the circuit structure is greatly simplified, so that the area of a chip is reduced, and the power consumption is reduced. However, since there is a node in the dynamic latch where the potential floats (floating) for a portion of the time, the parasitic capacitance at that node needs to maintain the correct voltage state during that time period.

To mitigate or avoid device leakage from affecting the voltage at the node, the circuit devices connected to the node need to use low leakage devices. Low leakage devices are typically high threshold devices and are slower than low threshold devices, which also affects the speed of the dynamic latch. At the same time, the dynamic latch needs to operate at a higher frequency to prevent functional errors. While in certain states of the processor (e.g., sleep or idle states), the dynamic latch may operate at a relatively low frequency, in which case the prior art dynamic latch may experience functional errors.

To address one or more of the above issues, the present invention provides a static latch and a processor and a computing device including the same.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a static latch including: an input stage for receiving a latch input (D); an output stage for outputting a latch output (Q); an intermediate node (B) arranged between an output of the input stage and an input of the output stage, wherein the output stage receives as input a signal at the intermediate node; and a feedback stage receiving the latch output and providing feedback to the intermediate node, wherein the feedback stage and input stage have a logic high state, a logic low state, and a high impedance state.

In some embodiments, the feedback stage comprises a tri-state gate comprising: first to fourth transistors connected in series, the first and second transistors being transistors of a first conductivity type, the third and fourth transistors being transistors of a second conductivity type, the second conductivity type being different from the first conductivity type, a control terminal of one of the first and second transistors being connected to the latch output, a control terminal of the other of the first and second transistors being connected to a first clock signal, a control terminal of one of the third and fourth transistors being connected to the latch output, a control terminal of the other of the third and fourth transistors being connected to a second clock signal, wherein the second clock signal is an inverse of the first clock signal, and a node at which the second and third transistors are connected to each other is connected to the intermediate node.

In some embodiments, the feedback stage comprises an inverter and a transmission gate connected in series, an input of the inverter being connected to the latch output, an output of the inverter being connected to an input of the transmission gate, an output of the transmission gate being connected to the intermediate node, two control terminals of the transmission gate receiving a first clock signal and a second clock signal, respectively, wherein the second clock signal is the inverse of the first clock signal.

In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. When the first clock signal is high and the second clock signal is low, the feedback stage is turned off, thereby assuming a high impedance state. The feedback stage provides feedback to the intermediate node according to the latch output when the first clock signal is low and the second clock signal is high.

In some embodiments, the input stage is tristate logic, the tristate logic receiving the latch input and the first and second clock signals, the tristate logic assuming a logic high state, a logic low state and a high impedance state in dependence on the input and the first and second clock signals.

In some embodiments, the tristate logic comprises an inverter and a transmission gate connected in series, the inverter receiving the latch input, the output of the inverter being connected to one end of the transmission gate, the other end of the transmission gate being connected to the intermediate node, the control ends of the transmission gate receiving the first and second clock signals respectively.

In some embodiments, the tri-state logic comprises a tri-state gate comprising: fifth to eighth transistors connected in series, the fifth and sixth transistors being transistors of a first conductivity type, the seventh and eighth transistors being transistors of a second conductivity type, a control terminal of one of the fifth and sixth transistors being connected to the latch input, a control terminal of the other of the fifth and sixth transistors being connected to the second clock signal, a control terminal of one of the seventh and eighth transistors being connected to the latch input, a control terminal of the other of the seventh and eighth transistors being connected to the first clock signal, a node at which the sixth and seventh transistors are connected to each other being connected to the intermediate node.

In some embodiments, the transistors of the first conductivity type are PMOS transistors and the transistors of the second conductivity type are NMOS transistors. The input stage provides an output to the intermediate node according to the latch input when the first clock signal is high and the second clock signal is low. When the first clock signal is low and the second clock signal is high, the input stage is turned off, thereby assuming a high impedance state.

In some embodiments, the threshold values of the transistors in the static latch are substantially the same.

According to an aspect of the present disclosure, there is provided a processor including: at least one static latch, said static latch being a static latch according to any embodiment of the present disclosure.

In some embodiments, the at least one static latch comprises a plurality of static latches; and a clock circuit for providing a required clock signal to each of the plurality of static latches.

In some embodiments, the clock circuit includes a first inverter and a second inverter connected in series, the first inverter receiving a clock signal and outputting a first clock signal, the second inverter receiving the first clock signal and outputting a second clock signal, the first clock signal and the second clock signal being provided to each of the plurality of static latches.

According to some aspects of the present disclosure, there is provided a computing device comprising a processor according to any embodiment of the present disclosure.

In some embodiments, the computing device is a computing device for digital currency.

The static latch according to the embodiment of the disclosure can stably maintain the potential of the floating node, and can reduce the power consumption of the static latch and the complexity of the preparation process. The static latch according to the embodiment of the disclosure can work at a lower frequency and also can work at a higher frequency, thereby providing flexibility for processor design and reducing power consumption.

Processors and computing devices according to the present disclosure may be used for correlation calculations for digital currencies (e.g., bitcoin, lexel, ethernet, and other digital currencies).

Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic block diagram of a static latch according to one embodiment of the present disclosure;

FIG. 2 shows a circuit diagram of a static latch according to one embodiment of the present disclosure;

FIG. 3A shows a schematic circuit diagram of a static latch according to another embodiment of the present disclosure;

FIG. 3B shows a schematic circuit diagram of a static latch according to another embodiment of the present disclosure;

FIG. 4 shows a schematic block diagram of a processor including a clock circuit and a static latch, according to one embodiment of the present disclosure;

FIG. 5 shows a schematic block diagram of a clock circuit according to one embodiment of the present disclosure;

FIG. 6 shows a schematic block diagram of a processor including a clock circuit and a plurality of static latches, according to one embodiment of the present disclosure; and

FIG. 7 shows a timing diagram of schematic signal waveforms of a static latch according to one embodiment of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of parts and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise. Additionally, techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification as appropriate.

It should be appreciated that the following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the disclosure, its application, or uses. It should also be understood that any implementation exemplarily described herein does not necessarily represent that it is preferred or advantageous over other implementations. This disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.

In this context, "tri-state logic" means a logic circuit whose output assumes three states depending on the input and the control signal: a logic high state, a logic low state, and a high impedance state. The control signal may be, for example, a clock signal.

In this context, "tri-state gate" means a "minimum level" logic gate (or referred to as a logic gate circuit) whose output can achieve the three states (logic high state, logic low state, and high resistance state). Here, "logic gate of the minimum hierarchy" means that an individual logic gate or logic unit as a part thereof cannot be separated from the logic gate (tri-state gate).

In addition, certain terminology may also be used in the following description for the purpose of reference only, and thus is not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

It will be further understood that the terms "comprises/comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

FIG. 1 shows a schematic block diagram of a static latch according to one embodiment of the present disclosure. As shown IN fig. 1, a static latch 100 according to an embodiment of the present disclosure includes an input stage 103 for receiving an Input (IN), and an output stage 105 for outputting a latch Output (OUT).

The static latch 100 also has an intermediate node (B) disposed between the output of the input stage and the input of the output stage. In operation, the potential of the intermediate node B is floating.

In some embodiments, the intermediate node B may be directly connected to the output of the input stage, as shown in fig. 1.

The input of the output stage 105 receives a signal dependent on the potential of the intermediate node. Preferably, as shown in the embodiment shown in fig. 1, the input of the output stage 105 is directly connected to the intermediate node B.

The static latch 100 further comprises a feedback stage 107, the feedback stage 107 receiving the latch output OUT and providing feedback to said intermediate node B. According to an embodiment of the present disclosure, the feedback stage 107 has a logic high state, a logic low state, and a high impedance state.

In addition, one or more of the components of the static latch 100 may receive a respective clock signal. As shown in fig. 1, the input stage 103 and the feedback stage 107 each receive a respective clock. Here, it should be understood that the clock CKs is merely exemplary and does not mean that the input stage 103, the feedback stage 107, and other components (if any) and the like all receive the same clock signal. Furthermore, although in the embodiment shown in fig. 1, the output stage 105 is shown as not receiving a clock signal, the disclosure is not limited thereto.

FIG. 2 shows a circuit diagram of a static latch according to one embodiment of the present disclosure. As shown in fig. 2, a static latch 200 according to an embodiment of the present disclosure includes an input stage 203, an output stage 205, an intermediate node B, and a feedback stage 207. An intermediate node B is arranged between the output of the input stage 203 and the input of the output stage 205. In operation, the potential at the intermediate node B is floating.

Input stage 203 receives input D and provides an output to an intermediate node B. Here, input stage 203 receives an input D (also referred to as a latch input) and provides an output to an intermediate node B. Input stage 203 also receives clock signals CLKP and CLKN. Preferably, the input stage 203 is implemented as tristate logic which assumes a logic high state, a logic low state and a high impedance state depending on the input D and the first clock signal (CLKP or CLKN) and the second clock signal (CLKN or CLKP).

In a preferred embodiment, as shown in fig. 2, the input stage 203 is implemented as a CMOS tri-state gate comprising four transistors. The CMOS tri-state gate includes:

transistors

531, 533, 535, and 537 connected in series, wherein

transistors

531 and 533 are PMOS transistors and

transistors

535 and 537 are NMOS transistors.

Transistors

531 and 533 are connected in series with each other. One end (here, source) of the transistor 533 is connected to one end (here, drain) of the transistor 531. A control terminal (gate) of one of the

transistors

531 and 533 is connected to the latch input D, and a control terminal (gate) of the other of the

transistors

531 and 533 is connected to the clock signal CLKN. Preferably, as shown in fig. 2, the gate of transistor 531 is connected to input D and the gate of transistor 533 is connected to clock signal CLKN. One end (here, a source) of the transistor 531 is connected to the power supply voltage VDD.

The drain of the PMOS transistor 533 and the drain of the NMOS transistor 535 are connected to each other and to the intermediate

node B. Transistors

535 and 537 are connected in series with each other. One terminal (here, a source) of the transistor 535 is connected to one terminal (here, a drain) of the transistor 537. A control terminal (gate) of one of

transistors

535 and 537 is connected to input D, while a control terminal (gate) of the other of

transistors

535 and 537 is connected to clock signal CLKP. Preferably, as shown in fig. 2, the gate of transistor 537 is connected to input D and the gate of transistor 535 is connected to the clock signal CLKP. The other end (here, the source) of the transistor 537 is connected to the ground GND.

Those skilled in the art will readily appreciate that there are many ways to implement the tristate logic of input stage 203 and is not limited to the manner shown in fig. 2. For example, the tristate logic may also be implemented to include an inverter and a transmission gate, as will be described later with reference to the illustrations of FIGS. 3A-3B. In addition, in other embodiments, the signals received by the gates of

transistors

531 and 533 may be swapped, and correspondingly, the signals received by the gates of

transistors

535 and 537 may also be swapped. That is, it may be configured that the gates of

transistors

531 and 537 are connected to clock signals CLKN and CLKP, respectively, and the gates of

transistors

533 and 535 are connected to input D.

The output stage 205 receives as input the signal (voltage) at node B and its output is the latch output Q. In the present embodiment, the output stage 205 is implemented as an inverter including

CMOS transistors

511 and 513 connected in series with each other. The transistor 511 is a PMOS transistor, and the transistor 513 is an NMOS transistor. The transistor 511 has a control terminal (gate) connected to the node B, a source connected to the power supply voltage VDD, a drain connected to the drain of the transistor 513, and an output Q. The gate of the transistor 513 is connected to node B, and its source is connected to ground GND. In this context, the output Q may be used to indicate the signal of the output, and may also be used to indicate the output terminal, depending on the context. Similarly, input D may be used to indicate the signal of the input, and may also be used to indicate the input terminal.

The feedback stage 207 receives the latch output Q as an input and provides feedback to the intermediate node B. Here, the feedback stage 207 is implemented as tri-state logic. In the embodiment shown in fig. 2, the feedback stage 207 is implemented as a tri-state gate having a logic high state, a logic low state and a high impedance state.

Specifically, as shown in fig. 2, the tri-state gates of the feedback stage 207 are implemented by CMOS transistors. The tri-state gate includes:

transistors

521 and 527 connected in series in sequence. The

transistors

521, 523, 525, and 527 are referred to herein as first to fourth transistors, respectively, and the

aforementioned transistors

531, 533, 535, and 537 are referred to as fifth to eighth transistors, respectively. The first and

second transistors

521 and 523 are PMOS transistors, and the third and

fourth transistors

525 and 527 are NMOS transistors.

The first and

second transistors

521 and 523 are connected in series with each other. One end (here, drain) of the transistor 521 is connected to one end (here, source) of the transistor 523. A control terminal (gate) of one of the first and

second transistors

521 and 523 is connected to the latch output Q, and a control terminal of the other of the first and

second transistors

521 and 523 is connected to the clock signal CLKP. Here, in the embodiment shown in fig. 2, the gate of the first transistor 521 is connected to the latch output Q, and the gate of the second transistor 523 is connected to the clock signal CLKP. The other end (here, source) of the transistor 521 is connected to the power supply voltage VDD.

The drain of the PMOS transistor 523 and the drain of the NMOS transistor 525 are connected to each other and to the intermediate node B. The third and

fourth transistors

525 and 527 are connected in series with each other. One end (here, a source) of the transistor 525 is connected to one end (here, a drain) of the transistor 527. A control terminal (gate) of one of the third and

fourth transistors

525 and 527 is connected to the latch output Q, and a control terminal (gate) of the other of the third and

fourth transistors

525 and 527 is connected to the clock signal CLKN. In the embodiment shown in fig. 2, the gate of the fourth transistor 527 is connected to the latch output Q and the gate of the third transistor 525 is connected to the clock signal CLKN. Clock signal CLKN is the inverse of clock signal CLKP. The other end (here, source) of the transistor 527 is connected to the ground GND.

A node at which the second and

third transistors

523 and 525 are connected to each other is connected to the intermediate node B. Here, the drain of the transistor 523 is connected to the drain of the transistor 525 and to the intermediate node B.

It should be appreciated that although in the embodiment shown in fig. 2, the feedback stage 207 is implemented as a tri-state gate, in other embodiments the feedback stage 207 may be implemented in a variety of other ways.

The timing of a static latch according to an embodiment of the present disclosure is described below in conjunction with fig. 7 and 2. FIG. 7 shows a timing diagram of schematic signal waveforms of a static latch according to an embodiment of the disclosure. The clock signals CLKN and CLKP may be obtained from the clock signal CK in a manner such as that shown in fig. 5 (which will be described in more detail later). The clock signal CLKP and the clock signal CLKN are inverted with respect to each other, one of which may substantially coincide with the clock signal CK, without regard for delay. For example, here, the clock signal CLKP substantially coincides with the clock signal CK, and the clock signal CLKN is the inverse of the clock signal CLKP (or the clock signal CK).

Two full clock cycles T1 and T2, a partial clock before T1, and at least a portion of cycle T3 are shown in FIG. 7. As shown in fig. 7, immediately before the start time T1 of the period of T1: clock signal CK is low, correspondingly clock signal CLKN is high, and clock signal CLKP is low; input D is high;

transistors

533 and 535 are off and tri-state gate 203 is off; b is high and the output Q is low. While

transistors

525 and 523 are turned on and tri-state gate 207 is turned on, thereby maintaining the signal at node B (hereinafter signal B) high.

As shown in fig. 7, at time t1, the clock signal CK changes from logic low to logic high. Accordingly, the clock signal CLKP goes high from low and the clock signal CLKN goes low from high. At this time, input D is high.

Since the clock signal CLKN is toggled low and the clock signal CLKP is toggled high and the input D is high,

transistors

533 and 535 conduct and signal B goes high to low. The output stage 205 is an inverter, so its output signal Q also goes from low to high. On the other hand, since the clock signal CLKN is low and the clock signal CLKP is high, the transistor 523 and the transistor 525 in the tri-state gate 207 are also turned off, so that the tri-state gate 207 is turned off in a high impedance state. B is low.

At time T2 within the first period T1 of the clock CK, the clock signals CLKN and CLKP are flipped high and low, respectively, and Q is high, so that

transistors

525 and 523 in tri-state gate 207 are turned on, maintaining signal B low. Thus, the potential at the intermediate node B is maintained at a desired logic low potential.

During the time period t2-t3, the clock CK is low and accordingly the clock signal CLKP is low and the clock signal CLKN is high. And the output Q is high. Thus, the feedback stage 207 is turned on, keeping the signal at node B low.

Thereafter, immediately before period T2, the D signal changes from high to low. Before time t3, clock signal CK is low, and correspondingly clock signal CLKN is high and clock signal CLKP is low, similar to before time t 1. At this time, input D is low.

Transistors

533 and 535 are off and tri-state gate 203 is off; b is low, output Q is high, and

transistors

525 and 523 are turned on, thereby maintaining signal B low.

In the period T2, at the time T3, the clock signal CLKP changes from low to high again, and the clock signal CLKN changes from high to low again. At this time, signal D is low. Accordingly, in the input stage 203, the

transistors

535 and 533 are turned on, and the signal B is inverted high. Accordingly, the transistor output Q flips low.

In the feedback stage 207, the

transistors

523 and 525 in the tri-state gate 207 are turned off due to the clock signals CLKP and CLKN being flipped high and low, respectively, so that the tri-state gate is turned off and is in a high impedance state. B remains high.

Similarly, in the period T2, the signals B and Q maintain their logic levels. At time t4, clock signals CLKn and CLKP flip accordingly, while signals B and Q maintain their logic levels. At this point, clock signals CLKN and CLKP are flipped high and low, respectively, so that

transistors

525 and 523 in tristate gate 207 are turned on and Q is low, thereby maintaining signal B high. In this manner, the potential at the intermediate node B is maintained at the desired logic high potential.

Before period T3, the D signal goes from low to high. The situation at time T5 is substantially the same as at time T1, while the situation at time T6 in period T3 is substantially the same as at time T2; and therefore will not be described in detail herein.

As such, according to the static latch of the embodiments of the present disclosure, the potential of the floating node (e.g., node B) can be stably maintained, and the power consumption of the static latch can be reduced. Also, since the potential of the floating node may be maintained, the use of high threshold devices (e.g., high threshold transistors) may be avoided, such that the transistors in the static latch may be configured to have substantially the same threshold. Thus, the complexity of the preparation process is reduced.

Here, those skilled in the art will appreciate that although the transistor devices in the static latch are designed to have the same threshold based, variations in the process fabrication may result in some deviation in the threshold of the actually fabricated device. Generally, in this context, substantially the same threshold may mean within ± 20%, more preferably within ± 15%, more preferably within ± 10%, more preferably within ± 5% of the design or target threshold.

In addition, according to the static latch of the embodiment of the present disclosure, as few transistors as possible can be employed. In computationally intensive processors (e.g., processors for digital currency), there may be a large number of static latches, so even a one transistor reduction in static latches is significant for reducing chip area and power consumption.

In addition, according to the static latch according to the embodiment of the present disclosure, since the potential of the floating node can be effectively maintained, a malfunction is not caused even when operating at a low frequency. The static latch according to embodiments of the present disclosure may also operate at higher frequencies, providing flexibility for processor design and reducing power consumption.

It should also be understood that although described in the above examples in terms of a high-level efficient embodiment, in other embodiments of the present disclosure, a low-level efficient implementation may be employed. In this case, the waveforms of the clock signals CLKN and CLKP will be inverted.

Fig. 3A shows a schematic circuit diagram of a static latch according to another embodiment of the present disclosure. The static latch 300A shown in fig. 3A differs from the static latch 200 shown in fig. 2 only in the input stage. In static latch 300A, the tristate logic of input stage 303 is implemented as a series connection of an inverter and a transmission gate.

As shown in fig. 3A, the

CMOS transistors

531A and 535A constitute an inverter, and the CMOS transistors 533A and 537A constitute a transfer gate. The input of the inverter is connected to input D, the output of the inverter is connected to the input of the transmission gate (node E), and the output of the transmission gate is connected to the intermediate node (node B). Two control terminals of the transmission gate (i.e., gates of CMOS transistors 533A and 537A) receive the clock signal CLKN and the clock signal CLKP, respectively. The clock signal CLKN and the clock signal CLKP are inverted, i.e., the clock signal CLKN and the clock signal CLKP are the opposite of each other.

The operation and logic level variations of input stage 303 are the same as input stage 203 shown in fig. 2, and therefore the operation and logic level variations described above with respect to input stage 203 may be equally applicable thereto. In addition, the remaining components of fig. 3A are the same as the corresponding components in fig. 2, and thus further detailed description thereof is omitted here.

Fig. 3B shows a schematic circuit diagram of a static latch according to another embodiment of the present disclosure. The static latch 300B shown in fig. 3B differs from the static latch 300A shown in fig. 3A only in the feedback stage. In static latch 300B, the tristate logic of feedback stage 307 is implemented as a series of inverters and transmission gates.

As shown in fig. 3B, the

CMOS transistors

521A and 527A constitute an inverter, and the CMOS transistors 523A and 525A constitute a transfer gate. The input of the inverter is connected to the latch output node (Q) and the output of the inverter is connected to the input of the transmission gate (node F). The output of the transmission gate is connected to an intermediate node (node B). Two control terminals of the transmission gate (i.e., gates of CMOS transistors 523A and 525A) receive the clock signal CLKP and the clock signal CLKN, respectively.

In the embodiment shown in FIG. 3B, the inverse QN of the latch output Q may also be output using node F as one output.

In addition, a person skilled in the art will readily understand that the different implementations of the input stage and the feedback stage in the embodiments of the present disclosure may be combined arbitrarily, where appropriate. For example, one or more of the input stage and the feedback stage may be implemented as a tri-state gate or as a combination of an inverter and a transmission gate.

According to the static latch of the embodiment of the present disclosure, the output stage, the feedback stage, and the intermediate node B constitute a latch, so that the potential or logic level at the node B can be statically maintained.

On the other hand, as previously described, in order to mitigate or avoid device leakage from affecting the voltage at a node (e.g., node B), the circuit device connected to that node needs to use a low leakage device. Low leakage devices are typically high threshold devices and are slower in speed than low threshold devices, which also affects the speed of the dynamic latch. At the same time, the dynamic latch needs to operate at a higher frequency to prevent functional errors. While in certain states of the processor (e.g., sleep or idle states), the dynamic latch may operate at a relatively low frequency, in which case the prior art dynamic latch may experience functional errors. In contrast, according to the static latch of the embodiment of the present disclosure, the threshold values of the transistors therein can be configured to be substantially the same, while avoiding the use of high threshold devices. Thereby, the speed of the latch can be provided and the normal operation can be made without a functional error even at a low frequency.

According to the present disclosure, a processor is also provided. FIG. 4 shows a schematic block diagram of a processor including a clock circuit and a static latch, according to one embodiment of the present disclosure. As shown in fig. 4, processor 400 includes at least one static latch 401. The static latch may be a static latch according to any embodiment of the present disclosure. Processor 400 may also include clock circuit 403 for providing the required clock signal to each of the static latches. As shown in fig. 4, the clock circuit 403 receives a clock signal CK (which may be a system clock or a clock signal received from the outside) and outputs different clock signals CLKN and CLKP. As previously described, in some embodiments, the clock signals CLKN and CLKP are opposite in phase.

FIG. 5 shows a schematic block diagram of a clock circuit according to one embodiment of the present disclosure. The clock circuit 500 includes a first inverter 551 and a second inverter 553 connected in series. The first inverter 551 receives a clock signal (e.g., a system clock) CK and outputs a first clock signal (e.g., a clock signal CLKN or CLKP), and the second inverter receives the first clock signal and outputs a second clock signal (e.g., a clock signal CLKP or CLKN). As such, the first clock signal and the second clock signal are inverted with respect to each other. The first clock signal and the second clock signal may be provided to one or more of the plurality of static latches.

FIG. 6 shows a schematic block diagram of a processor including a clock circuit and a plurality of static latches, according to one embodiment of the present disclosure. As shown in fig. 6, the processor 600 includes a plurality of static latches 601 and a clock circuit 602 that provides a clock signal to the plurality of static latches 601. The clock circuit 602 receives the clock 602 and outputs clock signals CLKN and CLKP to each of the static latches 601. The clock circuit 602 may be, for example, a clock circuit as shown in fig. 4.

According to the present disclosure, there is also provided a computing device, which may comprise a processor according to any embodiment of the present disclosure. In some embodiments, the computing device may be a computing device for digital currency. The digital currency may be, for example, digital RMB, Bitty, Ether, Lett, and the like.

Those skilled in the art will appreciate that the boundaries between the operations (or steps) described in the above embodiments are merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A static latch, comprising:

an input stage for receiving a latch input (D);

an output stage for outputting a latch output (Q);

an intermediate node (B) arranged between an output of the input stage and an input of the output stage, wherein the output stage receives as input a signal at the intermediate node; and

a feedback stage receiving the latch output and providing feedback to the intermediate node,

wherein the feedback stage and the input stage have a logic high state, a logic low state, and a high impedance state.

2. The static latch of claim 1, wherein said feedback stage comprises a tri-state gate, said tri-state gate comprising:

first to fourth transistors connected in series in this order, wherein the first transistor and the second transistor are transistors of a first conductivity type, the third transistor and the fourth transistor are transistors of a second conductivity type, the second conductivity type being different from the first conductivity type,

a control terminal of one of the first and second transistors is connected to the latch output, a control terminal of the other of the first and second transistors is connected to a first clock signal,

a control terminal of one of the third and fourth transistors is connected to the latch output, a control terminal of the other of the third and fourth transistors is connected to a second clock signal, wherein the second clock signal is the inverse of the first clock signal,

a node at which the second transistor and the third transistor are connected to each other is connected to the intermediate node.

3. The static latch according to claim 1, wherein said feedback stage comprises a series connected inverter and transmission gate,

an input of the inverter is connected to the latch output, an output of the inverter is connected to an input of the transmission gate, an output of the transmission gate is connected to the intermediate node,

two control terminals of the transmission gate respectively receive a first clock signal and a second clock signal, wherein the second clock signal is the inverse of the first clock signal.

4. The static latch according to any of claims 2-3, wherein:

the first conductivity type is P-type, the second conductivity type is N-type,

when the first clock signal is high and the second clock signal is low, the feedback stage is turned off, thereby presenting a high impedance state;

the feedback stage provides feedback to the intermediate node according to the latch output when the first clock signal is low and the second clock signal is high.

5. The static latch according to any of claims 1-3, wherein said input stage is a tristate logic, said tristate logic receiving said latch input and said first and second clock signals, said tristate logic assuming a logic high state, a logic low state and a high impedance state depending on said input and said first and second clock signals.

6. The static latch of claim 5, wherein

The tristate logic comprises an inverter and a transmission gate connected in series, the inverter receives the latch input, the output of the inverter is connected to one end of the transmission gate, the other end of the transmission gate is connected to the intermediate node, and the control ends of the transmission gate receive the first and second clock signals respectively.

7. The static latch of claim 4, wherein

The input stage includes a tristate gate comprising:

fifth to eighth transistors connected in series in this order, wherein the fifth transistor and the sixth transistor are transistors of a first conductivity type, the seventh transistor and the eighth transistor are transistors of a second conductivity type,

a control terminal of one of the fifth and sixth transistors is connected to the latch input, a control terminal of the other of the fifth and sixth transistors is connected to the second clock signal,

a control terminal of one of the seventh and eighth transistors is connected to the latch input, a control terminal of the other of the seventh and eighth transistors is connected to the first clock signal,

a node at which the sixth transistor and the seventh transistor are connected to each other is connected to the intermediate node.

8. The static latch of claim 7, wherein:

the input stage provides an output to the intermediate node according to the latch input when the first clock signal is high and the second clock signal is low;

when the first clock signal is low and the second clock signal is high, the input stage is turned off, presenting a high impedance state.

9. The static latch of claim 1, wherein the threshold values of the transistors in the static latch are substantially the same.

10. A processor, comprising:

at least one static latch, said static latch being as claimed in any one of claims 1 to 9.

11. The processor of claim 10, wherein the at least one static latch comprises a plurality of static latches; and

a clock circuit for providing a required clock signal to each of the plurality of static latches.

12. The processor of claim 11, wherein the clock circuit comprises a first inverter and a second inverter connected in series, the first inverter receiving a clock signal and outputting a first clock signal, the second inverter receiving the first clock signal and outputting a second clock signal,

the first clock signal and the second clock signal are provided to each of the plurality of static latches.

13. A computing device comprising a processor according to any of claims 10-13.

14. The computing device of claim 13, wherein the computing device is a computing device for digital currency.