CN114556220B

CN114556220B - Multi-tone scheme for maskless lithography

Info

Publication number: CN114556220B
Application number: CN202080069582.2A
Authority: CN
Inventors: 克里斯多弗·丹尼斯·本彻; 托马斯·L·拉伊迪; 约瑟夫·R·约翰逊
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2019-08-30
Filing date: 2020-08-19
Publication date: 2024-07-02
Anticipated expiration: 2040-08-19
Also published as: KR20220048040A; US20220326616A1; WO2021041100A1; CN114556220A

Abstract

Examples described herein provide a system, software application, and method for a lithographic process for writing multiple hues in a single pass. A system includes a stage and a lithography system. The lithography system includes an image projection system, a controller, and a memory. The controller is coupled to the memory, which stores instruction codes. Execution of the instruction code by the controller causes the controller to control the stage and the image projection system to iteratively expose photoresist supported by the stage and to move the stage a step distance relative to the image projection system between sequential pairs of the exposures. Each exposure includes using a writing beam projected from the image projection system. Each exposure is at a respective one of the different doses. The accumulation of the different doses is a full toner amount for the photoresist.

Description

Multi-tone scheme for maskless lithography

Technical Field

Examples of the present disclosure generally relate to lithography systems. More particularly, examples of the present disclosure relate to systems, software applications, and/or methods for exposing a photolithographic process of multiple hues in a single pass (SINGLE PASS).

Background

Photolithography is widely used in the manufacture of semiconductor devices, such as for back-end processing of semiconductor devices, and display devices, such as Liquid Crystal Displays (LCDs). For example, large area substrates are commonly used in the manufacture of LCDs. LCDs or flat panel displays are commonly used for active matrix displays such as computers, touch panel devices, personal Digital Assistants (PDAs), cellular telephones, television monitors, and the like. Generally, a flat panel display includes a liquid crystal material layer as a phase change material sandwiched between two plates at each pixel. When power from the power supply is applied to or through the liquid crystal material, the amount of light passing through the liquid crystal material is controlled (e.g., selectively modulated) at the pixel locations, thereby enabling an image to be generated on the display.

With conventional photolithography systems, it is required to pass the substrate under a writable area of the photolithography system multiple times to write a pattern of full tone portions having full tone amounts and gray tone portions having gray tone amounts into a photoresist disposed over the substrate. Passing the substrate multiple times under the writeable area of the digital lithography system reduces throughput and may lead to overlay problems.

Disclosure of Invention

In some examples, a system is provided. The system includes a stage, a lithography system support, and a lithography system. The stage is configured to support a substrate having photoresist disposed thereon. The lithography system includes an image projection system, a controller, and a memory. The image projection system is coupled to the lithography system support. The controller is coupled to a memory, and the memory stores instruction code to be executed by the controller. Execution of the instruction code by the controller causes the controller to control the stage and the image projection system to iteratively expose the photoresist supported by the stage. The controller is further configured to move the stage relative to the image projection system by a step distance between sequential pairs of exposures. Each of the exposures includes the use of one or more writing beams projected from the image projection system. Each of the exposures is at a respective one of different doses. The accumulated dose as an accumulation of the different doses is a full toner dose for the photoresist.

In other examples, a non-transitory storage medium stores instructions. When the instructions are executed by a processor, the execution causes the processor to perform operations comprising generating a nominal address grid to be overlaid on a surface of a substrate to be processed by a lithography system. The processor generates a processing weight (processing multiplicity) by increasing a nominal weight (nominal multiplicity) by an integer multiple. The processor further generates the integer number of processing address grids based on the nominal address grid, and generates a recipe for a process by the lithography system based on the processing address grids and the different doses. The lithographic system includes an image projection system including an array of pixels. Each pixel of the array of pixels is configured to selectively direct a write beam toward the substrate surface. The processor is further configured to generate the nominal address grid based on the nominal number of weights and nominal pitches for forming full tone features in the photoresist. Additionally, the processor generating the nominal address grid is further based on the pixel array. Each of the processing address grids is associated with a respective one of the different doses. The cumulative dose as the accumulation of the different doses is a full-color toner amount used to form the full-color tone feature.

In yet another example, a method is provided. The method includes executing a recipe by a lithography system. Executing the recipe includes in a single scan: iteratively exposing a photoresist supported by a stage of the lithography system using an image projection system of the lithography system; and moving the stage relative to the image projection system a processing step after the exposing and before a subsequent exposing. The image projection system has an array of pixels. Each pixel of the array of pixels is configured to selectively direct a write beam toward the photoresist. The dose of each of the exposures is different from the previous one of the exposures. For each of the exposures, one or more pixels in the array of pixels project a respective write beam to the photoresist when a center of the respective pixel is aligned with an address location of a processing address grid associated with a respective dose of the respective exposure and when the address location is within a polygon associated with the respective dose of the respective exposure. The accumulation of doses is a full-tone dose used to form full-tone features in the photoresist.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to the described examples, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only examples and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective implementations.

FIG. 1 is a perspective view of a system (such as a digital lithography system) that may be implemented in some examples.

FIG. 2 is a simplified perspective schematic diagram of an image projection system according to some examples.

Fig. 3 is a simplified perspective schematic diagram of the image projection system of fig. 2 according to some examples.

FIG. 4 is a schematic diagram of an interconnect device configured to generate and execute a recipe by a system, according to some examples.

FIG. 5 is a schematic diagram of a recipe generation tool according to some examples.

Fig. 6 is a schematic diagram of a controller according to some examples.

Fig. 7A and 7B are flowcharts of methods for generating and performing recipes for a lithographic process according to some examples.

Fig. 8 is a nominal address grid overlaid on a surface of a substrate according to some examples.

Fig. 9 depicts three processing address grids overlaid on a substrate surface according to some examples.

Fig. 10 is a perspective view of a three-dimensional structure to be patterned in a photoresist according to some examples.

FIG. 11 is a dose curve cross-section implementing the three-dimensional structure and intermediate layer of FIG. 10 according to some examples.

Fig. 12 depicts a frame layer including frame polygons overlaid on a substrate surface according to some examples.

Fig. 13 is a dose curve cross-section implementing the three-dimensional structure and intermediate layer of fig. 10 according to some examples.

Fig. 14 depicts the intermediate layer of fig. 13 superimposed on a substrate surface according to some examples.

Fig. 15, 16, and 17 depict frame polygons of respective processing address grids and respective frame layers overlaid on a substrate surface, according to some examples.

Fig. 18 depicts a photoresist patterned using three levels of doses according to some examples.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one example may be beneficially incorporated in other examples without further recitation.

Detailed Description

Examples described herein provide a system, software application, and method for a lithographic process (such as a digital lithographic process) that writes multiple hues in a single pass. The recipe may be generated by generating a nominal address grid with a nominal weight and a nominal stride and generating an integer number n of processing address grids based on the nominal address grid. For example, the integer n is the number of different doses. Each processing address grid is associated with a respective dose. The processing weight is an integer n times the nominal weight, and the processing stride is a nominal stride divided by the integer n. The three-dimensional structure to be patterned in the photoresist may be decomposed into a plurality of frame layers, each frame layer having one or more frame polygons, wherein each frame layer is associated with a respective dose. A recipe may be generated that, when executed, iteratively exposes the photoresist (e.g., on a substrate on a stage), wherein the iterative exposure of the photoresist loops through different doses. Each exposure includes projecting a write beam (e.g., "shot") from a pixel of a pixel array of the image projection system to the photoresist when a center of the corresponding pixel is aligned with an address location of a processing address grid associated with a dose of the corresponding exposure and within a frame polygon of a frame layer associated with the dose of the corresponding exposure.

Formulations performed according to some examples described herein may implement convolution imaging in a photoresist. Convolution imaging may achieve various three-dimensional structures in a photoresist, such as tapered and/or angled sidewalls, concave surfaces, convex surfaces, and the like. The three-dimensional structures in the photoresist may be transferred into one or more underlying layers by an etching process (e.g., an anisotropic etching process) that may incorporate the three-dimensional structures into integrated circuits, displays, and the like. The recipe may be executed in a single pass of a system (e.g., a lithography system). Performing the recipe in a single pass may avoid multiple substrate loads and substrate alignments, which may avoid overlay errors when forming three-dimensional structures in the photoresist.

Various examples are described below. Although various features of different examples may be described together in a process flow or system, the various features may also be implemented separately or separately and/or in different process flows or different systems. Additionally, various process flows or operations are described as being performed in sequence; other examples may implement process flows or operations in a different order and/or with more or fewer operations.

FIG. 1 is a perspective view of a system 100 (such as a digital lithography system) that may be implemented in some examples. System 100 includes a base frame 110, a plate 120, a table 130, and a processing device 160. The base frame 110 may rest on the floor of the manufacturing facility and may support the plate 120. Passive air isolator 112 may be positioned between base frame 110 and plate 120 and may further support plate 120. For example, the plate 120 may be a monolithic granite.

The table 130 is disposed on the plate 120. The table 130 is supported on the plate 120 by a pair of supports 122 and a pair of rails 124. The pair of support members 122 are provided on the plate member 120. In some examples, plate 120 and pair of supports 122 may be a single piece of material. The pair of rails 124 is supported by the pair of supports 122, and the table 130 is movable along the rails 124 in the X-direction, as shown by the coordinate system shown in fig. 1. In some examples, the pair of tracks 124 is a pair of parallel magnetic channels. As shown, each track of the pair of tracks 124 is a straight path. In other examples, each track of the pair of tracks 124 may have a non-linear path.

The stage 130 is configured to support a substrate 140. Holes (not shown) may be formed in the table 130 to allow lift pins (not shown) to extend therethrough. The lift pins may be raised to an extended position to receive the substrate 140, such as from a transfer robot (not shown). The transfer robot may position the substrate 140 on a lift bar, and the lift bar may then lower the substrate 140 onto the table 130.

The substrate 140 comprises any suitable material and may be made of, for example, quartz, glass, or any other material that may be used as part of a flat panel display. In some examples, the substrate 140 may have a photoresist layer formed thereon. The photoresist layer on the substrate 140 may be patterned using the system 100. Photoresists are sensitive to electromagnetic radiation (e.g., blue, near-Ultraviolet (UV), ultraviolet, or deep ultraviolet) light. The photoresist may be a positive photoresist or a negative photoresist. After exposure to electromagnetic radiation, positive-working photoresists are soluble in a photoresist developer that is applied to the photoresist after exposure to electromagnetic radiation. The negative photoresist is insoluble after exposure to electromagnetic radiation in a photoresist developer applied to the photoresist after exposure to electromagnetic radiation. The chemical composition of the photoresist determines whether the photoresist is a positive photoresist or a negative photoresist. Exemplary photoresists include diazonaphthoquinone, phenolic resins, poly (methyl methacrylate), poly (methyl glutarimide), and SU-8. The pattern formed in the photoresist (as a result of exposing the photoresist to electromagnetic radiation and developing with a photoresist developer) may be used to form circuitry on the substrate 140. For example, after an exposure development is performed on the photoresist, the photoresist may be used as a mask for etching an underlying film to form various structures in the underlying mask layer.

The processing apparatus 160 includes a support 162 and a processing unit 164. The support 162 is disposed on the plate 120 and has an opening 166 for the table 130 to pass under the processing unit 164. The processing unit 164 is coupled to and supported by the support 162. In some examples, processing unit 164 is a pattern generator configured to expose photoresist on substrate 140 in a lithographic process. In some examples, the pattern generator may be configured to perform a maskless lithography process. The processing unit 164 may include an image projection system disposed in a housing 165. The processing device 160 may be used to perform maskless direct patterning. During operation, the table 130 may be moved in the X-direction from a loading position (as shown in fig. 1) to a processing position. The processing position may refer to one or more positions of the table 130 as the table 130 passes (e.g., steps or moves) under the processing unit 164. The table 130 may also be moved in the Y-direction by moving along the rails 150 to process and/or index the substrate 140.

The controller 170 is generally configured to facilitate control and automation of the process techniques described herein. The controller 170 may include and/or be communicatively coupled to a non-transitory memory. Instruction code representing a recipe for control and automation of the processing techniques implemented by the system 100 may be stored in memory. The controller 170 may execute instruction code stored in memory to implement recipes for control and automation of processing techniques performed by the system 100. The controller 170 is coupled to the encoder 126 on or to the table 130. Encoder 126 may provide position information of stage 130 to controller 170. The controller 170 is also coupled to or in communication with the processing apparatus 160. The processing equipment 160 and the platen 118 may provide information to the controller 170 regarding substrate processing and substrate alignment. The controller 170 may initiate various exposures through the processing device 160, as described in further detail below. The controller 170 facilitates control and automation of the method of the lithographic process to write multiple hues in a single pass.

Fig. 2 is a simplified perspective schematic diagram of an image projection system 202 according to some examples. As shown in fig. 2, each image projection system 202 is capable of generating a writing beam 204 and projecting the writing beam onto a surface 206 of the substrate 140. The entire surface 206 may be patterned with the write beam 204 as the substrate 140 moves in the X-direction and/or the Y-direction.

Each image projection system 202 includes an array of spatial light modulators. Each spatial light modulator is referred to as a pixel and, therefore, each image projection system 202 includes an array of spatial light modulator pixels. Spatial light modulator pixel arrays include, but are not limited to, digital micromirrors, liquid Crystal Displays (LCDs), liquid crystal on silicon (LCoS) devices, ferroelectric liquid crystal on silicon (FLCoS) devices, and micro-shutters. Each spatial light modulator pixel is individually controllable and configured to project a write beam. The number of image projection systems 202 may vary based on the size of the substrate 140 and/or the speed of the stage 130. In some examples, there are twenty-two (22) image projection systems 202 in processing device 160.

Fig. 3 is a simplified perspective schematic diagram of the image projection system 202 of fig. 2 according to some examples. The illustrated image projection system 202 includes a light source 302, an aperture 304, a lens 306, a frustrated prism assembly or mirror 308, spatial light modulator pixels 310, a light collector 312, and a projection lens 314. In other examples, the image projection system may include different or fewer components than shown.

The light source 302 may be a Light Emitting Diode (LED) or a laser, and the light source 302 may be capable of generating light having a predetermined wavelength. In some examples, the predetermined wavelength is in the blue or near Ultraviolet (UV) range, such as less than about 450nm. A frustrated prism assembly or mirror 308 may be configured to focus a beam 316 generated by light source 302 and passing through aperture 304 and lens 306 onto spatial light modulator pixel 310. Projection lens 314 may be a 10X objective.

The controller 170 is operable to individually control the spatial light modulator pixels 310 of the image projection system 202 based on instruction codes representing the recipe. In operation, each spatial light modulator pixel 310 is in an "on" position or an "off" position, based on control of the controller 170. During operation, beam 316 is generated by light source 302 and directed to a frustrated prism assembly or mirror 308. The beams 316 are directed from and focused by a frustrating prism assembly or mirror 308 to spatial light modulator pixels 310 of the image projection system 202. When beam 316 reaches spatial light modulator pixel 310, spatial light modulator pixel 310 in the "on" position reflects beam 316, e.g., forming writing beam 204, to projection lens 314. The projection lens 314 then projects the write beam 204 onto the surface 206 of the substrate 140. As used herein, the write beam 204 is also referred to as "emission". Spatial light modulator pixel 310 in the "off" position reflects beam 316 to light collector 312 instead of surface 206 of substrate 140.

In some examples, image projection system 202 is a Digital Micromirror Device (DMD) that includes mirrors, which are spatial light modulator pixels 310. In some examples, the DMD includes 1920×1080 mirrors, which represents the number of pixels of a high definition television or other flat panel display. In some examples, the DMD includes more than about 4,000,000 mirrors.

Fig. 4 is a schematic diagram of an interconnect device configured to generate and execute a recipe by the system 100. As shown in fig. 4, the interconnection device may include a controller 170, a recipe generation tool 402, and a server 404, each connected to a communication network 406 (e.g., an intranet and/or the internet). Examples of the recipe generation tool 402 and the controller 170 are shown and described below in fig. 5 and 6, respectively. Each server 404 may include a processor and system memory (not shown) and may be configured to manage content stored in database 408 using, for example, relational database software and/or a file system. The server 404 may communicate with the database 408 via a local connection (e.g., a Storage Area Network (SAN) or Network Attached Storage (NAS)) or via a communication network 406. Server 404 is configured to directly access data included in database 408 or interface with a database manager configured to manage data included within database 408. The server 404, recipe generation tool 402, and controller 170 may communicate with each other via a communication network 406, such as by using a network protocol (such as the TCP/IP protocol).

FIG. 5 is a schematic diagram of a recipe generation tool 402 according to some examples. The recipe generation tool 402 includes a Central Processing Unit (CPU) 502, a network interface 504, a memory 520, a storage device 530, and support circuitry 540, each connected to an interconnect 506. The recipe generation tool 402 may also include an I/O device interface 508 that connects I/O devices 510 (e.g., keyboard, display, touch screen, and mouse apparatus) to the recipe generation tool 402. The network interface 504 may be connected to, for example, the communication network 406 and may be configured to transmit data via the communication network 406.

The CPU 502 is configured to retrieve and execute instruction code stored in the memory 520 and/or storage device 530, and is generally configured to control and coordinate the operation of other system components. Similarly, the CPU 502 is configured to cause the application data 526 to be stored in the memory 520 and retrieve the application data stored in the memory 520. CPU 502 is included to represent a single CPU, multiple CPUs, a single CPU having multiple processing cores, and the like. The interconnect 506 is operable to transfer instruction code and application data 526 between the CPU 502, the I/O device interface 508, the storage 530, the network interface 504, and the memory 520.

Memory 520 is typically included to represent any non-transitory memory (e.g., random Access Memory (RAM) (such as static RAM and dynamic RAM), read Only Memory (ROM), etc.), which may be volatile and/or nonvolatile, and is operable in operation to store one or more software applications and data for use by CPU 502. Storage device 530 is typically included to represent any non-transitory, non-volatile memory, such as a hard disk drive, solid State Storage Drive (SSD), or the like. Although shown as a single unit, the storage device 530 may be a combination of fixed and/or removable storage apparatus, such as a fixed magnetic disk drive, floppy disk drive, hard disk drive, flash memory drive, magnetic tape drive, removable memory card, CD-ROM, optical storage device, or the like, configured to store non-volatile data. Memory 520 may store instruction code for recipe generation application software 522 that can be executed by CPU 502. In some examples, instruction code for recipe generation application software 522 may additionally and/or alternatively be stored in storage device 530.

Support circuitry 540 is also connected to interconnect 506 to support CPU 502 and/or to other components to support the CPU. The support circuits 540 may include a cache 542, a power supply 544, a clock circuit 546, input/output circuitry 548 and the like.

Fig. 6 is a schematic diagram of a controller 170 according to some examples. The controller 170 includes a CPU 602, a network interface 604, an interconnect 606, an I/O device interface 608, a memory 620, a storage 630, and support circuitry 640, each connected to the interconnect 606. The I/O device interface 608 connects to I/O devices 610 (e.g., keyboard, display, touch screen, and mouse apparatus), the processing apparatus 160, and the encoder 126. The network interface 604 may be connected to, for example, the communication network 406 and may be configured to transmit data via the communication network 406.

The CPU 602 is configured to retrieve and execute instruction code stored in the memory 620 and/or the storage device 630 and is generally configured to control and coordinate the operation of other system components. Similarly, the CPU 602 is configured to cause the application data 626 to be stored in the memory 620 and retrieve the application data stored in the memory 620. The CPU 602 may be any form of computer processor used in an industrial environment to control various processes and hardware (e.g., pattern generators, motors, and other hardware) and monitor processes (e.g., processing time and substrate position). Instruction code executable by the controller 170 may determine which tasks may be performed on the substrate 140. For example, the CPU 602 may control the processing apparatus 160 by communication via the interconnect 606 and the I/O device interface 608 and/or may receive data from the encoder 126 by communication via the interconnect 606 and the I/O device interface 608. The CPU 602 is included to represent a single CPU, multiple CPUs, a single CPU with multiple processing cores, and the like. The interconnect 606 is operable to transfer instruction code and application data 626 between the CPU 602, the I/O device interface 608, the storage device 630, the network interface 604, and the memory 620.

Memory 620 is typically included to represent any non-transitory memory that may be volatile and/or nonvolatile and that is operable in operation to store one or more software applications and data for use by CPU 602. Storage device 630 is typically included to represent any non-transitory, non-volatile memory, such as storage device 530. Memory 620 may store instruction codes for recipe execution application software 622 that can be executed by CPU 602. In some examples, instruction code for the recipe execution application software 622 may additionally and/or alternatively be stored in the storage device 630.

Support circuitry 640 is also connected to interconnect 606 to support CPU 602 and/or to other components to support the CPU. Support circuits 640 may include a cache 642, a power supply 644, clock circuit 646, input/output circuitry 648, and the like.

Some examples distribute aspects described herein among the various devices of fig. 4. For example, data related to the system 100 (e.g., rotational angle of an image projection system as described below) may be measured and/or obtained by the controller 170, and the controller 170 may communicate the data to the server 404 for storage in the database 408. The recipe generation tool 402 may retrieve data from the database 408 via the server 404 for generating a recipe to be implemented by the controller 170 on the system 100. The recipe generation tool 402 may generate a recipe and communicate the recipe to the server 404 for storage in a database 408 that may be retrieved by the controller 170, or may communicate the recipe to the controller 170. The controller 170 may then execute the recipe at the system 100. In some examples, recipe generation and execution may be performed by the controller 170. Various combinations and permutations of the different aspects of the distributions described herein will be apparent to those skilled in the art and are contemplated by the different examples.

Fig. 7A and 7B are flowcharts of a method 700 for generating and performing a recipe for a lithographic process, according to some examples. At block 702, an exposure recipe is generated. At block 704, an exposure recipe is executed. At block 706, the photoresist (which has been processed according to the exposure recipe) is developed. In some examples, the exposure recipe generated at block 704 is executed by the recipe generation tool 402, such as by executing the recipe generation application 522. As an example, the recipe generation application software 522 may include Computer Aided Design (CAD) software that allows a user to create a representation of a three-dimensional photoresist pattern to be implemented by the system 100 via the I/O device 510. The CAD software may render (render) frame polygons of the frame layer, as described below. The recipe generation application 522 may further generate an address grid and may generate a recipe based on the frame layer and the address grid, as described below. In other examples, these different operations are distributed to different tools executing various application software. The controller 170 may execute the recipe on the system 100, such as by controlling the image projection system and the workstation 130. The recipe may be executed to implement the various operations shown in block 704 and described further below.

In the example shown, generating the exposure recipe of block 702 includes blocks 710 through 718. At block 710, a nominal address grid is generated at a nominal weighing number and a nominal stride. The nominal address grid may also be generated based on the pixel array of the spatial light modulator of the image projection system, the rotation angle of the image projection system, and the number of dummy columns and/or dummy rows of the pixel array of the image projection system. The image projection system may be mounted on a support 162 such that the pixel array of the spatial light modulator is rotated by a rotation angle in a step or scan in the Y direction (as shown in fig. 1) relative to the substrate 140. The dummy columns and/or rows may be based on the rotation angle. Dummy columns and/or rows may be identified to avoid being disturbed by exposure. Dummy columns and/or rows may be turned off during processing.

The nominal weight and nominal step size may be based on considerations such as Line Edge Roughness (LER) and throughput. The nominal number may refer to the number of emissions to fill the photoresist with full tone features. Higher weights can increase accuracy and decrease LER, but require a tradeoff of increased processing time and decreased throughput. The nominal step distance may refer to the distance the stage 130 moves the substrate 140 between nominal exposures and may be closely related to the pixel array and the nominal weight. Typically, the nominal stride is the quotient of (i) the number of columns of the pixel array (e.g., extending substantially perpendicularly from the Y-direction of fig. 1) and the number of dummy columns divided by (ii) the nominal weight.

The nominal address grid may be formed as a collection of address locations overlaid on the substrate surface. Each address location corresponds to the center of the location of the pixel array at a given location of the substrate where the pixels of the pixel array are capable of directing the write beam to the substrate surface (e.g., it does not include pixels in dummy columns and/or rows). The set of address locations includes each center of each location of the pixel array (e.g., each location after movement triggers an exposure in a single scan). Using the nominal stride and rotation angle, the nominal address grid may be a hexagonal close-packed (HCP) pattern. Fig. 8 shows a nominal address grid 802 overlaid on a substrate surface 800 as an example.

Referring back to the method 700 of fig. 7A and 7B, at block 712, the target weighing number is increased by an integer n to arrive at a processing weight number. The integer n may allow for the emission of n doses. The dose level (e.g., individually described herein as j-level dose) may be different, which may permit gray scale exposure. As an example, n may be equal to three and the dose may be some binary exponential multiple of the nominal dose d ₀. In such an example, each dose may be (2 ^(j-1))d₀, where j corresponds to a dose level and ranges from 1 to n. Additionally, in this example, eight different dose accumulations may be generated for any polygon to be written to the photoresist (e.g., no exposure, d ₀ exposure, … …, 7d ₀ exposure). Any integer n equal to or greater than 2 may be implemented, in some examples, the integer n may generate four or more available quantization level exposures for any polygon to be written to the photoresist. The cumulative dose of doses at all levels is equal to the dose used to form full tone features in the photoresist (e.g.,Where D _FT is the full toner dose and D _j is the j level dose).

At block 714, the nominal stride is reduced to the processing stride. The processing stride is the quotient of the nominal stride divided by the integer n. Increasing the nominal weighing number by an integer n times results in a decrease in the nominal step size. As an example, if the nominal weights and nominal steps are 115 and 17.27 μm, and n is 3, the process weights are increased to 445 and the process steps are reduced to 5.76 μm.

At block 716, n processing address grids are generated. Each processing address grid is associated with a respective dose. The processing address grid may be generated based on the nominal address grid and using the processing weight and processing stride through rotation angles and identified dummy rows or columns. In some examples, a treatment address grid associated with one level of dose may be superimposed over a treatment address grid associated with another level of dose. In some examples, a processing address grid associated with one level of dose may be offset from a processing address grid associated with another level of dose by some multiple of, for example, a processing stride. Continuing with the example above, where n is equal to three (3). Fig. 9 shows three processing address grids 902, 904, 906 superimposed on a substrate surface 800. The processing address grid 902 corresponds to the nominal address grid 802 shown in fig. 8. For purposes of the description herein, the processing address grid 902 is associated with a j=3 horizontal dose (e.g., a 4d ₀ exposure). The processing address grid 904 is associated with a j=2 horizontal doses (e.g., 2d ₀ exposures). The processing address grid 906 is associated with a j=1 horizontal dose (e.g., d ₀ exposure). In this example, processing address grid 904 and processing address grid 906 are offset from processing address grid 902 by a processing stride and twice a processing stride, respectively. Any processing address grid may be associated with any level of dose.

At block 718, frame layers including one or more polygons to be patterned in the photoresist are generated, and each frame layer is associated with a respective one of the doses. A representation of a three-dimensional structure (e.g., CAD drawing) to be patterned in the photoresist may be decomposed into rasterized frame polygons. In general, a dose curve may be generated based on a representation of a three-dimensional structure to be patterned in a photoresist. Frame polygons may then be generated from the dose curve. The level of rasterization may be quantified based on the different levels of dose.

In some examples, intermediate layers each associated with a respective level of dose are generated from a dose curve based on the respective level of dose, and the intermediate layers are rasterized to form a frame layer having a polygon. The intermediate layer may be iteratively generated starting with the intermediate layer associated with the highest level dose and continuing to each next highest level dose at each iteration. Each intermediate layer includes pixels that have been identified as being associated with the intermediate layer. In each iteration and for a respective intermediate layer, a pixel is identified as being associated with that intermediate layer if: at the location of the corresponding pixel, the difference between the dose curve and the accumulation of dose levels of the previous iteration (if any) at that location is greater than or equal to the dose associated with the intermediate layer. Each intermediate layer is then rasterized into a corresponding frame layer, wherein successive pixels that have been identified as being associated with the intermediate layer form a corresponding frame polygon within the frame layer. Pixels within the frame polygon are set to on for exposure of the associated dose, while other pixels are set to off.

Fig. 10 shows a perspective view of an exemplary three-dimensional structure 1000 to be patterned in photoresist. The three-dimensional structure 1000 is in this example a semi-elliptical cylinder.

Fig. 11 shows a cross section of a dose curve 1100 to achieve a three-dimensional structure 1000 and an exemplary intermediate layer. The cross-section of the dose curve 1100 of fig. 11 closely approximates the cross-section of the three-dimensional structure 1000 of fig. 10, for example, to more easily conceptualize the relationship between dose accumulation and the three-dimensional structure 1000. In practice, the dose curve cross-section may differ from the corresponding cross-section of the three-dimensional structure, for example, due to a non-linear relationship between the dose and the structure formed as a result of exposure to the dose.

In fig. 11, j=3 middle layers include pixels 1102 and are defined as being associated with a j=3 horizontal dose (e.g., 4d ₀). The pixels 1102 below the dose curve 1100 between the boundaries 1110d correspond to locations where the dose curve 1100 is greater than or equal to j=3 horizontal doses (e.g., 4d ₀) and are identified as being associated with j=3 middle layers.

The j=2 middle layer includes pixels 1104a, 1104b and is defined as being associated with a j=2 horizontal dose (e.g., 2d ₀). The pixels 1104a below the dose curve 1100 between the boundaries 1110b correspond to locations where the difference between the dose curve 1100 and the j=3 horizontal dose (e.g., 4d ₀) is greater than or equal to the j=2 horizontal dose (e.g., 2d ₀) and are identified as being associated with the j=2 middle layer. The pixel 1104b below the dose curve 1100 between the boundary 1110d and the boundary 1110f corresponds to a location where the dose curve 1100 (e.g., where there is no j=3 horizontal dose) is greater than or equal to j=2 horizontal doses (e.g., 2d ₀) and is identified as being associated with the j=2 middle layer.

The j=1 middle layer includes pixels 1106a, 1106b, 1106c, 1106d and is defined as being associated with a j=1 horizontal dose (e.g., d ₀). The pixels 1106a under the dose curve 1100 between the boundaries 1110a correspond to locations where the difference between the dose curve 1100 and the accumulation of j=3 horizontal doses (e.g., 4d ₀) and j=2 horizontal doses (e.g., 2d ₀) is greater than or equal to j=1 horizontal doses (e.g., d ₀) and are identified as being associated with j=1 interlayers. The pixel 1106b below the dose curve 1100 between the boundary 1110b and the boundary 1110c corresponds to a position where the difference between the dose curve 1100 and the j=3 horizontal dose (e.g., 4d ₀) (e.g., where no j=2 horizontal dose is present) is greater than or equal to the j=1 horizontal dose (e.g., d ₀) and is identified as being associated with the j=1 middle layer. Pixel 1106c below dose curve 1100 between boundary 1110d and boundary 1110e corresponds to a position where the difference between dose curve 1100 and j=2 horizontal doses (e.g., 2d ₀) (e.g., where j=3 horizontal doses are not present) is greater than or equal to j=1 horizontal doses (e.g., d ₀) and is identified as being associated with a j=1 middle layer. The pixel 1106d below the dose curve 1100 between the boundary 1110f and the boundary 1110g corresponds to a location where the dose curve 1100 (e.g., where there is no j=3 horizontal dose or j=2 horizontal dose) is greater than or equal to j=1 horizontal dose (e.g., d ₀) and is identified as being associated with the j=1 middle layer.

Fig. 12 shows that the frame layer includes frame polygons to continue the foregoing example. The j=3 middle layer is rasterized to j=3 frame layers. Pixel 1102 forms a frame polygon 1202 for the j=3 frame layer. For a j=3 horizontal dose (e.g., 4d ₀), the pixels within the frame polygon 1202 are set to on, and for a j=3 horizontal dose, the pixels outside the frame polygon 1202 are set to off. The j=2 middle layer is rasterized to a j=2 frame layer. The pixels 1104a form frame polygons 1204a for the j=2 frame layers, and the corresponding consecutive pixels 1104b form frame polygons 1204b for the j=2 frame layers. For a j=2 horizontal dose (e.g., 2d ₀), pixels within any of the frame polygons 1204 a-1204 b are set to on, and pixels outside of the frame polygons 1204 a-1204 b are set to off. The j=1 middle layer is rasterized to a j=1 frame layer. Pixel 1106a forms frame polygon 1206a for the j=1 frame layer; the corresponding consecutive pixels 1106b form frame polygons 1206b for the j=1 frame layer; the corresponding consecutive pixels 1106c form a frame polygon 1206c for the j=1 frame layer; and the corresponding consecutive pixels 1106d form frame polygons 1206d for the j=1 frame layer. For a j=1 horizontal dose (e.g., d ₀), pixels within any of the frame polygons 1206 a-1206 d are set to on, and pixels outside of the frame polygons 1206 a-1206 d are set to off. Fig. 12 shows frame polygons 1202 for j=3 frame layers, frame polygons 1204a through 1204b for j=2 frame layers, and frame polygons 1206a through 1206d for j=1 frame layers, each of which is overlaid on the substrate surface 800.

The cumulative dose is shown by the overlapping middle layer in fig. 11. The region between boundaries 1110a receives a cumulative dose of 7d ₀ (e.g., d ₀+2d₀+4d₀), which in this example is the dose used to form full tone features in the photoresist. A cumulative dose of 6d ₀ (e.g., 2d ₀+4d₀) is received at a respective region between the boundary 1110a and the boundary 1110 b. The cumulative dose of 5d ₀ (e.g., d ₀+4d₀) is received at the corresponding region between boundary 1110b and boundary 1110 c. The cumulative dose of 4d ₀ is received at the corresponding region between boundary 1110c and boundary 1110 d. The cumulative dose 3d ₀ (e.g., d ₀+2d₀) is received at a corresponding region between the boundary 1110d and the boundary 1110 e. The cumulative dose of 2d ₀ is received at the corresponding region between boundary 1110e and boundary 1110 f. The cumulative dose d ₀ is received at the corresponding region between the boundary 1110f and the boundary 1110 g.

In some examples, intermediate layers each associated with a respective accumulation of doses are generated from a dose curve based on the respective accumulated doses, and the intermediate layers are rasterized to form a frame layer comprising polygons. Each intermediate layer includes pixels that have been identified as being associated with the intermediate layer. The intermediate layer may be generated by comparing the dose curve with the corresponding accumulated dose associated with the corresponding layer. For a respective intermediate layer, a respective pixel is identified as being associated with that intermediate layer when the respective pixel is at a position where the dose curve is equal to or greater than the cumulative dose associated with the respective intermediate layer. Each intermediate layer is then rasterized into frame layers that are each associated with a respective level of dose using boolean expressions to identify pixels as being associated with the respective frame layer. Successive pixels that have been identified as being associated with a frame layer form a corresponding frame polygon within the frame layer. Pixels within the frame polygon are set to on for exposure of the associated dose, while other pixels are set to off.

Fig. 13 shows a cross section of a dose curve 1300 to achieve a three-dimensional structure 1000 and an exemplary intermediate layer. Fig. 14 shows an intermediate layer overlying a substrate surface 800. Just like fig. 11, the cross-section of the dose curve 1300 of fig. 13 closely approximates the cross-section of the three-dimensional structure 1000 of fig. 10, but in practice the dose curve cross-section may be different from the cross-section of the three-dimensional structure.

In fig. 13, an a=1 middle layer includes pixels 1302 and is defined as being associated with an a=1 cumulative dose (e.g., d ₀). The pixels 1302 below the dose curve 1300 between the boundaries 1320g correspond to locations where the dose curve 1300 is greater than or equal to a=1 cumulative doses (e.g., d ₀) and are identified as being associated with a=1 middle layer.

The a=2 middle layer includes pixels 1304 and is defined as being associated with a=2 cumulative doses (e.g., 2d ₀). The pixels 1304 below the dose curve 1300 between the boundaries 1320f correspond to locations where the dose curve 1300 is greater than or equal to a=2 cumulative doses (e.g., 2d ₀) and are identified as being associated with a=2 middle layers.

The a=3 intermediate layer includes pixels 1306 and is defined to be associated with a=3 cumulative doses (e.g., 3d ₀). The pixels 1306 below the dose curve 1300 between the boundaries 1320e correspond to locations where the dose curve 1300 is greater than or equal to a=3 cumulative doses (e.g., 3d ₀) and are identified as being associated with a=3 intermediate layers.

The a=4 middle layer has pixels 1308 and is defined as being associated with a=4 cumulative dose (e.g., 4d ₀). The pixels 1308 under the dose curve 1300 between the boundaries 1320d correspond to locations where the dose curve 1300 is greater than or equal to a=4 cumulative doses (e.g., 4d ₀) and are identified as being associated with a=4 middle layers.

The a=5 middle layer has pixels 1310 and is defined as being associated with a=5 cumulative dose (e.g., 5d ₀). The pixels 1310 below the dose curve 1300 between the boundaries 1320c correspond to locations where the dose curve 1300 is greater than or equal to a=5 cumulative doses (e.g., 5d ₀) and are identified as being associated with an a=5 middle layer.

The a=6 intermediate layer includes pixels 1312 and is defined as being associated with a=6 cumulative dose (e.g., 6d ₀). The pixels 1312 below the dose curve 1300 between the boundaries 1310b correspond to locations where the dose curve 1300 is greater than or equal to a=6 cumulative doses (e.g., 6d ₀) and are identified as being associated with a=6 intermediate layers.

The a=7 middle layer has pixels 1314 and is defined to be associated with a=7 cumulative dose (e.g., 7d ₀). Pixels 1314 below the dose curve 1300 between boundaries 1310a correspond to locations where the dose curve 1300 is greater than or equal to a=7 cumulative doses (e.g., 7d ₀) and are identified as being associated with an a=7 middle layer. In fig. 14, intermediate layers with corresponding pixels 1302 to 1314 are shown, which are superimposed on the substrate surface 800.

Intermediate layers a=1 to a=7 are rasterized into frame layers associated with the corresponding doses using boolean expressions. To rasterize the j=3 frame layers associated with the j=3 horizontal dose (e.g., 4d ₀), pixels 1308 are identified as frame polygons 1202 associated with the j=3 frame layers and form the j=3 frame layers. For a j=3 horizontal dose (e.g., 4d ₀), the pixels within the frame polygon 1202 are set to on, and for a j=3 horizontal dose, the pixels outside the frame polygon 1202 are set to off. To rasterize the j=2 frame layer associated with the j=2 horizontal dose (e.g., 2d ₀), pixels corresponding to (i) pixel 1312 or (ii) pixel 1304 that do not overlap pixel 1308 are identified as being associated with the j=2 frame layer, and consecutive pixels of those identified pixels form frame polygons 1204 a-1204 b of the j=2 frame layer. For a j=2 horizontal dose (e.g., 2d ₀), the pixels within the frame polygons 1204 a-1204 b are set to on, and for a j=2 horizontal dose, the pixels outside the frame polygons 1204 a-1204 b are set to off. To rasterize the j=1 frame layer associated with the j=1 dose (e.g., d ₀), pixels corresponding to (i) pixel 1314, (ii) pixel 1310 that does not overlap with pixel 1312, (iii) pixel 1306 that does not overlap with pixel 1308, or (iv) pixel 1302 that does not overlap with pixel 1304 are identified as being associated with the j=1 frame layer, and consecutive pixels of these identified pixels form frame polygons 1206 a-1206 d of the j=1 frame layer. For a j=1 horizontal dose (e.g., d ₀), the pixels within the frame polygons 1206 a-1206 d are set to on, and for a j=1 horizontal dose, the pixels outside the frame polygons 1206 a-1206 d are set to off. As described above. Fig. 12 shows frame polygons 1202 for j=3 frame layers, frame polygons 1204a through 1204b for j=2 frame layers, and frame polygons 1206a through 1206d for j=1 frame layers, each of which is overlaid on the substrate surface 800.

In some examples, the processing stride, processing address grid, and frame layer generated in block 702 may be or form a recipe. In such an example, the recipe execution application 622 may include logic or control that interprets the processing steps, processes the address grid, and frame layers to execute the recipe and process the substrate 140 in the system 100. In some examples, recipe generation application 522 may use the processing steps, the processing address grid, and the frame layer to infer, for example, the original position of the substrate during processing and which pixels of the image projection system are turned on to project a dose. Any permutation or combination in the generation and execution of the recipe is within the scope of the various examples.

Referring back to the method 700 of fig. 7A and 7B, at block 704 an exposure recipe is executed. In block 704 and block 720, index j is set equal to integer n. Then, at block 722, the photoresist on the substrate supported by the stage of the system (e.g., system 100) is exposed to a j-level dose. When the center of the corresponding pixel is aligned with the address location of the processing address grid associated with the j horizontal dose and within the frame polygon of the frame layer associated with the j horizontal dose, the pixels of the image projection system are turned on (and thus, the corresponding write beam or emission is projected); otherwise, the pixels of the image projection system are turned off. Following the exposure of block 722, at block 724, a determination is made as to whether the recipe is complete (e.g., the frame polygons of the frame layer are completely filled). If the recipe is not complete, at block 726 the stage is moved a processing distance relative to the image projection system to trigger another exposure. Movement of the table relative to the image projection system includes moving the table while the image projection system remains in a fixed position, moving the image projection system while the table remains in a fixed position, or a combination of both the table and the image projection system. Additionally, movement of the stage relative to the image projection system may be performed by continuous movement (e.g., without stopping for exposure, where each exposure is triggered by moving a processing step from the position of occurrence of the previous exposure) and/or by discrete steps (e.g., pausing at a position for exposure).

Then, at block 728, it is determined whether the index j is equal to or less than 1. If not, at block 728, the index j is decremented by one and the method 700 loops back to block 722 for another exposure. If at block 728, index j is equal to or less than 1, method 700 loops back to block 720 to reset index j to equal n. Thus, as shown in block 704, the photoresist is iteratively exposed with corresponding movement, wherein the iterative exposure loops between doses of different levels. The dose may be achieved by varying the dwell time and/or intensity of the exposure relative to other doses. Block 704 is shown as an example. The operations of the blocks may be performed in a different order. Alternatively, cycling between different doses may be performed in any order.

Fig. 15 to 17 show examples of executing an exposure recipe continuing the above example, where the integer n is equal to three (3). In the first iteration, at block 720, index j is set to 3. Then, at block 722, the photoresist is exposed to a j=3 horizontal dose (e.g., 4d ₀). Fig. 15 shows a processing address grid 902 and a frame polygon 1202 of j=3 frame layers (each associated with a j=3 horizontal dose) superimposed on a substrate surface 800. Each of the image projection systems has pixels aligned with the address locations of the processing address grid 902 and centered within the frame polygon 1202 turned on and directs the corresponding emission of the j=3 horizontal doses to the locations of the photoresist corresponding to those pixels. As determined in block 724, the frame polygons 1202, 1204 a-1204 b, 1206 a-1206 d are not completely filled, and then, at block 726, the stage is moved relative to the image projection system by a processing step distance to trigger another exposure. Since index j is not less than or equal to one, as determined at block 728, index j is reduced by one to get 2.

In a second iteration, with index j set to 2, at block 722, the photoresist is exposed to a j=2 horizontal dose (e.g., 2d ₀). Fig. 16 shows a processing address grid 904 overlaid on a substrate surface 800 and frame polygons 1204 a-1204 b (each associated with a j=2 horizontal dose) of j=2 frame layers. The pixels of the image projection system, each having a center aligned with the address location of the processing address grid 904 and within any of the frame polygons 1204 a-1204 b, are turned on and the corresponding emission of the j=2 horizontal doses is directed to the locations of the photoresist corresponding to those pixels. As determined in block 724, the frame polygons 1202, 1204 a-1204 b, 1206 a-1206 d are not completely filled, and then, at block 726, the stage is moved relative to the image projection system by a processing step distance to trigger another exposure. Since index j is not less than or equal to one, as determined at block 728, index j is reduced by one to get 1.

In a third iteration, with index j set to 1, at block 722, the photoresist is exposed to j=1 horizontal doses (e.g., d ₀). Fig. 17 shows a processing address grid 906 and frame polygons 1206a through 1206d (each associated with a j=1 horizontal dose) of j=1 frame layers superimposed on a substrate surface 800. The pixels of the image projection system, each having a center aligned with the address location of the processing address grid 906 and within any of the frame polygons 1206 a-1206 d, are turned on and the corresponding emission of the j=1 horizontal dose is directed to the locations of the photoresist corresponding to those pixels. As determined in block 724, the frame polygons 1202, 1204 a-1204 b, 1206 a-1206 d are not completely filled, and then, at block 726, the stage is moved relative to the image projection system by a processing step distance to trigger another exposure. Since index j is equal to one, as determined at block 728, index j is reset to 3 at block 720. Then, a subsequent iteration with a moving exposure is performed, where the exposure loops through doses of different levels until the frame polygons 1202, 1204 a-1204 b, 1206 a-1206 d are completely filled, as determined by block 724, to complete recipe execution.

Referring back to the method 700 of fig. 7A and 7B, at block 706, the photoresist is developed. Continuing with the example described in the context of fig. 8-17, the photoresist may be developed into the three-dimensional structure 1000 of fig. 10.

The various examples may be implemented with any number of levels of doses. Examples may implement any differently quantified dose, which may or may not be a binary exponential multiple of the nominal dose. Table 1 below shows exemplary combinations of cumulative doses when the integer n equals two (2). Table 2 below shows exemplary combinations of cumulative doses when the integer n equals three (3). Table 3 below shows exemplary combinations of cumulative doses when the integer equals four. In these tables, d _j indicates the j-level dose, and d ₁＜d₂＜d₃＜d₄ is generally assumed.

Fig. 18 depicts a photoresist patterned using three levels of doses according to some examples. In this example, the photoresist is a three-dimensional blazed grating. As shown, the use of a single scan process produces smooth, tapered sidewalls. The single scan process may be implemented with a single substrate loading and single substrate alignment. Accordingly, since multiple substrate loading steps and multiple substrate alignments can be avoided, a single scan can be used to reduce processing time. Additionally, overlay errors may be avoided by a single substrate loading and single substrate alignment. The exposure may be self-aligned.

While the foregoing is directed to examples of the present disclosure, other and further examples of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A system for a lithographic process, the system comprising:

a stage configured to support a substrate having a photoresist disposed thereon;

a lithography system support;

A lithography system comprising an image projection system, a controller, and a memory, wherein:

the image projection system is coupled to the lithography system support;

the controller is coupled to the memory, and the memory stores instruction code to be executed by the controller;

execution of the instruction code by the controller causes the controller to control the stage and the image projection system to:

Iteratively exposing the photoresist supported by the stage, each of the exposures including the use of one or more writing beams projected from the image projection system, each of the exposures being at a respective one of a different dose, the accumulated dose being a full color toner quantity for the photoresist as an accumulated of different doses; and

The stage is moved by a step distance relative to the image projection system between sequential pairs of exposures, wherein each address grid associated with a respective one of the different doses is offset from each other address grid associated with each other of the different doses.

2. The system of claim 1, wherein the different doses are different binary exponential multiples of a nominal dose.

3. The system of claim 1, wherein:

the image projection system includes an array of pixels; and

For each of the exposures, one or more of the pixels of the pixel array projects a respective write beam to the photoresist when the center of the respective pixel is aligned with an address location of an address grid within a polygon, each of the address grid and the polygon being associated with a respective one of the different doses of the respective exposure.

4. The system of claim 3, wherein each address grid associated with any of the different doses is a hexagonal close-packed (HCP) pattern of address locations.

5. The system of claim 3, wherein different frame layers are associated with respective ones of the different doses, a frame layer of the frame layers comprising the polygon associated with a respective one of the different doses of the respective exposure.

6. A non-transitory storage medium storing instructions that, when executed by a processor, cause the processor to perform operations comprising:

generating a nominal address grid to be superimposed on a substrate surface to be processed by a lithography system, the lithography system comprising an image projection system, the image projection system comprising an array of pixels, each pixel of the array of pixels configured to selectively direct a write beam toward the substrate surface, the generating the nominal address grid being based on a nominal number of weights and a nominal step for forming full tone features in a photoresist, the generating the nominal address grid further being based on the array of pixels;

Generating a process weight by increasing the target weight by an integer multiple;

generating the integer number of processing address grids based on the nominal address grid, each of the processing address grids being associated with a respective one of different doses, a cumulative dose being a full-tone toner quantity for forming the full-tone feature; and

A recipe for processing by the lithography system is generated based on the processing address grid and the different doses.

7. The non-transitory storage medium of claim 6, wherein:

the recipe includes instruction code to be executed by a controller; and

Execution of the instruction code by the controller causes the controller to control a stage of the lithographic system and the image projection system to:

Iteratively exposing the photoresist supported by the stage, each of the exposures being at a respective one of the different doses, for each of the exposures, one or more of the pixels of the pixel array projecting a respective write beam to the photoresist when a center of a respective pixel is aligned with an address location of the processing address grid associated with a respective one of the different doses of the respective exposure and when the address location is within a polygon associated with the respective one of the different doses of the respective exposure; and

The stage is moved relative to the image projection system by a processing step after each of the exposures before a next one of the exposures.

8. The non-transitory storage medium of claim 7, wherein the processing stride is a quotient of the nominal stride divided by the integer.

9. The non-transitory storage medium of claim 6, wherein the different doses are different binary exponential multiples of a nominal dose.

10. The non-transitory storage medium of claim 6, wherein each of the processing address grids is a hexagonal close-packed (HCP) pattern of address locations.

11. The non-transitory storage medium of claim 6, wherein the operations further comprise:

Obtaining a representation of a three-dimensional structure to be patterned in the photoresist; and

The representation of the three-dimensional structure is decomposed into polygons in respective layers, each of the layers being associated with a respective one of the different doses, the recipe being further based on the polygons of the layers.

12. A lithographic method, comprising:

executing a recipe by a lithography system, the executing the recipe comprising in a single scan:

iteratively exposing a photoresist supported by a stage of the lithographic system using an image projection system of the lithographic system, the image projection system comprising an array of pixels, each pixel of the array of pixels configured to selectively direct a write beam toward the photoresist, a dose of each of the exposures being different from a previous one of the exposures, for each of the exposures, one or more pixels of the array of pixels projecting a respective write beam to the photoresist when a center of the respective pixel is aligned with an address location of a processing address grid associated with the respective dose of the respective exposure and when the address location is within a polygon associated with the respective dose of the respective exposure, a buildup of the doses being a full-color toner amount for forming a full-color tone feature in the photoresist; and

The stage is moved relative to the image projection system by a processing stride after the exposure and before a subsequent exposure, wherein each processing address grid associated with a respective dose is offset from each other processing address grid associated with each other dose.

13. The lithographic method of claim 12, further comprising:

generating a nominal address grid to be superimposed on the photoresist, the generating the nominal address grid being based on a nominal number of weights and a nominal step for forming the full tone feature in the photoresist, the generating the nominal address grid further being based on the pixel array;

Generating a processing weight by increasing the nominal weight by an integer multiple, the processing stride being a quotient of the nominal stride divided by the integer;

generating the integer number of treatment address grids based on the nominal address grids, each of the treatment address grids being associated with a respective one of the doses; and

The recipe is generated based on the processing address grid and the dose.

14. The lithographic method of claim 12 or 13, further comprising:

Decomposing the representation of the three-dimensional structure into polygons in respective frame layers, each of the frame layers associated with a respective one of the doses, wherein the recipe is further based on the polygons of the frame layers.

15. The lithographic method of claim 14, wherein decomposing the representation of the three-dimensional structure comprises:

obtaining a dose curve corresponding to the three-dimensional structure;

Starting from a highest dose and iteratively continuing for each next highest dose, identifying pixels of a respective intermediate layer associated with the dose of a respective iteration, the identified pixels corresponding to respective locations at which a difference between the dose curve and a cumulative dose of a previous iteration is equal to or greater than the dose of the respective iteration; and

The intermediate layer is rasterized into the frame layer.

16. The lithographic method of claim 14, wherein decomposing the representation of the three-dimensional structure comprises:

obtaining a dose curve corresponding to the three-dimensional structure;

For each of the intermediate layers, identifying pixels of the respective intermediate layer corresponding to respective locations at which the dose curve is equal to or greater than a cumulative dose associated with the respective intermediate layer; and

The intermediate layer is rasterized into the frame layers, each of the frame layers being associated with a respective one of the doses.

17. The lithographic method of claim 12, wherein each processing address grid associated with a respective dose is a hexagonal close-packed (HCP) pattern of address locations.

18. The lithographic method of claim 12, wherein the dose is a different binary exponential multiple of a nominal dose.

19. A system for a lithographic process, the system comprising:

a lithography system support;

The image projection system is coupled to the lithography system support and includes an array of pixels;

Iteratively exposing the photoresist supported by the stage, each of the exposures comprising using one or more write beams projected from the image projection system, each of the exposures being at a respective one of different doses, the accumulated dose being a full toner dose for the photoresist as an accumulation of different doses, wherein for each of the exposures, when a center of a respective pixel is aligned with an address location of an address grid within a polygon, one or more of the pixels of the pixel array projects a respective write beam to the photoresist, each of the address grid and the polygon being associated with a respective one of the different doses of a respective exposure, wherein each address grid associated with any of the different doses is a hexagonal close-packed (HCP) pattern of address locations; and

The stage is moved by a step distance relative to the image projection system between sequential pairs of exposures.

20. A lithographic method, comprising:

generating a nominal address grid to be superimposed on the photoresist, the generating the nominal address grid being based on a nominal number of weights and a nominal step for forming full tone features in the photoresist, the generating the nominal address grid further being based on a pixel array;

generating a processing weight by increasing the nominal weight by an integer multiple, a processing stride being a quotient of the nominal stride divided by the integer;

Generating the integer number of treatment address grids based on the nominal address grids, each of the treatment address grids being associated with a respective one of the doses;

generating a recipe based on the processing address grid and the dose; and

Iteratively exposing the photoresist supported by a stage of the lithographic system using an image projection system of the lithographic system, the image projection system comprising the pixel array, each pixel of the pixel array configured to selectively direct a write beam toward the photoresist, a dose of each of the exposures being different from a previous one of the exposures, for each of the exposures, one or more pixels of the pixel array projecting a respective write beam to the photoresist when a center of the respective pixel is aligned with an address location of a processing address grid associated with the respective dose of the respective exposure and when the address location is within a polygon associated with the respective dose of the respective exposure, an accumulation of the doses being a full-color toner amount for forming the full-color tone feature in the photoresist; and

The stage is moved relative to the image projection system by the processing step after the exposure and before a subsequent exposure.

21. A lithographic method, comprising:

iteratively exposing a photoresist supported by a stage of the lithographic system using an image projection system of the lithographic system, the image projection system comprising an array of pixels, each pixel of the array of pixels configured to selectively direct a write beam toward the photoresist, a dose of each of the exposures being different from a previous one of the exposures, for each of the exposures, one or more pixels of the array of pixels projecting a respective write beam to the photoresist when a center of the respective pixel is aligned with an address location of a processing address grid associated with the respective dose of the respective exposure and when the address location is within a polygon associated with the respective dose of the respective exposure, an accumulation of the doses being a full tone dose for forming full tone features in the photoresist, wherein each processing address grid associated with the respective dose is a hexagonal packing (HCP) pattern of address locations; and

The stage is moved relative to the image projection system by a processing step after the exposure and before a subsequent exposure.