CN114553630A - Bus terminal resistor automatic loading and ID self-distribution method and system, equipment, medium and product - Google Patents
Bus terminal resistor automatic loading and ID self-distribution method and system, equipment, medium and product Download PDFInfo
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- CN114553630A CN114553630A CN202210014887.4A CN202210014887A CN114553630A CN 114553630 A CN114553630 A CN 114553630A CN 202210014887 A CN202210014887 A CN 202210014887A CN 114553630 A CN114553630 A CN 114553630A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40019—Details regarding a bus master
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Abstract
The invention provides a bus terminal resistor automatic loading and ID self-distributing system, wherein each device in the system reserves a main interface terminal and a secondary interface terminal, and the secondary interface terminal of the previous device is connected with the main interface terminal of the next device through a communication line, a control detection logic line and a feedback monitoring logic line. The invention relates to an electronic device, a storage medium, and a program product. The invention also relates to a bus terminal resistor automatic loading and ID self-distribution method. The invention can automatically distinguish the two farthest end points, is not influenced by external factors, and realizes the self-allocation of the equipment ID. The invention does not require the user to have professional foundation, does not need to add accessories, is economic and convenient, has no hardware requirement, is beneficial to increasing the market prospect of system-level intelligent application and improving the user experience.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a method, a system, equipment, a medium and a product for automatically loading bus terminal resistors and automatically distributing ID.
Background
For high speed communications (e.g., CAN bus communications, 485 bus communications) with a communication speed of 125kbps to 1Mbps, it is required that there are, and CAN only be, 2 termination resistances of typically 120 ohms, equal to the transmission line impedance, added to the two farthest distant ends of the linear topology within one network (directly connected by a set of cables), as shown in fig. 1.
The industrial application is more in the past, and the first and last equipment is distinguished by people, makes two terminal resistance accessories, and manually inserts on the communication terminal. This requires a professional base for the user and the addition of accessories, which is neither economical nor convenient.
Some schemes for automatically adding a terminal resistor to a system appear in the market later, but certain hard requirements are met, such as no equipment in the system is powered off, no equipment fails to go wrong, and the like, so that the terminal resistor is forcedly removed, and communication paralysis of the whole system is caused.
Moreover, ID assignment also has a great problem, for example, if the 485 communication system is produced in a batch manner, device IDs are definitely overlapped when leaving factory, and ID assignment of the built system is bound to be performed again. When the ID of the devices in the system are the same, if the master wants to acquire data from the slave, all the devices with the same ID respond at the same time and return data, which causes data dislocation and error on the bus and fails to complete the analysis. Even if the host wants to modify the ID, after the host issues the command, the slaves with the same ID will respond at the same time, resulting in the simultaneous modification of the same device ID, and still not meeting the requirement of different device IDs for each device in the system.
Communication of products has higher and higher proportion in actual civil environment, and system level intelligent application has more and more market, and the user probably has no professional basis to it is very much attentive to experience. Therefore, a method for a system to automatically distinguish the two farthest endpoints without being affected by external factors and to implement self-assignment of device IDs is urgently needed.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a bus terminal resistor automatic loading and ID self-distribution method, a system automatically distinguishes two farthest end points, is not influenced by external factors, and realizes the self-distribution of equipment ID.
The invention provides a bus terminal resistor automatic loading and ID self-distribution method, which comprises the following steps:
setting the state, namely setting the output ends of the control detection logic lines of all the devices according to preset configuration;
detecting states, namely detecting the states of the input ends of the control detection logic lines of all the devices;
confirming a first device, and if the state of the input end of a control detection logic line of the device is detected to be different from the set state, confirming the first device, and sending a control signal by the first device through the output end of the control detection logic line;
confirming the last equipment, judging the working state of the next-stage equipment, if the working state is normal, sending a chip selection control signal by the next-stage equipment, controlling the controllable switch to be switched to a detection loop, feeding back a signal to the previous-stage equipment through the output end of the feedback monitoring logic line when the next-stage equipment detects the control signal through the input end of the control detection logic line, simultaneously sending an enabling controller signal, and sending the control signal to the next-stage equipment through the output end of the control detection logic line; if the current is abnormal, the controllable switch is kept in a straight-through loop, the control signal is directly sent to the next-stage equipment through the output end of the control detection logic line, and the feedback signal sent by the next-stage equipment through the output end of the feedback detection logic line is directly transmitted to the previous-stage equipment through the straight-through loop of the next-stage equipment; and circularly executing the step until the input end of the feedback monitoring logic line monitors that no feedback exists, and determining that the terminal equipment is the terminal equipment.
Further, still include:
presetting state, sending control command, presetting the control detection logic line output ends of all devices according to preset configuration;
modifying the ID of the first device, sending an ID modification command, responding and modifying the ID by the first device, sending a control signal by the first device through controlling the output end of the detection logic line, and setting the output end of the control detection logic line to be in a reverse state of a preset state;
modifying the ID of the post-stage equipment, sending an ID modification command, responding and modifying the ID by the equipment which does not modify the ID and controls the state of the input end of the detection logic line to be the reverse state of the preset state, sending a control signal by controlling the output end of the detection logic line, setting the output end of the control detection logic line to be the reverse state of the preset state, and executing the step circularly until the bus has no response.
Further, in the step of setting the state, the output ends of the control detection logic lines of all the devices are pulled low.
Further, in the step of confirming the first device, if the state of the input end of the control detection logic line of the device is detected to be not low level, the first device is confirmed.
Furthermore, in the step of presetting the state, the output ends of the control detection logic lines of all the devices are pulled down; and the step of modifying the ID of the first equipment is to set the output end of the control detection logic line of the first equipment high.
An electronic device, comprising: a processor;
a memory; and a program, wherein the program is stored in the memory and configured to be executed by the processor, the program comprising instructions for performing a bus termination resistance auto-load and ID self-assignment method.
A computer-readable storage medium having stored thereon a computer program for executing by a processor a bus termination resistance auto-loading and ID self-assigning method.
A computer program product comprising computer programs/instructions which, when executed by a processor, implement a bus termination resistance auto-loading and ID self-assignment method.
The system is characterized in that a main interface terminal and a secondary interface terminal are reserved in each device, and the secondary interface terminal of the previous-stage device is connected with the main interface terminal of the next-stage device through a communication line, a control detection logic line and a feedback monitoring logic line.
Furthermore, the system also comprises a controllable switch, a secondary interface terminal of the previous-stage device is connected with the wire inlet end of the controllable switch corresponding to the current device through the control detection logic line, a main interface terminal of the next-stage device is connected with the wire inlet end of the controllable switch corresponding to the current device through the feedback monitoring logic line, the first wire outlet end of the controllable switch corresponding to the current equipment and the enabling end of the current equipment are connected with the wire inlet end of the controllable switch corresponding to the next-stage equipment through the control detection logic line, the second outlet end of the controllable switch corresponding to the current equipment is connected with the current equipment, the coil of the controllable switch corresponding to the current equipment is connected with the chip selection end of the current equipment and the ground, and the first wire outlet end of the controllable switch corresponding to the current equipment and the enabling end of the current equipment are connected with the wire inlet end of the controllable switch corresponding to the previous-stage equipment through the feedback monitoring logic line.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a bus terminal resistor automatic loading and ID self-distribution method, a system can automatically distinguish two farthest end points, is not influenced by external factors, and realizes the self-distribution of equipment ID. The invention does not require the user to have professional foundation, does not need to add accessories, is economic and convenient, has no hardware requirement, is beneficial to increasing the market prospect of system-level intelligent application and improving the user experience.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings. The detailed description of the present invention is given in detail by the following examples and the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of a topology according to the background of the invention;
FIG. 2 is a schematic diagram of an automatic bus termination resistor loading and ID self-distribution system of the present invention;
FIG. 3 is a circuit diagram of the internal circuit of the device connected to the control detection logic according to the embodiment of the present invention;
FIG. 4 is a circuit diagram of the internal circuit of the device to which the feedback monitor logic line is connected according to the embodiment of the present invention;
FIG. 5 is a flow chart of a method for automatically loading bus termination resistors in accordance with the present invention;
FIG. 6 is a flow chart of a bus termination resistance ID self-assignment method of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that any combination of the embodiments or technical features described below can be used to form a new embodiment without conflict.
As shown in fig. 2, each device in the system reserves a Primary interface terminal (Primary) and a Secondary interface terminal (Secondary), the Secondary interface terminal of the previous device is connected with the Primary interface terminal of the next device through a Communication Line (Communication Line) and a Logic Line (Logic Line), and the Logic Line includes a control detection Logic Line and a feedback monitoring Logic Line. Adopt the mode of hand-in-hand to link: secondary _1-Primary _2-Secondary _2-Primary _3-Secondary _3- · Primary _ n. And the confirmation of the positions of the devices is realized by controlling and monitoring signals of the two logic lines.
In one embodiment, the system also comprises a controllable switch, the secondary interface terminal of the previous stage device is connected with the wire inlet terminal of the controllable switch corresponding to the current device through a control detection logic line, the primary interface terminal of the next stage device is connected with the wire inlet terminal of the controllable switch corresponding to the current device through a feedback monitoring logic line, the first wire outlet end of the controllable switch corresponding to the current equipment and the enabling end of the current equipment are connected with the wire inlet end of the controllable switch corresponding to the next-stage equipment through the control detection logic line, the second outlet end of the controllable switch corresponding to the current equipment is connected with the current equipment, the coil of the controllable switch corresponding to the current equipment is connected with the chip selection end of the current equipment and the ground, and the first wire outlet end of the controllable switch corresponding to the current equipment and the enabling end of the current equipment are connected with the wire inlet end of the controllable switch corresponding to the previous-stage equipment through the feedback monitoring logic line.
As shown in fig. 3, the enable terminal EN1 of the first device MCU1 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded via the resistor R2, the collector of the transistor Q1 is connected to the 3.3V power supply via the resistor R1, the junction of the emitter of the transistor Q1 and the resistor R2 is connected to the input terminal of the controllable switch corresponding to the second device via the control detection logic line, the first output terminal of the controllable switch corresponding to the second device is connected to the input terminal of the controllable switch corresponding to the third device via the control detection logic line, the loop connected to the first output terminal of the controllable switch is a through loop, the second output terminal of the controllable switch corresponding to the second device MCU2 is connected to the input terminal of the second device MCU2, the loop connected to the second output terminal of the controllable switch is a detection loop, the chip select terminal CS of the second device MCU2 is connected to one end of the coil of the controllable switch, and the other end of the coil of the controllable switch is grounded, the enabling end EN2 of the second device MCU2 is connected with the base of a triode Q2, the emitter of the triode Q2 is grounded through a resistor R4, the collector of the triode Q2 is connected with a 3.3V power supply through a resistor R3, the connection position of the emitter of the triode Q2 and the resistor R4 is connected with the incoming line end of a controllable switch corresponding to the third device through a control detection logic line, and the connection of the later-stage devices is analogized in turn. Logic Line _ T _ IN (T ═ 1,2,3.. n) mainly serves to determine whether or not it is the first station and whether or not there is a device ahead.
As shown in fig. 4, the enable terminal EN2 of the third MCU3 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected to the 3.3V power supply through the resistor R1, the junction of the collector of the transistor Q1 and the resistor R1 is connected to the incoming line terminal of the controllable switch corresponding to the second device through the feedback monitoring logic line, the first outgoing line terminal of the controllable switch corresponding to the second device is connected to the incoming line terminal of the controllable switch corresponding to the first device through the feedback monitoring logic line, the loop connected to the first outgoing line terminal of the controllable switch is a through loop, the second outgoing line terminal of the controllable switch corresponding to the second device is connected to the input terminal of the second MCU2, the loop connected to the second outgoing line terminal of the controllable switch is a detection loop, the chip select terminal CS of the second MCU2 is connected to one end of the coil of the controllable switch, the other end of the controllable switch is grounded, the enabling end EN1 of the second device MCU2 is connected with the base electrode of a triode Q2, the emitting electrode of the triode Q2 is grounded, the collecting electrode of the triode Q2 is connected with a 3.3V power supply through a resistor R3, the connecting part of the collecting electrode of the triode Q2 and the resistor R3 is connected with the incoming line end of a controllable switch corresponding to the first device through a feedback monitoring logic line, and the connection of the later-stage devices is analogized in sequence. The condition for judging whether the self is the last one is as follows: sending a feedback signal through Logic Line _ T _ feedback (T ═ 1,2,3.. n), and if feedback is monitored, determining that the feedback is not the last one, and if no feedback is monitored, determining that the feedback is the last one.
As shown in fig. 5, the method for automatically loading bus termination resistors and automatically loading ID self-distribution system bus termination resistors includes the following steps:
and setting the state, namely setting the control detection logic line output ends of all the devices according to preset configuration. In this embodiment, the control detection Logic Line output terminals of all devices are pulled low, that is, all Logic Line _ T _ OUT (T ═ 1,2,3.. n) in fig. 3 are pulled low (device default pull-low). It should be understood that the state of the control sense logic line output may be set as appropriate.
And detecting the state, namely detecting the state of the input end of the control detection Logic Line of all the devices, namely detecting the state of Logic Line _ T _ IN (T is 1,2,3.. n).
The first device is confirmed, if it is detected that the state of the control detection logic line input end of the device is different from the set state, in this embodiment, if it is detected that the state of the control detection logic line input end of the device is a non-low level, it is confirmed that the first device is the device, and the first device sends the control signal through the control detection logic line output end. When detecting that the Logic Line _ T _ IN (T ═ 1,2,3.. n) is a device with a non-low level, determining that the device is the first device, and sending a control signal by the first device through the Logic Line _1_ OUT.
Confirming the last equipment, judging the working state of the next-stage equipment, if the working state is normal, sending a chip selection control signal by the next-stage equipment, controlling the controllable switch to be switched to a detection loop, feeding back a signal to the previous-stage equipment through the output end of the feedback monitoring logic line when the next-stage equipment detects the control signal through the input end of the control detection logic line, simultaneously sending an enabling controller signal, and sending the control signal to the next-stage equipment through the output end of the control detection logic line; if the current is abnormal, the controllable switch is kept in a straight-through loop, the control signal is directly sent to the next-stage equipment through the output end of the control detection logic line, and the feedback signal sent by the next-stage equipment through the output end of the feedback detection logic line is directly transmitted to the previous-stage equipment through the straight-through loop of the next-stage equipment; and circularly executing the step until the input end of the feedback monitoring logic line monitors that no feedback exists, and determining that the terminal equipment is the terminal equipment.
If the second device IN fig. 3 and 4 is IN a normal working state, the MCU2 of the second device sends a chip selection control signal CS to control the controllable switch to switch IN the detection loop, and the MCU2 of the second device detects the control signal through the Logic Line _2_ IN, and then sends a feedback signal to the previous device through the Logic Line _2_ feedback, and sends an enable controller signal EN to send a control signal to the third device through the Logic Line _2_ OUT. And sequentially circulating until no feedback is monitored by the Logic Line _ n _ test, automatically distinguishing two farthest end points, and finishing the automatic loading of the terminal resistor.
If the second device in fig. 3 and 4 is in an abnormal operating state (power off, shutdown, failure, etc.), the MCU2 of the second device cannot send the chip select control signal CS, the controllable switch is kept in the through loop, and the control signal of the preceding device is directly transmitted to the third device through the Logic Line _2_ OUT, so as to automatically complete the filtering of the abnormal operating state machine, and the feedback signal is the same, and the Logic Line _3_ feedback signal of the third device is directly transmitted to the first device through the through loop of the second device, so as to finally complete the distinguishing of the farthest end point and the automatic loading of the terminal resistance.
The automatic loading of the bus termination resistance and the automatic ID distribution method of the bus termination resistance corresponding to the distribution system cooperate the distribution equipment ID command with the logic line level for use, for example, only the equipment which detects non-low level can execute the command of modifying the equipment ID. As shown in fig. 6, the method comprises the following steps:
presetting the state, and before distributing the equipment ID, the host sends a control command to preset the control detection logic line output ends of all the equipment according to the preset configuration. In this embodiment, the output ends of the control detection logic lines of all the devices are pulled low. Logic lines of Logic Line _ T _ OUT (T ═ 1,2,3.. n) of all devices in fig. 3 are pulled low. It should be understood that the control detection logic line outputs of all devices may be set high, and the determination levels of the detection signals may be inverted.
And modifying the ID of the first device, wherein only the Logic Line _1_ IN of the first device detects that the ID is high level or suspended, after the host sends an ID modification command, only the first device responds and modifies the ID, and after the configuration of the first device is finished, the output end of the control detection Logic Line is set to be IN a reverse state of a preset state by sending a control signal through the output end of the control detection Logic Line. In this embodiment, the output terminal of the control detection logic line of the first device is set high. I.e., Logic Line _1_ OUT Logic Line in fig. 3 is set high.
Modifying the ID of the post-stage equipment, sending an ID modification command, responding and modifying the ID by the equipment which does not modify the ID and controls the state of the input end of the detection logic line to be the reverse state of the preset state, sending a control signal by controlling the output end of the detection logic line, setting the output end of the control detection logic line to be the reverse state of the preset state, and executing the step circularly until the bus has no response. At this time, only Logic Line _1_ IN and Logic Line _2_ IN fig. 3 detect non-low level, and because the ID of the first device has been modified, only the second device will respond and modify the device ID without responding, and the automatic ID assignment to all devices is completed IN turn.
An electronic device, comprising: a processor;
a memory; and a program, wherein the program is stored in the memory and configured to be executed by the processor, the program comprising instructions for performing the bus termination resistance auto-load and ID self-assignment method.
A computer-readable storage medium having stored thereon a computer program for executing a bus termination resistance auto-loading and ID self-assignment method by a processor.
A computer program product comprising computer programs/instructions which, when executed by a processor, implement a bus termination resistance auto-loading and ID self-assignment method.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner; those skilled in the art can readily practice the invention as shown and described in the drawings and detailed description herein; however, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the scope of the invention as defined by the appended claims; meanwhile, any changes, modifications, and evolutions of the equivalent changes of the above embodiments according to the actual techniques of the present invention are still within the protection scope of the technical solution of the present invention.
Claims (10)
1. The automatic loading and ID self-distribution method of the bus terminal resistor is characterized by comprising the following steps:
setting the state, namely setting the output ends of the control detection logic lines of all the devices according to preset configuration;
detecting states, namely detecting the states of the input ends of the control detection logic lines of all the devices;
confirming a first device, and if the state of the input end of a control detection logic line of the device is detected to be different from the set state, confirming the first device, and sending a control signal by the first device through the output end of the control detection logic line;
confirming the last equipment, judging the working state of the next-stage equipment, if the working state is normal, sending a chip selection control signal by the next-stage equipment, controlling the controllable switch to be switched to a detection loop, feeding back a signal to the previous-stage equipment through the output end of the feedback monitoring logic line when the next-stage equipment detects the control signal through the input end of the control detection logic line, simultaneously sending an enabling controller signal, and sending the control signal to the next-stage equipment through the output end of the control detection logic line; if the current is abnormal, the controllable switch is kept in a straight-through loop, the control signal is directly sent to the next-stage equipment through the output end of the control detection logic line, and the feedback signal sent by the next-stage equipment through the output end of the feedback detection logic line is directly transmitted to the previous-stage equipment through the straight-through loop of the next-stage equipment; and circularly executing the step until the input end of the feedback monitoring logic line monitors that no feedback exists, and determining that the terminal equipment is the terminal equipment.
2. The method for automatically loading bus termination resistors and self-assigning IDs as claimed in claim 1, further comprising:
presetting state, sending control command, presetting the control detection logic line output ends of all devices according to preset configuration;
modifying the ID of the first device, sending an ID modification command, responding and modifying the ID by the first device, sending a control signal by the first device through controlling the output end of the detection logic line, and setting the output end of the control detection logic line to be in a reverse state of a preset state;
modifying the ID of the post-stage equipment, sending an ID modification command, responding and modifying the ID by the equipment which does not modify the ID and controls the state of the input end of the detection logic line to be the reverse state of the preset state, sending a control signal by controlling the output end of the detection logic line, setting the output end of the control detection logic line to be the reverse state of the preset state, and executing the step circularly until the bus has no response.
3. The method for automatically loading and automatically distributing ID in bus termination resistors as claimed in claim 2, wherein: in the step of setting the state, the output ends of the control detection logic lines of all the devices are pulled low.
4. The method for automatically loading and automatically distributing ID of bus termination resistor as claimed in claim 3, wherein: in the step of confirming the first device, if the state of the input end of the control detection logic line of the device is detected to be non-low level, the first device is confirmed.
5. The method for automatically loading and automatically distributing ID of bus termination resistor as claimed in claim 4, wherein: in the step of presetting the state, the output ends of the control detection logic lines of all the devices are pulled down; and the step of modifying the ID of the first equipment is to set the output end of the control detection logic line of the first equipment high.
6. An electronic device, characterized by comprising: a processor;
a memory; and a program, wherein the program is stored in the memory and configured to be executed by the processor, the program comprising instructions for carrying out the method according to any one of claims 1-5.
7. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program is executed by a processor for performing the method according to any of claims 1-5.
8. A computer program product comprising computer programs/instructions, characterized in that the computer programs/instructions, when executed by a processor, implement the method according to any of claims 1-5.
9. A bus termination resistor auto-loading and ID self-distribution system implementing the method of any of claims 1-5, characterized by: a main interface terminal and a secondary interface terminal are reserved in each device in the system, and the secondary interface terminal of the previous-stage device is connected with the main interface terminal of the next-stage device through a communication line, a control detection logic line and a feedback monitoring logic line.
10. The bus termination resistor auto-loading and ID self-dispensing system of claim 9, wherein: the secondary interface terminal of the previous stage device is connected with the wire inlet end of the controllable switch corresponding to the current device through the control detection logic wire, the primary interface terminal of the next stage device is connected with the wire inlet end of the controllable switch corresponding to the current device through the feedback monitoring logic wire, the first wire outlet end of the controllable switch corresponding to the current equipment and the enabling end of the current equipment are connected with the wire inlet end of the controllable switch corresponding to the next-stage equipment through the control detection logic line, the second outlet end of the controllable switch corresponding to the current equipment is connected with the current equipment, the coil of the controllable switch corresponding to the current equipment is connected with the chip selection end of the current equipment and the ground, and the first wire outlet end of the controllable switch corresponding to the current equipment and the enabling end of the current equipment are connected with the wire inlet end of the controllable switch corresponding to the previous-stage equipment through the feedback monitoring logic line.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210014887.4A CN114553630A (en) | 2022-01-07 | 2022-01-07 | Bus terminal resistor automatic loading and ID self-distribution method and system, equipment, medium and product |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210014887.4A CN114553630A (en) | 2022-01-07 | 2022-01-07 | Bus terminal resistor automatic loading and ID self-distribution method and system, equipment, medium and product |
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| CN114553630A true CN114553630A (en) | 2022-05-27 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115277290A (en) * | 2022-07-16 | 2022-11-01 | 超同步股份有限公司 | Automatic sequential numbering circuit and method for devices connected to field bus |
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2022
- 2022-01-07 CN CN202210014887.4A patent/CN114553630A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115277290A (en) * | 2022-07-16 | 2022-11-01 | 超同步股份有限公司 | Automatic sequential numbering circuit and method for devices connected to field bus |
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