CN114553325A - Gaussian channel simulation circuit and method - Google Patents

Gaussian channel simulation circuit and method Download PDF

Info

Publication number
CN114553325A
CN114553325A CN202210033259.0A CN202210033259A CN114553325A CN 114553325 A CN114553325 A CN 114553325A CN 202210033259 A CN202210033259 A CN 202210033259A CN 114553325 A CN114553325 A CN 114553325A
Authority
CN
China
Prior art keywords
function value
value memory
function
trigger unit
random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210033259.0A
Other languages
Chinese (zh)
Inventor
付祥旭
王家豪
李盈玉
陈振兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China University of Geosciences
Original Assignee
China University of Geosciences
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by China University of Geosciences filed Critical China University of Geosciences
Priority to CN202210033259.0A priority Critical patent/CN114553325A/en
Publication of CN114553325A publication Critical patent/CN114553325A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/0082—Monitoring; Testing using service channels; using auxiliary channels
    • H04B17/0087—Monitoring; Testing using service channels; using auxiliary channels using auxiliary channels or channel simulators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/30—Monitoring; Testing of propagation channels
    • H04B17/391—Modelling the propagation channel
    • H04B17/3912—Simulation models, e.g. distribution of spectral power density or received signal strength indicator [RSSI] for a given geographic region

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to the field of electronic circuits, and provides a Gaussian channel simulation circuit and a Gaussian channel simulation method, wherein the Gaussian channel simulation circuit comprises the following steps: the device comprises a calculation module, a linear feedback shift register unit, a first F function value memory, a second F function value memory, a third F function value memory, a fourth F function value memory, a fifth F function value memory, a multiplexer, a G function value memory, an FG multiplier, a sign inverter and an iterative accumulator. The invention has the characteristics of strong real-time performance, high reliability and simple structure; meanwhile, the signal-to-noise ratio can be conveniently adjusted, random numbers obeying Gaussian distribution are generated in real time, and the task of adding noise to input is achieved.

Description

Gaussian channel simulation circuit and method
Technical Field
The invention relates to the field of electronic circuits, in particular to a Gaussian channel simulation circuit and a Gaussian channel simulation method.
Background
Channel simulators are necessary tools to study the performance of a communication system. In the process of researching the error code performance of the related algorithm of the transmitter and the receiver system, if the test is carried out in the actual channel environment, on one hand, the test cost is higher, and on the other hand, the channel environment is changed in real time, which is not beneficial to analyzing the result. For the research of the channel simulator, the channel simulator in the prior art has complex design and low real-time performance. In order to meet the sampling point generation rate of high-speed system test, the generation rate requirement is often met by means of packing logic. For the structural optimization of the simulator for gaussian channels, there is relatively little research on correlation.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
To solve the above problem, the present invention provides a gaussian channel simulation circuit, comprising: the device comprises a calculation module, a linear feedback shift register unit, a first F function value memory, a second F function value memory, a third F function value memory, a fourth F function value memory, a fifth F function value memory, a multiplexer, a G function value memory, an FG multiplier, a sign inverter and an iterative accumulator;
the linear feedback shift register unit comprises a plurality of LFSR registers;
the calculation module is electrically connected with the first F function value memory, the second F function value memory, the third F function value memory, the fourth F function value memory, the fifth F function value memory and the G function value memory;
the linear feedback shift register unit is electrically connected with the calculation module, the first F function value memory, the second F function value memory, the third F function value memory, the fourth F function value memory, the fifth F function value memory, the G function value memory and the sign inverter;
the first F function value memory, the second F function value memory, the third F function value memory, the fourth F function value memory, and the fifth F function value memory are all electrically connected to the multiplexer, the multiplexer is electrically connected to the FG multiplier, the FG multiplier is electrically connected to the G function value memory and the sign inverter, and the sign inverter is electrically connected to the iterative accumulator.
Preferably, the LFSR register includes: the trigger comprises a first trigger unit, a second trigger unit, a third trigger unit, a fourth trigger unit and a fifth trigger unit;
the first trigger unit, the second trigger unit and the fifth trigger unit are connected in series;
the second trigger unit, the third trigger unit, the fourth trigger unit and the fifth trigger unit are connected in parallel;
the first trigger unit includes: the trigger is connected with the adder in series;
the second trigger unit includes: a trigger;
the third trigger unit includes: the trigger is connected with the adder in series;
the fourth trigger unit includes: the trigger is connected with the adder in series;
the fifth trigger unit includes: the trigger is connected with the adder in series.
Preferably, the reading addresses of the first F function value memory, the second F function value memory, the third F function value memory, the fourth F function value memory and the fifth F function value memory are all 4-bit binary numbers, the output F function values are all 9-bit binary numbers, the decimal place is 7 bits, and the integer place is 2 bits.
Preferably, the reading address of the G function value memory is an 8-bit binary number, the output G function value is an 8-bit binary number, wherein the decimal place is 7 bits, and the integer place is 1 bit.
Preferably, the result of the multiplication output by the FG multiplier is a 9-bit binary number, where the decimal place is 6 bits and the integer is 3 bits.
Preferably, the sign inverter assigns a random sign to the multiplication result output from the FG multiplier.
A Gaussian channel simulation method is realized based on the Gaussian channel simulation circuit and comprises the following steps:
s1: the linear feedback shift register unit provides reading addresses for the calculation unit, the first F function value memory, the second F function value memory, the third F function value memory, the fourth F function value memory, the fifth F function value memory, the sign inverter and the G function value memory;
s2: the linear feedback shift register unit generates a first random variable x1iAnd a second random variable x2iI is the generation number of the random variable, i is a positive integer from 1 to p, and p is the total generation number of the random variable; the linear feedback shift register unit converts a first random variable x into a second random variable x1iAnd a second random variable x2iTransmitting to a calculation module through a first random variable x1iCalculating to obtain F function value, and obtaining the value by a second random variable x2iCalculating to obtain a G function value;
s3: the calculation module stores the F function values into a first F function value memory to a fifth F function value memory in sequence according to the running time, and stores the G function values into a G function value memory;
s4: the multiplexer extracts the F function values from the first F function value memory to the fifth F function value memory in sequence according to the running time and transmits the F function values to the FG multiplier; the G function value memory transmits the G function value to the FG multiplier;
s5: FG multiplier multiplies F function value and G function value to obtain multiplication result ni；
S6: FG multiplier multiplies result niThe multiplication result with the symbol is transmitted to a symbol inverter for symbol addition to obtain a multiplication result with the symbol, and the multiplication result with the symbol is transmitted to an iteration accumulator for storage;
s7: repeating the steps S2-S6 p times, and accumulating the signed multiplication results obtained p times by the iterative accumulator to obtain an output result.
Preferably, step S2 specifically includes:
s21: by a first random variable x1iF function value F (x) is obtained by calculation1i) The calculation formula is as follows:
Figure BDA0003467276730000031
the expression of the simulation model fr(s) of the F function value is:
Figure BDA0003467276730000032
Fr(0)＝0
wherein r is a random integer ranging from 1 to K, K is a positive integer greater than 1; m is a first scaling factor; s is a random integer varying within the range of [1,15 ]; delta is a random real number uniformly distributed within the interval [0,1 ]; r represents a quantization function;
s22: by a second random variable x2iG function value G (x) is obtained by calculation2i) The calculation formula is as follows:
Figure BDA0003467276730000033
the expression of the simulation model G (s') of the G function value is as follows:
Figure BDA0003467276730000034
wherein m ' is a second scaling factor, s ' is a random integer varying within the range of [1,255], δ ' is a random real number uniformly distributed within the interval [0,1], and R represents a quantization function.
Preferably, in step S5, the multiplication result niThe calculation formula of (c) is:
ni＝f(x1i)g(x2i)
wherein, f (x)1i) Is the ith F function value, g (x)2i) Is the ith G function value;
multiplication result niIs simulated by the simulation model RniThe expression of (a) is:
Rni＝(1-2*sign)*P(r,s,s′)-sign
wherein P (r, s, s ') is a normalized function of the Gaussian channel power amplitude, sign is a sign function, r is a random integer varying in the range of 1 to K, s is a random integer varying in the range of [1,15], and s' is a random integer varying in the range of [1,255 ].
The invention has the following beneficial effects:
the channel simulator can reduce the test cost and provide a stable channel meeting specific statistical characteristics for the test. The optimized Gaussian channel simulator logic circuit has the characteristics of strong real-time performance, high reliability and simple structure; meanwhile, the signal-to-noise ratio can be conveniently adjusted, random numbers obeying Gaussian distribution are generated in real time, and the task of adding noise to input is achieved.
Drawings
FIG. 1 is a block diagram of the system of the present invention;
FIG. 2 illustrates an internal structure of a conventional LFSR register;
FIG. 3 is an internal structure of an improved LFSR register;
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the present invention provides a gaussian channel simulation circuit, including: a calculation module, a linear feedback shift register unit 11, a first F function value memory 21, a second F function value memory 22, a third F function value memory 23, a fourth F function value memory 24, a fifth F function value memory 25, a multiplexer 26, a G function value memory 31, an FG multiplier 41, a sign inverter 51, and an iterative accumulator 61;
the linear feedback shift register unit 11 includes a plurality of LFSR registers;
the calculation module is electrically connected to the first F function value memory 21, the second F function value memory 22, the third F function value memory 23, the fourth F function value memory 24, the fifth F function value memory 25, and the G function value memory 31;
the linear feedback shift register unit 11 is electrically connected to the calculation module, the first F function value memory 21, the second F function value memory 22, the third F function value memory 23, the fourth F function value memory 24, the fifth F function value memory 25, the G function value memory 31, and the sign inverter 51;
said first F function value memory 21, said second F function value memory 22, said third F function value memory 23, said fourth F function value memory 24, and said fifth F function value memory 25 are all electrically connected to said multiplexer 26, said multiplexer 26 is electrically connected to said FG multiplier 41, said FG multiplier 41 is electrically connected to said G function value memory 31 and said sign inverter 51, and said sign inverter 51 is electrically connected to said iterative accumulator 61;
specifically, the calculation module is used for calculating to obtain an F function value and a G function value, the calculation function of the calculation module is realized through an FPGA, 5 Xilinx IP cores blk _ mem _ gen are used for storing the F function value, the reading address is 4 bits, and the data size is 9 bits; storing a G function value by adopting 1 Xilinx IP core blk _ mem _ gen, wherein the reading address is 8 bits, and the data size is 8 bits; the read addresses are from the linear feedback shift register unit 11 and correspond to the read addresses of the G function value memory 31 and the first to fifth F function value memories 21 to 25; five F function values and a G function value are obtained by calculation in five clock cycles respectively, the five F function values are stored in a first F function value memory 21 to a fifth F function value memory 25 respectively, and the G function value is stored in a G function value memory 31;
the linear feedback shift register unit 11 is configured to generate a random sequence that is in accordance with uniform distribution, and use the random sequence as a read address of the calculation module, the first to fifth F function value memories 21 to 25, the G function value memory 31, and the sign inverter 51 for address lookup;
the first to fifth F function value memories 21 to 25 are configured to store corresponding F function values according to the number of times the random variable is generated by the calculation module;
the multiplexer 26 is configured to retrieve corresponding stored values from the first F function value memory 21 to the fifth F function value memory 25 according to the number of times the random variable is generated by the calculation module;
a G function value memory 31 for storing G function values;
FG multiplier 41 is used for multiplying F function value and G function value to obtain multiplication result ni；
The sign inverter 51 is used for giving the multiplication result niGiving a random symbol to obtain a signed multiplication result;
the iterative accumulator 61 is configured to accumulate signed multiplication results obtained multiple times to obtain an output result.
Referring to fig. 2, the LFSR register in the prior art has a linear connection structure inside, including: flip-flop 311, flip-flop 312, flip-flop 313, flip-flop 314, flip-flop 315, and adder 321;
the flip-flop 311 is connected to the flip-flop 312, the flip-flop 312 is connected to the adder 321, the adder 321 is connected to the flip-flop 313, the flip-flop 313 is connected to the flip-flop 314, and the flip-flop 314 is connected to the flip-flop 315; the LFSR register with the structure generates a read address every 4 clock cycles, and the problem that the read address generation speed is too slow exists.
Referring to fig. 3, to solve this problem, the present invention provides an improved linear feedback shift register unit 11;
if the linear feedback shift register unit 11 has u LFSR registers, the generated random sequence has 2uSeed combination; after the reset is completed, the LFSR register must be initialized to a value different from "00000", otherwise the LFSR register will remain at this value; the u random sequences do not need to be generated by u LFSR registers, and the number of LSFR registers can be reduced by grouping; the read addresses are grouped into 4 groups, and only 7 LSFR registers are needed, 2 of them are provided to the G function value memory 31, 4 are provided to the first to fifth F function value memories 21 to 25, and 1 is provided to the sign inverter 51; the read addresses provided to the calculation module correspond to the read addresses of the G function value memory 31 and the first to fifth F function value memories 21 to 25;
the LFSR register includes: the trigger comprises a first trigger unit, a second trigger unit, a third trigger unit, a fourth trigger unit and a fifth trigger unit;
the first trigger unit, the second trigger unit and the fifth trigger unit are connected in series;
the second trigger unit, the third trigger unit, the fourth trigger unit and the fifth trigger unit are connected in parallel;
the first trigger unit includes: a flip-flop 211 and an adder 221, the flip-flop 211 being connected in series with the adder 221;
the second trigger unit includes: a flip-flop 212;
the third trigger unit includes: a flip-flop 213 and an adder 222, the flip-flop 213 being connected in series with the adder 222;
the fourth trigger unit includes: a flip-flop 214 and an adder 223, the flip-flop 214 being connected in series with the adder 223;
the fifth trigger unit includes: a flip-flop 215 and an adder 224, the flip-flop 215 being connected in series with the adder 224;
in particular, the method comprises the following steps of,
given an initial value, a random sequence w is generated every 4 clock cycles in the linear feedback shift register unit 11, with irreducible polynomial y ═ w5+w2+1 calculation yields a binary random number y of 1bit, where w5＝w(t-4)+w4(t-4), t being the clock period;
and y is simultaneously output in parallel through the output port 231, the output port 232, the output port 233 and the output port 234, the operation is executed once every four clock cycles, four times of virtual conversion can be completed in one clock cycle, a 4-bit reading address is obtained, and the clock cycle is saved.
In the present invention, the reading addresses of the first F function value memory 21, the second F function value memory 22, the third F function value memory 23, the fourth F function value memory 24, and the fifth F function value memory 25 are all 4-bit binary numbers, and the output F function values are all 9-bit binary numbers, where the decimal place is 7 bits, and the integer place is 2 bits;
specifically, the first F function value memory 21, the second F function value memory 22, the third F function value memory 23, the fourth F function value memory 24, and the fifth F function value memory 25 all use a RAM core having a depth of 16, an address bit width is 4, a data bit width is 9, and the F function values stored in these five F function value memories are different.
In the present invention, the reading address of the G function value memory 31 is an 8-bit binary number, the output G function value is an 8-bit binary number, wherein the decimal place is 7 bits, and the integer place is 1 bit;
specifically, the G function value memory 31 uses a RAM core with a depth of 256, an address bit width of 8, and a data bit width of 8.
In the present invention, the multiplication result output by the FG multiplier 41 is a 9-bit binary number, where the decimal place is 6 bits and the integer is 3 bits.
In the present invention, the sign inverter 51 gives a random sign to the multiplication result output from the FG multiplier 41.
The invention provides a Gaussian channel simulation method which is realized based on the Gaussian channel simulation circuit and is characterized by comprising the following steps:
s1: the linear feedback shift register unit 11 provides a read address to the calculation unit, the first F function value memory 21, the second F function value memory 22, the third F function value memory 23, the fourth F function value memory 24, the fifth F function value memory 25, the sign inverter 51, and the G function value memory 31;
s2: the linear feedback shift register unit 11 generates a first random variable x1iAnd a second random variable x2iI is the generation number of the random variable, i is a positive integer from 1 to p, and p is the total generation number of the random variable; the linear feedback shift register unit 11 converts the first random variable x1iAnd a second random variable x2iTransmitted to a calculation module by a first random variable x1iF function value is obtained through calculation, and the second random variable x is used2iCalculating to obtain a G function value;
in particular, a first random variable x1iIs at [0,1]]Interval complianceUniformly distributed random number, second random variable x2iIs also in [0,1]]Random numbers with uniformly distributed intervals;
s3: the calculation module stores the F function values in the first F function value memory 21 to the fifth F function value memory 25 in sequence according to the running time, and stores the G function values in the G function value memory 31;
s4: the multiplexer 26 sequentially extracts the F function values from the first to fifth F function value memories 21 to 25 in accordance with the operation time, and transmits the F function values to the FG multiplier 41; the G function value memory 31 transmits the G function value to the FG multiplier 41;
s5: FG multiplier 41 multiplies F function value and G function value to obtain multiplication result ni；
S6: FG multiplier 41 multiplies result niThe symbol is transmitted to a symbol inverter 51 for adding symbols, so that a signed multiplication result is obtained, and the signed multiplication result is transmitted to an iteration accumulator 61 for storage;
s7: repeating the steps S2-S6 p times, and accumulating the signed multiplication results obtained p times by the iterative accumulator 61 to obtain an output result; the value of p is preferably set to 4, resulting in an output of a 12bit binary number, where the fractional bits are 6 bits and the integer bits are 6 bits.
In the present invention, step S2 specifically includes:
s21: by a first random variable x1iF function value F (x) is obtained by calculation1i) The calculation formula is as follows:
Figure BDA0003467276730000081
the expression of the simulation model fr(s) of the F function value is:
Figure BDA0003467276730000082
Fr(0)＝0
wherein r is a random integer ranging from 1 to K, K is a positive integer greater than 1; m is a first scaling factor; s is a random integer varying within the range of [1,15 ]; delta is a random real number uniformly distributed within the interval [0,1 ]; r represents a quantization function;
specifically, the value of k is preferably set to 5, and the value of m is preferably set to 7;
s22: by a second random variable x2iG function value G (x) is obtained by calculation2i) The calculation formula is as follows:
Figure BDA0003467276730000083
the expression of the simulation model G (s') of the G function value is as follows:
Figure BDA0003467276730000084
wherein m ' is a second scaling factor, s ' is a random integer varying within the range of [1,255], δ ' is a random real number uniformly distributed within the interval [0,1], and R represents a quantization function;
specifically, the value of m' is preferably set to 7.
In the present invention, in step S5, the multiplication result niThe calculation formula of (c) is:
ni＝f(x1i)g(x2i)
wherein, f (x)1i) Is the ith F function value, g (x)2i) Is the ith G function value;
multiplication result niIs simulated by the simulation model RniThe expression of (a) is:
Rni＝(1-2*sign)*P(r,s,s′)-sign
wherein P (r, s, s ') is a normalized function of the Gaussian channel power amplitude, sign is a sign function, r is a random integer varying in the range of 1 to K, s is a random integer varying in the range of [1,15], and s' is a random integer varying in the range of [1,255 ].
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third and the like do not denote any order, but rather the words first, second and the like may be interpreted as indicating any order.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (9)

1. A gaussian channel simulation circuit, comprising: the device comprises a calculation module, a linear feedback shift register unit (11), a first F function value memory (21), a second F function value memory (22), a third F function value memory (23), a fourth F function value memory (24), a fifth F function value memory (25), a multiplexer (26), a G function value memory (31), an FG multiplier (41), a sign inverter (51) and an iteration accumulator (61);
the linear feedback shift register unit (11) comprises a plurality of LFSR registers;
the calculation module is electrically connected with the first F function value memory (21), the second F function value memory (22), the third F function value memory (23), the fourth F function value memory (24), the fifth F function value memory (25) and the G function value memory (31);
the linear feedback shift register unit (11) is electrically connected to the calculation module, the first F function value memory (21), the second F function value memory (22), the third F function value memory (23), the fourth F function value memory (24), the fifth F function value memory (25), the G function value memory (31), and the sign inverter (51);
the first F function value memory (21), the second F function value memory (22), the third F function value memory (23), the fourth F function value memory (24), and the fifth F function value memory (25) are all electrically connected to the multiplexer (26), the multiplexer (26) is electrically connected to the FG multiplier (41), the FG multiplier (41) is electrically connected to the G function value memory (31) and the sign inverter (51), and the sign inverter (51) is electrically connected to the iteration accumulator (61).
2. The gaussian channel simulation circuit of claim 1, wherein the LFSR register comprises: the trigger comprises a first trigger unit, a second trigger unit, a third trigger unit, a fourth trigger unit and a fifth trigger unit;
the first trigger unit, the second trigger unit and the fifth trigger unit are connected in series;
the second trigger unit, the third trigger unit, the fourth trigger unit and the fifth trigger unit are connected in parallel;
the first trigger unit includes: a flip-flop (211) and an adder (221), the flip-flop (211) being connected in series with the adder (221);
the second trigger unit includes: a trigger (212);
the third trigger unit includes: a flip-flop (213) and an adder (222), the flip-flop (213) being connected in series with the adder (222);
the fourth trigger unit includes: a flip-flop (214) and an adder (223), the flip-flop (214) being connected in series with the adder (223);
the fifth trigger unit includes: a flip-flop (215) and an adder (224), the flip-flop (215) being connected in series with the adder (224).
3. The gaussian channel simulation circuit according to claim 1, wherein the first F-function value memory (21), the second F-function value memory (22), the third F-function value memory (23), the fourth F-function value memory (24) and the fifth F-function value memory (25) have read addresses of 4-bit binary numbers, and output F-function values of 9-bit binary numbers, wherein the decimal place is 7 bits and the integer digit is 2 bits.
4. A gaussian channel simulation circuit according to claim 1 wherein the read address of the G-function value memory (31) is an 8-bit binary number and the output G-function value is an 8-bit binary number, wherein the small number bit is 7 bits and the integer number bit is 1 bit.
5. Gaussian channel simulation circuit according to claim 1, wherein the result of the multiplication output by the FG multiplier (41) is a 9-bit binary number, where the decimal place is 6 bits and the integer is 3 bits.
6. Gaussian channel simulation circuit according to claim 1, characterized in that the sign inverter (51) assigns random signs to the multiplication results output by the FG multiplier (41).
7. A gaussian channel simulation method implemented based on a gaussian channel simulation circuit according to any one of claims 1-6, comprising:
s1: a linear feedback shift register unit (11) provides a read address for the calculation unit, a first F function value memory (21), a second F function value memory (22), a third F function value memory (23), a fourth F function value memory (24), a fifth F function value memory (25), a sign inverter (51), and a G function value memory (31);
s2: the linear feedback shift register unit (11) generates a first random variable x1iAnd a second random variationQuantity x2iI is the generation number of the random variable, i is a positive integer from 1 to p, and p is the total generation number of the random variable; the linear feedback shift register unit (11) converts the first random variable x1iAnd a second random variable x2iTransmitted to a calculation module by a first random variable x1iCalculating to obtain F function value, and obtaining the value by a second random variable x2iCalculating to obtain a G function value;
s3: the calculation module stores the F function values into a first F function value memory (21) to a fifth F function value memory (25) in sequence according to the running time, and stores the G function values into a G function value memory (31);
s4: a multiplexer (26) sequentially extracts F function values from the first F function value memory (21) to the fifth F function value memory (25) according to the running time, and transmits the F function values to an FG multiplier (41); the G function value memory (31) transmits the G function value to an FG multiplier (41);
s5: FG multiplier (41) multiplies F function value and G function value to obtain multiplication result ni；
S6: FG multiplier (41) multiplies result niThe symbol is transmitted to a symbol inverter (51) for adding symbols, a signed multiplication result is obtained, and the signed multiplication result is transmitted to an iterative accumulator (61) for storage;
s7: repeating the steps S2-S6 p times, and accumulating the signed multiplication results obtained p times by the iterative accumulator (61) to obtain an output result.
8. The gaussian channel simulation method according to claim 7, wherein step S2 specifically comprises:
s21: by a first random variable x1iF function value F (x) is obtained by calculation1i) The calculation formula is as follows:
Figure FDA0003467276720000031
the expression of the simulation model fr(s) of the F function value is:
Figure FDA0003467276720000032
wherein r is a random integer ranging from 1 to K, K is a positive integer greater than 1; m is a first scaling factor; s is a random integer varying within the range of [1,15 ]; delta is a random real number uniformly distributed within the interval [0,1 ]; r represents a quantization function;
s22: by a second random variable x2iG function value G (x) is obtained by calculation2i) The calculation formula is as follows:
Figure FDA0003467276720000033
the expression of the simulation model G (s') of the G function value is as follows:
Figure FDA0003467276720000034
wherein m ' is a second scaling factor, s ' is a random integer varying within the range of [1,255], δ ' is a random real number uniformly distributed within the interval [0,1], and R represents a quantization function.
9. The gaussian channel simulation method of claim 7, wherein in step S5, the multiplication result niThe calculation formula of (2) is as follows:
ni＝f(x1i)g(x2i)
wherein, f (x)1i) Is the ith F function value, g (x)2i) Is the ith G function value;
multiplication result niIs simulated by the simulation model RniThe expression of (a) is:
Rni＝(1-2*sign)*P(r,s,s′)-sign
wherein P (r, s, s ') is a normalized function of the Gaussian channel power amplitude, sign is a sign function, r is a random integer varying in the range of 1 to K, s is a random integer varying in the range of [1,15], and s' is a random integer varying in the range of [1,255 ].
CN202210033259.0A 2022-01-12 2022-01-12 Gaussian channel simulation circuit and method Pending CN114553325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210033259.0A CN114553325A (en) 2022-01-12 2022-01-12 Gaussian channel simulation circuit and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210033259.0A CN114553325A (en) 2022-01-12 2022-01-12 Gaussian channel simulation circuit and method

Publications (1)

Publication Number Publication Date
CN114553325A true CN114553325A (en) 2022-05-27

Family

ID=81671281

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210033259.0A Pending CN114553325A (en) 2022-01-12 2022-01-12 Gaussian channel simulation circuit and method

Country Status (1)

Country Link
CN (1) CN114553325A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050036607A1 (en) * 2003-08-15 2005-02-17 Wan Wade Keith Pseudo-random number generation based on periodic sampling of one or more linear feedback shift registers
CN101131710A (en) * 2007-09-13 2008-02-27 南京大学 Low-density odd-even checking codec hardware simulation system based on programmable gate array
CN102314332A (en) * 2011-07-27 2012-01-11 中国科学院计算机网络信息中心 Pseudo random number generation device and method
CN102571171A (en) * 2012-01-10 2012-07-11 西安交通大学 Hardware achieving method of multiple-input and multiple-output wireless communication system channel model
CN107659315A (en) * 2017-09-25 2018-02-02 天津大学 A kind of sparse binary-coding circuit for compressed sensing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050036607A1 (en) * 2003-08-15 2005-02-17 Wan Wade Keith Pseudo-random number generation based on periodic sampling of one or more linear feedback shift registers
CN101131710A (en) * 2007-09-13 2008-02-27 南京大学 Low-density odd-even checking codec hardware simulation system based on programmable gate array
CN102314332A (en) * 2011-07-27 2012-01-11 中国科学院计算机网络信息中心 Pseudo random number generation device and method
CN102571171A (en) * 2012-01-10 2012-07-11 西安交通大学 Hardware achieving method of multiple-input and multiple-output wireless communication system channel model
CN107659315A (en) * 2017-09-25 2018-02-02 天津大学 A kind of sparse binary-coding circuit for compressed sensing

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
J.-L. DANGER等: "Efficient FPGA implementation of Gaussian noise generator for communication channel emulation", 《 ICECS 2000. 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (CAT. NO.00EX445)》 *
王家豪等: "煤矿井下随钻测量电磁传输信道建模", 《煤炭学报》 *

Similar Documents

Publication Publication Date Title
Lee et al. A Gaussian noise generator for hardware-based simulations
US8180055B2 (en) Cryptographic system incorporating a digitally generated chaotic numerical sequence
Tsaban et al. Efficient linear feedback shift registers with maximal period
US4691291A (en) Random sequence generators
JP2002516007A (en) Correlator method and apparatus
Masoodi et al. An analysis of linear feedback shift registers in stream ciphers
US20050044119A1 (en) Pseudo-random number generator
US4115867A (en) Special-purpose digital computer for computing statistical characteristics of random processes
Panda et al. FPGA prototype of low latency BBS PRNG
US7340496B2 (en) System and method for determining the Nth state of linear feedback shift registers
Gupta et al. Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
Ahmad et al. Selection of polynomials for cyclic redundancy check for the use of high speed embedded: an algorithmic procedure
Wang et al. Analysis of the Time Series Generated by a New High‐Dimensional Discrete Chaotic System
Lachowicz et al. Fast evaluation of the square root and other nonlinear functions in FPGA
US20040054703A1 (en) Method and device for generating a pseudo-random sequence using a discrete logarithm
CN114553325A (en) Gaussian channel simulation circuit and method
US6480870B1 (en) Random number generator using lehmer algorithm
Thane et al. Hardware design and implementation of pseudorandom number generator using piecewise linear chaotic map
Venkatesh et al. Reconfigurable architecture to speed-up modular exponentiation
TWI387921B (en) A normal distributed random number generator by using the clt and the random number generating method thereof
Glen On the period length of pseudorandom number sequences
Gomar et al. A digital pseudo random number generator based on a chaotic dynamic system
RU2812412C1 (en) Device for forming triplex numbers
Nair et al. A low-complexity hardware AWGN channel emulator on FPGA using central limit theorem
RU2800190C1 (en) Device for forming pseudo-random complex numbers

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20220527

RJ01 Rejection of invention patent application after publication