CN114551156A - Relay contact protection circuit for controlling capacitive load - Google Patents
Relay contact protection circuit for controlling capacitive load Download PDFInfo
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- CN114551156A CN114551156A CN202210190293.9A CN202210190293A CN114551156A CN 114551156 A CN114551156 A CN 114551156A CN 202210190293 A CN202210190293 A CN 202210190293A CN 114551156 A CN114551156 A CN 114551156A
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- relay
- current suppression
- capacitive load
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/02—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses a relay contact protection circuit for controlling capacitive load, comprising: the power input anode of the surge current suppression circuit is externally connected with the anode of the power input, and the power input cathode of the surge current suppression circuit is externally connected with the cathode of the power input; the power output positive pole of the surge current suppression circuit is connected with the relay control circuit, and the relay control circuit is connected with the capacitive load; the power output negative electrode of the surge current suppression circuit is connected with the capacitive load; and the time schedule controller is respectively connected with the surge current suppression circuit and the relay control circuit. The invention uses the surge current suppression circuit with the energy and the relay control circuit to control the capacitive load to supply power, and the time schedule controller ensures that the relay contact is firstly switched on and then the surge current suppression circuit is enabled when the load is electrified, thereby avoiding the impact of surge energy borne by the relay contact. The relay can select the model with small contact capacity to reduce the size, weight and cost of the product and prolong the service life of the relay.
Description
Technical Field
The invention belongs to the technical field of power electronics, and relates to a relay contact protection circuit for controlling a capacitive load.
Background
In the circuit, when a relay is used for controlling a capacitive load, very high surge current can be generated at the moment of attracting a relay contact, the surge energy is in direct proportion to the capacitance of the load, and the excessively high surge energy can cause the adhesion and ablation of the relay contact, thereby causing fatal influences on the reliability and the service life of electronic equipment. The current capacity of the relay for switching capacitive loads is much less than the current capacity for switching purely resistive loads. In actual operation, to avoid this problem, a choke inductor or a parallel combination of a choke inductor and a resistor is typically connected in series between the relay contacts and the capacitive load, or a relay with a greater capacitive load capacity is selected. However, when the load capacitance is relatively large, the size and cost of the choke inductor will increase significantly and even an appropriate choke inductor cannot be selected, and the same problem is faced in the selection of a relay with a larger capacitive load switching capability.
Disclosure of Invention
The invention aims to solve the problems in the prior art and provides a relay contact protection circuit for controlling a capacitive load, wherein the topology of the relay contact protection circuit consists of an inrush current suppression circuit with an enabling control, a relay control circuit, a time schedule controller and the capacitive load. Through adjusting time sequence control, surge energy is absorbed by the surge current suppression circuit, and the relay contact is prevented from bearing surge impact.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
a relay contact protection circuit for controlling a capacitive load, comprising: the circuit comprises a surge current suppression circuit, a relay control circuit, a time schedule controller and a capacitive load;
the power input anode of the surge current suppression circuit is externally connected with the anode of the power input, and the power input cathode of the surge current suppression circuit is externally connected with the cathode of the power input; the power output positive pole of the surge current suppression circuit is connected with a relay control circuit, and the relay control circuit is connected with a capacitive load; the power output negative electrode of the surge current suppression circuit is connected with a capacitive load; and the time schedule controller is respectively connected with the surge current suppression circuit and the relay control circuit.
The invention is further improved in that:
the time schedule controller comprises an inrush current suppression circuit enabling control end and a relay on-off control end; the enabling control end of the surge current suppression circuit of the time schedule controller is connected with the surge current suppression circuit;
and the relay on-off control end of the time schedule controller is connected with the relay control circuit.
The relay control circuit includes: the circuit comprises a diode D1, a relay LS1, a triode Q1 and a resistor R1; the relay comprises a control coil, a common contact and a load normally open contact;
the common contact of the relay is connected with the power output anode of the surge current suppression circuit; the normally open contact of the relay load is connected with the capacitive load;
one end of the resistor R1 is connected with a relay on-off control end of the time schedule controller; the other end of the resistor R1 is connected with a base electrode of a triode Q1, an emitting electrode of the triode Q1 is grounded, a collector electrode of the triode Q1 is connected with an anode of a diode D1 and one end of a control coil of a relay LS1, and the other end of the control coil of the relay LS1 is connected with a cathode of a diode D1 and a control circuit for supplying power VCC.
The capacitive load comprises a capacitor CL and a resistor RL; the positive electrode of the capacitor CL is connected with one end of the resistor RL and a normally open contact of a relay load; and the negative electrode of the capacitor CL is connected with the other end of the resistor RL and the power output negative electrode of the surge current suppression circuit.
The circuit further comprises an isolation circuit, wherein the isolation circuit comprises an optocoupler OPT1, a resistor R10, a triode Q3, a resistor R11 and a diode D3;
the optocoupler OPT1 comprises a light emitting diode and a phototriode, wherein the light emitting diode is used as an input end, and the phototriode is used as an output end;
the anode of the diode D3 is connected with the base of the triode Q3 and one end of the resistor R11; the cathode of the diode D3 is connected with the enabling control end of the surge current suppression circuit of the time schedule controller; the emitter of the triode Q3 is grounded; the other end of the resistor R11 is connected with one end of a resistor R10 and a circuit power supply VCC;
the collector of the triode Q3 is connected with the negative electrode of a light emitting diode in the optocoupler OPT1, and the resistor R10 is connected with the positive electrode of the light emitting diode in the optocoupler OPT 1;
a collector electrode of a phototriode in the optocoupler OPT1 is connected with the surge current suppression circuit; and an emitter of a phototriode in the optocoupler OPT1 is connected with a negative electrode of a power input.
The isolation circuit further comprises a resistor R12, one end of the resistor R12 is connected with the cathode of the diode D3, and the resistor R12 is connected with a circuit power supply VCC.
The surge current suppression circuit includes: the circuit comprises an integrated circuit U1, a MOS transistor Q1, a resistor R9, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D2, a triode Q2 and a capacitor C2;
the positive electrode of the power supply input is connected with one end of the resistor R9, one end of the resistor R2, one end of the resistor R4 and the VIN pin of the integrated circuit U1;
the other end of the resistor R9 is connected with a SENSE pin of an integrated circuit U1 and the drain electrode of a MOS tube Q1; the grid electrode of the MOS tube Q1 is connected with a CATE pin of an integrated circuit U1, one end of a resistor R6 and the anode of a diode D2, and the source electrode of the MOS tube Q1 is connected with an OUT pin, a PGD pin and a relay control circuit of the integrated circuit U1;
the base electrode of the triode Q2 is connected with the other end of the resistor R6, the cathode of the diode D2 is connected with the emitter electrode of the triode Q2 and one end of the capacitor C2, and the other end of the capacitor C2 is connected with the collector electrode of the triode Q2 and the ground;
the other end of the resistor R2 is connected with a UVLO pin of an integrated circuit U1 and one end of a resistor R3;
the other end of the resistor R4 is connected with an OVLO pin of an integrated circuit U1, one end of a resistor R5 and a collector electrode of an optocoupler OPT1 phototriode;
the negative electrode of the power supply input is connected with the other end of the resistor R5, the other end of the resistor R3, a TIMER pin, a PWR pin and a GND pin of the integrated circuit U1.
The inrush current suppression circuit further includes: a capacitor C3, a resistor R8, a resistor R7 and a capacitor C1;
the capacitor C3 is positioned between a TIMER pin of the integrated circuit U1 and the negative pole of the power supply input; the resistor R8 is positioned between a PWR pin of the integrated circuit U1 and the negative pole of the power supply input; the resistor R7 is located between a PGD pin of the integrated circuit U1 and a source electrode of the MOS transistor Q1, one end of the capacitor C1 is connected with a positive electrode of a power supply input, and the other end of the capacitor C1 is grounded.
The model of the integrated circuit U1 is LM 5069; the MOS tube Q1 is an NMOS tube.
Compared with the prior art, the invention has the following beneficial effects:
the invention uses the surge current suppression circuit with the enable and the relay control circuit to be connected in series to control the capacitive load to supply power, and the time schedule controller ensures that the relay contact is firstly switched on and then passes through the enable surge current suppression circuit when the load is electrified, thereby avoiding the impact of surge energy borne by the relay contact. Because the relay contact does not bear the energy impact when the switch, the relay can select the model that the contact capacity is littleer in order to reduce product size, weight and cost, improves relay life.
Drawings
In order to more clearly explain the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a block diagram of one topology of a relay contact protection circuit for controlling a capacitive load in accordance with an embodiment of the present invention;
FIG. 2 is a timing diagram illustrating a control of a relay contact protection circuit for controlling a capacitive load according to an embodiment of the present invention;
fig. 3 is another topology block diagram of a relay contact protection circuit for controlling a capacitive load according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.
In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is usually arranged when the product of the present invention is used, the description is merely for convenience and simplicity, and the indication or suggestion that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, cannot be understood as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
Furthermore, the term "horizontal", if present, does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the embodiments of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The invention is described in further detail below with reference to the accompanying drawings:
referring to fig. 1, the present invention discloses a relay contact protection circuit for controlling a capacitive load, comprising: the circuit comprises a surge current suppression circuit, a relay control circuit, a time schedule controller and a capacitive load. The surge current suppression circuit is provided with an enable control end EN _ Inrush and is used for controlling the on-off of a circuit and suppressing surge current; the relay control circuit consists of a relay LS1, a diode D1, a triode Q1 and a resistor R1; on-off control of a Relay contact is realized through a control terminal EN _ Relay; the relay LS1 is used for isolating the load power supply and the control circuit power supply; the time schedule controller realizes the control of the power-on sequence and the power-off sequence of the load through control signals EN _ Inrush and EN _ Relay, and avoids the damage of Relay contacts caused by surge energy.
The structure of the relay contact protection circuit for controlling the capacitive load can be as follows: the power input → the surge current suppression circuit → the relay → the capacitive load are connected in sequence, and the following steps can be also adopted: power input → relay → surge current suppression circuit → capacitive load. Namely, the sequence of the relay and the surge current suppression circuit does not influence the protection result.
According to the following steps: when the power input → the surge current suppression circuit → the relay control circuit → the capacitive load are sequentially connected with the circuit, the positive pole of the power input of the surge current suppression circuit is externally connected with the positive pole of the power input, and the negative pole of the power input of the surge current suppression circuit is externally connected with the negative pole of the power input; the power output positive pole of the surge current suppression circuit is connected with the relay control circuit, and the relay control circuit is connected with the capacitive load; the power output negative electrode of the surge current suppression circuit is connected with the capacitive load; and the time schedule controller is respectively connected with the surge current suppression circuit and the relay control circuit.
The surge current suppression circuit topology comprises an NMOS or PMOS surge current suppression circuit with an enable control realized by using an integrated circuit control chip to control a MOSFET and a discrete device.
The time schedule controller comprises an Inrush current suppression circuit enabling control end (EN _ Inrush) and a Relay on-off control end (EN _ Relay); an Inrush current suppression circuit enabling control end (EN _ Inrush) of the time schedule controller is connected with the Inrush current suppression circuit; and a Relay on-off control end (EN _ Relay) of the time schedule controller is connected with the Relay control circuit.
The logic of the Inrush current suppression circuit enable control terminal (EN _ Inrush) and the Relay control terminal signal (EN _ Relay) is not limited to the high level, and a low level or a combinational logic may be used. Taking the high-level enable control logic as an example, the controller output timing satisfies the timing shown in fig. 2. The enabling time of the inrush current suppression circuit in the power-on process needs to lag the time of the relay switch-on time t1, and t1 needs to be longer than the action time of the relay.
The time schedule controller is used for controlling the on-off sequence of the surge suppression circuit and the relay contact, and ensuring that the relay contact cannot bear surge energy impact. The time schedule controller may be any type of hardware delay circuit, single chip, microprocessor, DSP, FPGA, etc., and is not limited thereto.
The relay control circuit includes: the circuit comprises a diode D1, a relay LS1, a triode Q1 and a resistor R1; the relay comprises a control coil, a common contact and a load normally open contact;
the common contact of the relay is connected with the power output anode of the surge current suppression circuit; the normally open contact of the relay load is connected with the capacitive load;
one end of the resistor R1 is connected with the relay on-off control end of the time schedule controller; the other end of the resistor R1 is connected with a base electrode of a triode Q1, an emitting electrode of the triode Q1 is grounded, a collector electrode of the triode Q1 is connected with an anode of a diode D1 and one end of a control coil of a relay LS1, and the other end of the control coil of the relay LS1 is connected with a cathode of a diode D1 and a control circuit for supplying power VCC.
The Relay control signal (EN _ Relay) and the Inrush current suppression circuit enable signal (EN _ Inrush) can adopt a non-isolation structure, and can also adopt optical isolation, magnetic isolation and capacitance isolation measures.
The relay can be a single-group contact or a plurality of groups of contacts in the forms of single-pole single-throw, single-pole double-throw, double-pole double-throw and the like, and is not limited to a common electromagnetic relay, a magnetic latching relay, a sealed relay and the like.
The capacitive load comprises a capacitor CL and a resistor RL; the positive electrode of the capacitor CL is connected with one end of the resistor RL and a normally open contact of a relay load; the negative electrode of the capacitor CL is connected to the other end of the resistor RL and the negative electrode of the power output of the surge current suppression circuit.
The capacitive load is an equivalent circuit, and may be a circuit unit, a circuit module, a circuit system or a subsystem.
As shown in fig. 3, the relay contact protection circuit for controlling the capacitive load further includes an isolation circuit, where the isolation circuit includes an optocoupler OPT1, a resistor R10, a transistor Q3, a resistor R11, and a diode D3;
the optocoupler OPT1 comprises a light emitting diode and a phototriode, wherein the light emitting diode is used as an input end, and the phototriode is used as an output end;
the anode of the diode D3 is connected with the base of the triode Q3 and one end of the resistor R11; the cathode of the diode D3 is connected with the enabling control end of the surge current suppression circuit of the time schedule controller; the emitter of the triode Q3 is grounded; the other end of the resistor R11 is connected with one end of a resistor R10 and a circuit power supply VCC;
the collector of the triode Q3 is connected with the negative electrode of a light emitting diode in the optocoupler OPT1, and the resistor R10 is connected with the positive electrode of the light emitting diode in the optocoupler OPT 1;
a collector electrode of a phototriode in the optocoupler OPT1 is connected with the surge current suppression circuit; and an emitter of a phototriode in the optocoupler OPT1 is connected with a negative electrode of the power input.
The isolation circuit further comprises a resistor R12, one end of the resistor R12 is connected with the cathode of the diode D3, and the resistor R12 is connected with the circuit power supply VCC.
The optocoupler OPT1, the resistor R10, the triode Q3, the resistor R11, the resistor R12 and the diode D3 form a surge current suppression circuit enabling control isolation circuit. The isolation circuit may use a non-isolated form.
The surge current suppression circuit includes: the circuit comprises an integrated circuit U1, a MOS transistor Q1, a resistor R9, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D2, a triode Q2 and a capacitor C2;
the surge current suppression circuit is realized by an integrated circuit U1 driving MOS transistor Q1. The resistor R2 and the resistor R3 realize overvoltage sampling; the resistor R4 and the resistor R5 realize undervoltage sampling; the resistor R6, the diode D2, the triode Q2 and the capacitor C2 realize MOS tube grid voltage slope adjustment and power-down discharge.
The anode of the power input is connected with one end of the resistor R9, one end of the resistor R2, one end of the resistor R4 and the VIN pin of the integrated circuit U1;
the other end of the resistor R9 is connected with a SENSE pin of the integrated circuit U1 and the drain electrode of the MOS tube Q1; the grid of the MOS tube Q1 is connected with a CATE pin of the integrated circuit U1, one end of the resistor R6 and the anode of the diode D2, and the source of the MOS tube Q1 is connected with an OUT pin, a PGD pin and a relay control circuit of the integrated circuit U1;
the base electrode of the triode Q2 is connected with the other end of the resistor R6, the cathode of the diode D2 is connected with the emitter electrode of the triode Q2 and one end of the capacitor C2, and the other end of the capacitor C2 is connected with the collector electrode of the triode Q2 and the ground;
the other end of the resistor R2 is connected with a UVLO pin of the integrated circuit U1 and one end of the resistor R3;
the other end of the resistor R4 is connected with an OVLO pin of the integrated circuit U1, one end of the resistor R5 and a collector electrode of an optocoupler OPT1 phototriode;
the negative pole of the power supply input is connected with the other end of the resistor R5, the other end of the resistor R3, a TIMER pin, a PWR pin and a GND pin of the integrated circuit U1.
The inrush current suppression circuit further includes: a capacitor C3, a resistor R8, a resistor R7 and a capacitor C1;
the capacitor C3 is located between the TIMER pin of the integrated circuit U1 and the negative pole of the power supply input; the resistor R8 is positioned between the PWR pin of the integrated circuit U1 and the negative pole of the power supply input; the resistor R7 is located between the PGD pin of the integrated circuit U1 and the source of the MOS transistor Q1, one end of the capacitor C1 is connected with the anode of the power input, and the other end of the capacitor C1 is grounded.
The model of the integrated circuit U1 is LM 5069; the MOS transistor Q1 is an NMOS transistor.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A relay contact protection circuit for controlling a capacitive load, comprising: the circuit comprises a surge current suppression circuit, a relay control circuit, a time schedule controller and a capacitive load;
the power input anode of the surge current suppression circuit is externally connected with the anode of the power input, and the power input cathode of the surge current suppression circuit is externally connected with the cathode of the power input; the power output positive pole of the surge current suppression circuit is connected with a relay control circuit, and the relay control circuit is connected with a capacitive load; the power output negative electrode of the surge current suppression circuit is connected with a capacitive load; and the time schedule controller is respectively connected with the surge current suppression circuit and the relay control circuit.
2. The relay contact protection circuit for controlling a capacitive load according to claim 1, wherein the timing controller comprises an inrush current suppression circuit enable control terminal and a relay on-off control terminal; the enabling control end of the surge current suppression circuit of the time schedule controller is connected with the surge current suppression circuit;
and the relay on-off control end of the time schedule controller is connected with the relay control circuit.
3. The relay contact protection circuit for controlling a capacitive load of claim 2, wherein said relay control circuit comprises: the circuit comprises a diode D1, a relay LS1, a triode Q1 and a resistor R1; the relay comprises a control coil, a common contact and a load normally open contact;
the common contact of the relay is connected with the power output anode of the surge current suppression circuit; the normally open contact of the relay load is connected with the capacitive load;
one end of the resistor R1 is connected with a relay on-off control end of the time schedule controller; the other end of the resistor R1 is connected with a base electrode of a triode Q1, an emitting electrode of the triode Q1 is grounded, a collector electrode of the triode Q1 is connected with an anode of a diode D1 and one end of a control coil of a relay LS1, and the other end of the control coil of the relay LS1 is connected with a cathode of a diode D1 and a control circuit for supplying power VCC.
4. The relay contact protection circuit for controlling a capacitive load according to claim 3, wherein said capacitive load comprises a capacitor CL and a resistor RL; the positive electrode of the capacitor CL is connected with one end of the resistor RL and a normally open contact of a relay load; and the negative electrode of the capacitor CL is connected with the other end of the resistor RL and the power output negative electrode of the surge current suppression circuit.
5. The relay contact protection circuit for controlling a capacitive load according to claim 4, further comprising an isolation circuit comprising an opto-coupler OPT1, a resistor R10, a transistor Q3, a resistor R11 and a diode D3;
the optocoupler OPT1 comprises a light emitting diode and a phototriode, wherein the light emitting diode is used as an input end, and the phototriode is used as an output end;
the anode of the diode D3 is connected with the base of the triode Q3 and one end of the resistor R11; the cathode of the diode D3 is connected with the enabling control end of the surge current suppression circuit of the time schedule controller; the emitter of the triode Q3 is grounded; the other end of the resistor R11 is connected with one end of a resistor R10 and a circuit power supply VCC;
the collector of the triode Q3 is connected with the negative electrode of a light emitting diode in the optocoupler OPT1, and the resistor R10 is connected with the positive electrode of the light emitting diode in the optocoupler OPT 1;
a collector electrode of a phototriode in the optocoupler OPT1 is connected with the surge current suppression circuit; and an emitter of a phototriode in the optocoupler OPT1 is connected with a negative electrode of the power input.
6. The relay contact protection circuit for controlling a capacitive load according to claim 5, wherein the isolation circuit further comprises a resistor R12, one end of the resistor R12 is connected to the cathode of the diode D3, and the resistor R12 is connected to the circuit power supply VCC.
7. The relay contact protection circuit for controlling a capacitive load of claim 6, wherein said inrush current suppression circuit comprises: the circuit comprises an integrated circuit U1, a MOS transistor Q1, a resistor R9, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D2, a triode Q2 and a capacitor C2;
the positive electrode of the power supply input is connected with one end of the resistor R9, one end of the resistor R2, one end of the resistor R4 and the VIN pin of the integrated circuit U1;
the other end of the resistor R9 is connected with a SENSE pin of an integrated circuit U1 and the drain electrode of a MOS tube Q1; the grid electrode of the MOS tube Q1 is connected with a CATE pin of an integrated circuit U1, one end of a resistor R6 and the anode of a diode D2, and the source electrode of the MOS tube Q1 is connected with an OUT pin, a PGD pin and a relay control circuit of the integrated circuit U1;
the base electrode of the triode Q2 is connected with the other end of the resistor R6, the cathode of the diode D2 is connected with the emitter electrode of the triode Q2 and one end of the capacitor C2, and the other end of the capacitor C2 is connected with the collector electrode of the triode Q2 and the ground;
the other end of the resistor R2 is connected with a UVLO pin of an integrated circuit U1 and one end of a resistor R3;
the other end of the resistor R4 is connected with an OVLO pin of an integrated circuit U1, one end of a resistor R5 and a collector electrode of an optocoupler OPT1 phototriode;
the negative electrode of the power supply input is connected with the other end of the resistor R5, the other end of the resistor R3, a TIMER pin, a PWR pin and a GND pin of the integrated circuit U1.
8. The relay contact protection circuit for controlling a capacitive load of claim 7, wherein said inrush current suppression circuit further comprises: a capacitor C3, a resistor R8, a resistor R7 and a capacitor C1;
the capacitor C3 is positioned between a TIMER pin of the integrated circuit U1 and the negative pole of the power supply input; the resistor R8 is positioned between a PWR pin of the integrated circuit U1 and the negative pole of the power supply input; the resistor R7 is located between a PGD pin of the integrated circuit U1 and a source electrode of the MOS transistor Q1, one end of the capacitor C1 is connected with a positive electrode of a power supply input, and the other end of the capacitor C1 is grounded.
9. The relay contact protection circuit for controlling a capacitive load of claim 8, wherein said integrated circuit U1 is model LM 5069; the MOS transistor Q1 is an NMOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210190293.9A CN114551156B (en) | 2022-02-28 | 2022-02-28 | Relay contact protection circuit for controlling capacitive load |
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| CN202210190293.9A CN114551156B (en) | 2022-02-28 | 2022-02-28 | Relay contact protection circuit for controlling capacitive load |
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| CN114551156B CN114551156B (en) | 2023-08-29 |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114551156B (en) | 2023-08-29 |
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