CN114531233A - Post-processing system for multi-degree-of-freedom modulation QKD and error correction decoding method - Google Patents

Post-processing system for multi-degree-of-freedom modulation QKD and error correction decoding method Download PDF

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CN114531233A
CN114531233A CN202111683564.6A CN202111683564A CN114531233A CN 114531233 A CN114531233 A CN 114531233A CN 202111683564 A CN202111683564 A CN 202111683564A CN 114531233 A CN114531233 A CN 114531233A
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郭邦红
杨帆
胡敏
范啸东
张锐
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Guangdong Yukopod Technology Development Co ltd
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Abstract

The invention discloses a post-processing system and an error correction decoding method for multi-degree-of-freedom modulation QKD (quantum key distribution), belonging to the field of quantum secret communication and optical fiber communication, and comprising a sender Alice and a receiver Bob, wherein the sender Alice comprises a quantum state generating and modulating device, an upper computer, an Altera Arria10 development board, an encoder, a decoder and a secret enhancement system; the receiver Bob comprises quantum state detection demodulation equipment, an upper computer, an encoder, a privacy enhancement system and an Altera Arria10 development board; the quantum state generating and modulating device is connected with the quantum state detection and demodulation device through a quantum channel, the sender Alice sends the quantum state to the quantum detection and demodulation device of the receiver Bob through the quantum channel, initial probabilities are set in a differentiation mode through recombination decoding bits, the reliability of the open syndrome is greatly improved, and therefore convergence is improved, iteration times are reduced, and error correction speed is improved.

Description

Post-processing system for multi-degree-of-freedom modulation QKD and error correction decoding method
Technical Field
The invention relates to the fields of quantum secret communication and optical fiber communication, in particular to a post-processing system for multi-degree-of-freedom modulation QKD and an error correction decoding method.
Background
Since the first Quantum Key Distribution (QKD) protocol was proposed in 1988, the corresponding post-processing supplementary protocol has evolved endlessly, wherein for error correction techniques, the BBBSS protocol was proposed in 1992; the Cascade protocol was proposed in 1993; then the Winnow protocol comes along. However, the interaction times of the protocols are high, and certain influence is caused on the safety of the system. A Low Density Parity Check code (LDPC) is one of linear block Codes, is proposed by Gallager in 1962, provides a definition, a construction method and a coding method of a Check matrix, and proves that the Check matrix has excellent performance which can approach the shannon limit; in 1981, two discoveries of Tanner have advanced the development of LDPC again, one of which proposes that an LDPC check matrix is constructed and expressed in a bipartite graph (i.e., Tanner graph) manner, and the other proposes a Sum-Product (SP) decoding algorithm and a Min-Sum (MS) decoding algorithm, which are still used so far.
In the process of QKD, the key reaching the post-processing system still comprises partial error codes due to the imperfection of the device, the noise of the channel and the eavesdropping behavior of a potential eavesdropper Eve, so that the QKD needs to be supplemented by data post-processing on a classical channel, both communication parties obtain the same key bits through error correction, and the leaked information is eliminated through confidentiality enhancement on the basis. The Field-Programmable Gate Array (FPGA) has the capabilities of pipeline parallel and data parallel, so that the delay is lower when processing tasks, and the FPGA is the best choice for realizing the error correction decoding process. In addition, the Arria10 FPGA of Altera is the better performance in the current market, and the performance is one rate grade higher than that of a competitive device by adopting the 20 nanometer technology. The ariia 10 FPGA and SoC consumes 40% less power than previous generation FPGAs and socs, with the industry's unique hard core floating point Digital Signal Processing (DSP) module, which rates up to 1,500giga floating point operations per second (GFLOPS).
In the prior art, a chinese patent publication No. CN106685655B proposes a physical system network of phase-bias multi-degree-of-freedom modulation QKD, and the patent does not relate to the research of a key agreement method; chinese patent publication No. CN111200493A proposes a post-processing system and method for phase-bias joint modulation QKD, which proposes a connection mode and an information interaction mode of an information interaction unit, a parameter estimation unit, an error correction unit, and a secret amplification unit, but does not relate to the research of an internal system and method of a specific key agreement (error correction unit).
Therefore, in view of the problems in the prior art, it is desirable to provide a fast error correction method that can be applied to QKD post-processing.
Disclosure of Invention
Therefore, the invention aims to provide a multi-degree-of-freedom modulation QKD post-processing system and an error correction decoding method thereof, which can quickly correct key errors caused by eavesdropping and can be realized in parallel on the basis of hardware.
In order to achieve the purpose, the invention adopts the following technical scheme:
a post-processing system for multi-degree-of-freedom modulation QKD comprises a sender Alice and a receiver Bob,
the sender Alice comprises quantum state generating and modulating equipment, an upper computer, an Altera Arria10 development board, a coder, a decoder and a privacy enhancement system; the Altera Arria10 development board is an FPGA hardware acceleration device;
the receiver Bob comprises quantum state detection demodulation equipment, an upper computer, an encoder, a privacy enhancement system and an Altera Arria10 development board;
the quantum state generating and modulating device is connected with the quantum state detection and demodulation device through a quantum channel, and the sender Alice sends the quantum state to the quantum detection and demodulation device of the receiver Bob through the quantum channel;
the encoder, the decoder and the privacy enhancement system of the sender Alice are all arranged on an Altera Arria10 development board of the sender Alice and are connected with an upper computer of the sender Alice; the encoder and the privacy enhancement system of the receiver Bob are both arranged on an Altera Arria10 development board of the receiver Bob and are connected with an upper computer of the receiver Bob, and the upper computer of the sender Alice is connected with the upper computer of the receiver Bob through a classical channel;
the method comprises the steps that a sender Alice and a receiver Bob extract part of position bits through respective upper computers and disclose and calculate a QBER, the QBER is a quantum bit error rate, a safety threshold value is stored in the upper computer of the sender Alice and the upper computer of the receiver Bob, when the QBER is larger than the safety threshold value, a secret key is discarded due to the distribution failure of the secret key, and when the QBER is smaller than the safety threshold value, the QBER is stored; after the upper computer of the sender Alice and the upper computer of the receiver Bob calculate QBER in the position bits of the public part, respectively taking the rest bits as screened key KsiftAAnd the screened secret key KsiftBSending the data to respective encoders for encoding;
the sender Alice generates a check bit K by the encoder of the sender AlicecAAnd the screened key KsiftAInputting the data into a decoder of the sender Alice; the encoder of the receiver Bob generates a check bit KcBSending the quantum state to the upper computer of the sender Alice through the classical channel by the upper computer of the receiver Bob, and then inputting the quantum state into a decoder of the sender Alice for decoding;
when the sender Alice successfully decodes, the generated error-corrected secret key KrecInputting the secrecy enhancement system of the sender Alice, simultaneously sending a decoding success mark, and sending the mark to the upper computer of the receiver Bob through the upper computer of the sender Alice and the classical channel, thereby controlling the screened secret key K of the receiver BobsiftBEntering a privacy enhancement system of a receiver Bob;
after the privacy enhancement system of the sender Alice and the receiver Bob finishes the work, the final secret key K is sentendAnd the data are stored in respective upper computers, the whole process of the QKD is finished, and the two communication parties obtain completely consistent and safe keys.
Preferably, the encoder, decoder and privacy enhancement system of the sender Alice are designed based on the Altera aria 10 development board;
the encoder, privacy enhancement system of the recipient Bob is based on an Altera ariia 10 development board design.
In the invention, an error correction decoding method suitable for a QKD post-processing scene is further provided, through recombining decoding bits, setting the initial probability in a differentiation mode, the reliability of a public syndrome can be improved, the initial probability is used as a standard correction key bit, so that the convergence degree is improved theoretically, the iteration times are reduced, and the error correction speed is improved, and meanwhile, a state transfer, matrix storage and parallel decoding structure based on an Altera Arria10 development board is provided, so that the hardware processing speed is improved.
An error correction decoding method for multi-degree-of-freedom modulation QKD post-processing is applied to the multi-degree-of-freedom modulation QKD post-processing system, and comprises the following steps:
s1, inputting a key; the key input further comprises the steps of:
s1-1, inputting the screened secret key K of the sender AlicesiftALength is m;
s1-2, inputting syndrome K sent by receiver BobcBLength of K is equal to KsiftAForm a sub-K to be decodedsThe length is n, and the n is stored in the RAM of the upper computers of the two sides, wherein n is m + k;
s2, initializing differentiation probability; the probability initialization further comprises the steps of:
s2-1, when K is in RAMsCode word position index add _ K ofs∈[1,m]The probability is initialized to:
Figure BDA0003453061400000041
wherein QBER is the quantum bit error rate, and log (-) is a logarithmic function;
s2-2, when the code word position index add _ Ks∈[m+1,n]The probability is initialized to:
Figure BDA0003453061400000042
wherein epsilon is a minimum value;
s3, data layering and quantifying; the hierarchical quantization of data further comprises the steps of:
s3-1, determining a quantization range, namely a probability value range;
s3-2, determining the quantization bit width, namely the probability value difference;
s3-3, inputting the probability information after quantization, and outputting an initialized probability quantization completion flag cin _ llr _ advance equal to 1, and an intermediate probability quantization completion flag cin _ llr _ mid _ advance equal to 1;
s4, carrying out a minimum sum decoding algorithm; the min-sum decoding algorithm further comprises the steps of:
s4-1, when cin _ llr _ alert is equal to 1, carrying out a round of horizontal updating;
s4-2, performing one round of vertical updating;
s4-3, judging: store result c _ in _ llr (add _ K)siftA) If c _ in _ llr (add _ K)siftA) If < 0, decision KsiftA(add_KsiftA) If not, K is determinedsiftA(add_KsiftA) When it is 0, update Ks={KsiftA,KcB}; wherein add _ KsiftAIs KsiftAA position index of (a);
s4-4, if the decoding times do not reach the maximum iteration times mitier: computing
Figure BDA0003453061400000043
If the result is
Figure BDA0003453061400000044
Decoding is successful, the output success flag decode _ finish is 1, if the result is not
Figure BDA0003453061400000045
Returning to execute step S4-1; if the decoding times reach the maximum iteration times, outputting a failure flag, namely, a pointer _ reach, returning to wait for decoding again, wherein qcH is an LDPC check matrix;
s5, outputA final key; if decode _ finish is 1, the final key K is outputendIf all the Output end marks are 1, returning to wait for the decoding of the next round of data;
steps S1-S5 each implement a state transition by a state machine comprising the following states:
START _ i: an initial state, jumping to a next state INPUT _ INI _ i when key _ valid is 1 and check _ bit _ valid is 1;
key INPUT and initialization state, when key _ address is 1, jumping to next state INPUT _ INI _ i;
quanti _ Go, data quantization hierarchical state, jump to next state MS _ cui when cin _ llr _ update 1;
MS _ Cul is the minimum sum decoding state, and when decoding _ finish is 1, the decoding successfully jumps to the next state OUTPUT _ i; when the miter _ reach indicates that the maximum iterative decoding times are reached but the decoding is not successful, jumping to an initial state START _ i;
OUTPUT _ i data OUTPUT state, when OUTPUT _ end equals 1, the OUTPUT end jumps to the initial state START _ i.
Preferably, the step S4-1 further includes the steps of:
s4-1-1, setting RAMRcv(i,add_Ks) The dimension is (m multiplied by n) and is used for storing the horizontal check result and carrying out initialization and zero clearing;
s4-1-2, according to two formulas:
Figure BDA0003453061400000051
wherein the content of the first and second substances,
Figure BDA0003453061400000052
the horizontal check probability of the (c, v) th memory in the kth iteration is obtained, omega (c) \ v is all information nodes except v connected with a check node c, alpha is a normalization parameter, the range is (0, 1), and the optimal normalization parameter is determined through simulation;
Figure BDA0003453061400000053
wherein the content of the first and second substances,
Figure BDA0003453061400000054
the vertical check probability of the (c, v) th memory in the kth iteration is defined, and psi (v) \ c is all check nodes except c connected with the information node v;
calculating the horizontal update probability according to a formula in a layered mode:
S(add_Ks)=c_in_llr(add_Ks)-Rcv(i,add_Ks);
s4-1-3, calculating the current iteration layer
Figure BDA0003453061400000061
And storing the result and the minimum address index thereof into a temporary cache RAM respectively, recording the result and the minimum address index as min _ cc and cc, and calculating:
Figure BDA0003453061400000062
stored as sub _ min; wherein i means i ∈ [1, n ];
s4-1-4, calculating a sign function:
Figure BDA0003453061400000063
s4-1-5, calculating and storing the level updating probability:
Rcv(i)=α·min_cc·sgn(c_in_llr(i))·sgn_i,i∈Ω(c)\cc;
Rcv(cc)=α·sub_min·sgn(c_in_llr(i))·sgn_i,i∈Ω(i)\cc;
preferably, step S4-2 further includes the following calculation:
Figure BDA0003453061400000064
the invention has the beneficial technical effects that:
the invention optimizes the minimum sum decoding algorithm and sets the initial probability in a differentiation way based on the design of a QKD optical system, the design of a post-processing system and the design environment of error correction codes, improves the convergence degree theoretically by improving the reliability of a public syndrome and correcting key bits by taking the syndrome as a standard, reduces the iteration times of decoding and improves the speed of error correction. Meanwhile, a state transfer, matrix storage and parallel decoding structure based on a development environment and an operation platform is provided, and the processing and operation speed of the functional hardware module is improved. And a secondary development hardware mode is adopted to realize a parallel error correction decoding process, and the decoding rate is increased, so that the efficiency of the whole QKD system is improved.
Drawings
FIG. 1 is a block diagram of a system for multi-degree-of-freedom modulation of QKD provided by the present invention;
FIG. 2 is a diagram of the error correction decoding state transition of the post-processing of the QKD with multiple degrees of freedom modulation provided by the present invention;
FIG. 3 is a flowchart of error correction decoding of post-processing of QKD with multiple degrees of freedom modulation provided by the present invention;
FIG. 4 is an LDPC check matrix and Tanner graph of multi-degree-of-freedom modulation QKD post-processing provided by the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments are further described in detail, but the scope of the present invention is not limited by the following embodiments.
Specifically, when the multi-degree-of-freedom modulation quantum key distribution protocol is based on a double-speed protocol, after signal transmission, reception and measurement are carried out through a physical layer, a transmitting party and a receiving party generate corresponding information. Since these pieces of information are not exactly equal to each other, and there are cases where information is leaked and an error occurs, it is necessary to further process these pieces of information through post-processing, and finally obtain a secure shared key. Based on this, the present embodiment proposes a key agreement system for multi-degree-of-freedom modulation QKD.
As shown in fig. 1-4, a post-processing system for multi-degree-of-freedom modulation QKD, includes a sender Alice and a receiver Bob,
the sender Alice comprises quantum state generating and modulating equipment, an upper computer, an Altera Arria10 development board, a coder, a decoder and a privacy enhancement system; the upper computer is field equipment for monitoring and controlling a communication process, and is a computer provided with configuration Software (SCADA) or realizing the functions of common configuration software; the Altera Arria10 development board is an FPGA hardware acceleration device;
the receiver Bob comprises quantum state detection demodulation equipment, an upper computer, an encoder, a privacy enhancement system and an Altera Arria10 development board;
the security enhancement system is used for compressing the mapping key string, sacrificing a small amount of keys to reduce the leaked information by exponential order, thereby eliminating the intercepted key bits and extracting the final key.
The quantum state generating and modulating device is connected with the quantum state detection and demodulation device through a quantum channel, and the sender Alice sends the quantum state to the quantum detection and demodulation device of the receiver Bob through the quantum channel;
the encoder, the decoder and the privacy enhancement system of the sender Alice are all arranged on an Altera Arria10 development board of the sender Alice and are connected with an upper computer of the sender Alice; the encoder and the privacy enhancement system of the receiver Bob are both arranged on an Altera Arria10 development board of the receiver Bob and connected with an upper computer of the receiver Bob, and the upper computer of the sender Alice is connected with the upper computer of the receiver Bob through a classical channel.
Through the technical scheme, in a specific application, the sender Alice and the receiver Bob extract part of position bits through respective upper computers and disclose and calculate QBER, wherein the QBER is a quantum bit error rate,
and if the total public bit number is N _ p and the inconsistent bit number after comparison is N _ p, then:
Figure BDA0003453061400000081
a safety threshold is stored in the upper computer of the sender Alice and the upper computer of the receiver Bob, when the QBER is greater than the safety threshold, the key distribution fails and the key is discarded, and when the QBER is less than the safety threshold, the QBER is stored; after the upper computer of the sender Alice and the upper computer of the receiver Bob calculate QBER in the position bits of the public part, respectively taking the rest bits as screened key KsiftAAnd the screened secret key KsiftBSending the data to respective encoders for encoding;
the sender Alice generates a check bit K by the encoder of the sender AlicecAAnd the screened key KsiftAInputting the data into a decoder of the sender Alice; the encoder of the receiver Bob generates a check bit KcBSending the quantum state to the upper computer of the sender Alice through the classical channel by the upper computer of the receiver Bob, and then inputting the quantum state into a decoder of the sender Alice for decoding;
when the sender Alice successfully decodes, the generated error-corrected secret key KrecInputting the secrecy enhancement system of the sender Alice, simultaneously sending a sign of successful decoding, and sending the sign to the upper computer of the receiver Bob through the classical channel by the upper computer of the sender Alice, thereby controlling the screened secret key K of the receiver BobsiftBEntering a privacy enhancement system of a receiver Bob;
after the privacy enhancement system of the sender Alice and the receiver Bob finishes the work, the final secret key K is sentendStoring the data in respective upper computers, finishing the whole process of QKD, and obtaining completely consistent and safe keys by both communication parties;
in this embodiment, the sender Alice's encoder, decoder and privacy enhancement system are designed based on the Altera aria 10 development board;
the encoder, privacy enhancement system of the recipient Bob is based on an Altera ariia 10 development board design.
In the embodiment, an error correction decoding method suitable for a QKD post-processing scene is further provided, through recombination decoding bits, initial probabilities are set in a differentiation mode, the credibility of a public syndrome can be improved, the syndrome is used as a standard correction key bit, so that the convergence degree is improved, the iteration times are reduced, and the error correction speed is improved in theory.
An error correction decoding method for multi-degree-of-freedom modulation QKD post-processing is applied to the multi-degree-of-freedom modulation QKD post-processing system, and comprises the following steps:
s1, inputting a key; the key input further comprises the steps of:
s1-1, inputting the screened secret key K of the sender AlicesiftALength is m;
s1-2, inputting syndrome K sent by receiver BobcBLength of K is equal to KsiftAForm a sub-K to be decodedsThe length is n, and the n is stored in the RAM of the upper computers of the two sides, wherein n is m + k;
s2, initializing differentiation probability; the probability initialization further comprises the steps of:
s2-1, when K is in RAMsCode word position index add _ K ofs∈[1,m]The probability is initialized to:
Figure BDA0003453061400000091
wherein QBER is the quantum bit error rate, and log (-) is a logarithmic function;
s2-2, when the code word position index add _ Ks∈[m+1,n]The probability is initialized to:
Figure BDA0003453061400000092
wherein epsilon is a minimum value;
s3, data layering and quantifying; the hierarchical quantization of data further comprises the steps of:
s3-1, determining a quantization range, namely a probability value range;
s3-2, determining the quantization bit width, namely the probability value difference;
s3-3, inputting the probability information after quantization, and outputting an initialized probability quantization completion flag cin _ llr _ advance equal to 1, and an intermediate probability quantization completion flag cin _ llr _ mid _ advance equal to 1;
s4, carrying out a minimum sum decoding algorithm; the min-sum decoding algorithm further comprises the steps of:
s4-1, when cin _ llr _ alert is equal to 1, carrying out a round of horizontal updating;
in this embodiment, step S4-1 further includes the following steps:
s4-1-1, setting RAMRcv(i,add_Ks) The dimension is (m multiplied by n) and is used for storing the horizontal checking result and initializing and resetting;
s4-1-2, according to two formulas:
Figure BDA0003453061400000101
wherein the content of the first and second substances,
Figure BDA0003453061400000102
the horizontal check probability of the (c, v) th memory in the kth iteration is shown, omega (c) \ v is all information nodes except v connected with a check node c, alpha is a normalization parameter, the range is (0, 1), and the optimal normalization parameter is determined through simulation;
Figure BDA0003453061400000103
wherein the content of the first and second substances,
Figure BDA0003453061400000104
as the vertical check probability of the (c, v) th memory in the kth iteration, psi (v) \ c is all check nodes except c connected with the information node v;
as shown in fig. 4, the variable nodes and the check nodes are concepts in an LDPC check matrix Tanner graph, columns of the check matrix represent check nodes C, rows of the check matrix represent information nodes V, and non-zero bits in the check matrix represent that the check nodes are connected with the information nodes, which represents a constraint relationship:
calculating the horizontal update probability according to formula layering, namely rows of the check matrix:
S(add_Ks)=c_in_llr(add_Ks)-Rcv(i,add_Ks);
s4-1-3, calculating the current iteration layer
Figure BDA0003453061400000105
And storing the result and the minimum address index thereof into a temporary cache RAM respectively, recording the result and the minimum address index as min _ cc and cc, and calculating:
Figure BDA0003453061400000106
stored as sub _ min; wherein i means i ∈ [1, n ];
s4-1-4, calculating a sign function:
Figure BDA0003453061400000107
s4-1-5, calculating and storing the level updating probability:
Rcv(i)=α·min_cc·sgn(c_in_llr(i))·sgn_i,i∈Ω(c)\cc;
Rcv(cc)=α·sub_min·sgn(c_in_llr(i))·sgn_i,i∈Ω(i)\cc;
s4-2, performing one round of vertical updating;
in the present embodiment, step S4-2 further includes the following calculations:
Figure BDA0003453061400000111
S4-3and judging: store result c _ in _ llr (add _ K)siftA) If c _ in _ llr (add _ K)siftA) If < 0, decision KsiftA(add_KsiftA) If not, K is determinedsiftA(add_KsiftA) When it is 0, update Ks={KsiftA,KcB}; wherein add _ KsiftAIs KsiftAA position index of (a);
s4-4, if the decoding times do not reach the maximum iteration times mitier: computing
Figure BDA0003453061400000112
If the result is
Figure BDA0003453061400000113
If the decoding is successful, the output success flag decode _ finish is equal to 1, if the result is not
Figure BDA0003453061400000114
Returning to execute step S4-1; if the decoding times reach the maximum iteration times, outputting a failure flag, namely, a pointer _ reach, returning to wait for decoding again, wherein qcH is an LDPC check matrix;
s5, outputting the final key; if decode _ finish is 1, the final key K is outputendIf all the Output end marks are 1, returning to wait for the decoding of the next round of data;
as shown in FIG. 2, steps S1-S5 each implement a state transition through a state machine that includes the following states:
START _ i: an initial state, jumping to a next state INPUT _ INI _ i when key _ valid is 1 and check _ bit _ valid is 1;
key INPUT and initialization state, when key _ address is 1, jumping to next state INPUT _ INI _ i;
quanti _ Go, data quantization hierarchical state, jump to next state MS _ cui when cin _ llr _ algorithm is 1;
MS _ Cul is the minimum sum decoding state, and when decoding _ finish is 1, the decoding successfully jumps to the next state OUTPUT _ i; when the miter _ reach indicates that the maximum iterative decoding times are reached but the decoding is not successfully carried out, jumping to an initial state START _ i;
OUTPUT _ i, data OUTPUT state, when OUTPUT _ end is 1, the OUTPUT end jumps to initial state START _ i.
The embodiment optimizes the minimum sum decoding algorithm and sets the initial probability in a differentiation manner based on the design of a QKD optical system, the design of a post-processing system and the design environment of error correction codes, improves the convergence degree theoretically by improving the reliability of a public syndrome and taking the syndrome as a standard correction key bit, reduces the iteration times of decoding and improves the speed of error correction. Meanwhile, a state transfer, matrix storage and parallel decoding structure based on a development environment and an operation platform is provided, and the processing and operation speed of the functional hardware module is improved. And a secondary development hardware mode is adopted to realize a parallel error correction decoding process, and the decoding rate is increased, so that the efficiency of the whole QKD system is improved.
Variations and modifications to the above-described embodiments may occur to those skilled in the art from the disclosure and teachings of the above specification. Therefore, the present patent is not limited to the specific embodiments disclosed and described above, and some modifications and variations of the present patent should fall within the scope of the claims of the present patent. In addition, although specific terms are employed herein, such terms are used for convenience of description and are not to be construed as limiting the scope of the invention.

Claims (5)

1. A post-processing system for multi-degree-of-freedom modulation QKD is characterized by comprising a sender Alice and a receiver Bob,
the sender Alice comprises quantum state generating and modulating equipment, an upper computer, an Altera Arria10 development board, a coder, a decoder and a privacy enhancement system; the Altera Arria10 development board is an FPGA hardware acceleration device;
the receiver Bob comprises quantum state detection demodulation equipment, an upper computer, an encoder, a privacy enhancement system and an Altera Arria10 development board;
the quantum state generating and modulating device is connected with the quantum state detection and demodulation device through a quantum channel, and the sender Alice sends the quantum state to the quantum detection and demodulation device of the receiver Bob through the quantum channel;
the encoder, the decoder and the privacy enhancement system of the sender Alice are all arranged on an Altera Arria10 development board of the sender Alice and are connected with an upper computer of the sender Alice; the encoder and the privacy enhancement system of the receiver Bob are both arranged on an Altera Arria10 development board of the receiver Bob and are connected with an upper computer of the receiver Bob, and the upper computer of the sender Alice is connected with the upper computer of the receiver Bob through a classical channel;
the method comprises the steps that a sender Alice and a receiver Bob extract part of position bits through respective upper computers and disclose and calculate a QBER, the QBER is a quantum bit error rate, a safety threshold value is stored in the upper computer of the sender Alice and the upper computer of the receiver Bob, when the QBER is larger than the safety threshold value, a secret key is discarded due to the distribution failure of the secret key, and when the QBER is smaller than the safety threshold value, the QBER is stored; after the upper computer of the sender Alice and the upper computer of the receiver Bob calculate QBER in the position bits of the public part, respectively taking the rest bits as screened key KsiftAAnd the screened secret key KsiftBSending the data to respective encoders for encoding;
the sender Alice generates a check bit K by the encoder of the sender AlicecAAnd the screened key KsiftAInputting the data into a decoder of the sender Alice; the encoder of the receiver Bob generates a check bit KcBSending the quantum state to the upper computer of the sender Alice through the classical channel by the upper computer of the receiver Bob, and then inputting the quantum state into a decoder of the sender Alice for decoding;
when the sender Alice successfully decodes, the generated error-corrected secret key KrecInputting the secrecy enhancement system of the sender Alice, simultaneously sending a sign of successful decoding, and sending the sign to the upper computer of the receiver Bob through the classical channel by the upper computer of the sender Alice, thereby controlling the screened secret key K of the receiver BobsiftBEntering a privacy enhancement system of a receiver Bob;
the privacy enhancement system of the sender Alice and the receiver Bob is finishedAfter working, the final key K will be sentendAnd the data are stored in respective upper computers, the whole process of the QKD is finished, and the two communication parties obtain completely consistent and safe keys.
2. The system of claim 1, wherein the sender Alice's encoder, decoder and privacy enhancement system are designed based on the Altera aria 10 development board;
the encoder, privacy enhancement system of the recipient Bob is based on an Altera ariia 10 development board design.
3. An error correction decoding method for multi-degree-of-freedom modulation QKD post-processing, which is applied to the multi-degree-of-freedom modulation QKD post-processing system as claimed in any one of claim 1 or claim 2, and is characterized by comprising the following steps:
s1, inputting a key; the key input further comprises the steps of:
s1-1, inputting the screened secret key K of the sender AlicesiftALength is m;
s1-2, inputting syndrome K sent by receiver BobcBLength of K, the same as KsiftAForm a sub-K to be decodedsThe length is n, and the n is stored in the RAM of the upper computers of the two sides, wherein n is m + k;
s2, initializing differentiation probability; the probability initialization further comprises the steps of:
s2-1, when K is in RAMsCode word position index add _ K ofs∈[1,m]The probability is initialized to:
Figure FDA0003453061390000021
wherein QBER is the quantum bit error rate, and log (-) is a logarithmic function;
s2-2, when the code word position index add _ Ks∈[m+1,n]The probability is initialized to:
Figure FDA0003453061390000022
wherein epsilon is a minimum value;
s3, data layering and quantifying; the hierarchical quantization of data further comprises the steps of:
s3-1, determining a quantization range, namely a probability value range;
s3-2, determining the quantization bit width, namely the probability value difference;
s3-3, inputting the probability information after quantization, and outputting an initialized probability quantization completion flag cin _ llr _ advance equal to 1, and an intermediate probability quantization completion flag cin _ llr _ mid _ advance equal to 1;
s4, carrying out a minimum sum decoding algorithm; the min-sum decoding algorithm further comprises the steps of:
s4-1, when cin _ llr _ alert is equal to 1, carrying out a round of horizontal updating;
s4-2, performing one round of vertical updating;
s4-3, judging: store result c _ in _ llr (add _ K)siftA) If c _ in _ llr (add _ K)siftA) If < 0, decision KsiftA(add_KsiftA) 1, otherwise, the result is KsiftA(add_KsiftA) When it is 0, update Ks={KsiftA,KcB}; wherein add _ KsiftAIs KsiftAA position index of (a);
s4-4, if the decoding times do not reach the maximum iteration times mitier: computing
Figure FDA0003453061390000031
If the result is
Figure FDA0003453061390000032
Decoding is successful, the output success flag decode _ finish is 1, if the result is not
Figure FDA0003453061390000033
Returning to execute step S4-1; if the decoding times reach the maximum iteration times, outputtingA failure flag, namely, a pointer _ reach, returns to wait for decoding again, wherein qcH is an LDPC check matrix;
s5, outputting the final key; if decode _ finish is 1, the final key K is outputendIf all the Output end marks are 1, returning to wait for the decoding of the next round of data;
steps S1-S5 each implement a state transition by a state machine comprising the following states:
START _ i: an initial state, jumping to a next state INPUT _ INI _ i when key _ valid is 1 and check _ bit _ valid is 1;
key INPUT and initialization state, when key _ address is 1, jumping to next state INPUT _ INI _ i;
quanti _ Go, data quantization hierarchical state, jump to next state MS _ cui when cin _ llr _ algorithm is 1;
MS _ Cul is the minimum sum decoding state, when decoding _ finish is 1, the decoding is successfully jumped to the next state OUTPUT _ i; when the miter _ reach indicates that the maximum iterative decoding times are reached but the decoding is not successfully carried out, jumping to an initial state START _ i;
OUTPUT _ i, data OUTPUT state, when OUTPUT _ end is 1, the OUTPUT end jumps to initial state START _ i.
4. The error correction decoding method according to claim 3, wherein the step S4-1 further comprises the steps of:
s4-1-1, setting RAMRcv(i,add_Ks) The dimension is (m multiplied by n) and is used for storing the horizontal checking result and initializing and resetting;
s4-1-2, according to two formulas:
Figure FDA0003453061390000041
wherein the content of the first and second substances,
Figure FDA0003453061390000042
for the horizontal check probability of the (c, v) th memory in the k-th iteration, omega (c) \ vDetermining the optimal normalization parameters for all information nodes connected with the check node c except for v, wherein alpha is a normalization parameter and the range is (0, 1), and the optimal normalization parameter is determined through simulation;
Figure FDA0003453061390000043
wherein the content of the first and second substances,
Figure FDA0003453061390000044
as the vertical check probability of the (c, v) th memory in the kth iteration, psi (v) \ c is all check nodes except c connected with the information node v;
calculating the horizontal update probability according to a formula in a layered mode:
S(add_Ks)=c_in_llr(add_Ks)-Rcv(i,add_Ks);
s4-1-3, calculating the current iteration layer
Figure FDA0003453061390000045
And storing the result and the minimum address index thereof into a temporary cache RAM respectively, recording the result and the minimum address index as min _ cc and cc, and calculating:
Figure FDA0003453061390000046
stored as sub _ min; wherein i means i ∈ [1, n ];
s4-1-4, calculating a sign function:
Figure FDA0003453061390000047
s4-1-5, calculating and storing the level updating probability:
Rcv(i)=α·min_cc·sgn(c_in_llr(i))·sgn_i,i∈Ω(c)\cc;
Rcv(cc)=α·sub_min·sgn(c_in_llr(i))·sgn_i,i∈Ω(i)\cc。
5. the error correction decoding method according to claim 4, wherein the step S4-2 further comprises the following calculation:
Figure FDA0003453061390000051
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