CN114530413B - Array substrate and manufacturing method thereof - Google Patents
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- CN114530413B CN114530413B CN202210159201.0A CN202210159201A CN114530413B CN 114530413 B CN114530413 B CN 114530413B CN 202210159201 A CN202210159201 A CN 202210159201A CN 114530413 B CN114530413 B CN 114530413B
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- 239000000758 substrate Substances 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 154
- 229920002120 photoresistant polymer Polymers 0.000 claims description 224
- 229910044991 metal oxide Inorganic materials 0.000 claims description 66
- 150000004706 metal oxides Chemical class 0.000 claims description 66
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 20
- 239000001301 oxygen Substances 0.000 claims description 20
- 229910052760 oxygen Inorganic materials 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 10
- 238000004380 ashing Methods 0.000 claims description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 9
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000037230 mobility Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 206010021143 Hypoxia Diseases 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses an array substrate and a manufacturing method thereof, wherein the array substrate comprises: a substrate; a gate electrode and a scan line formed on the substrate, the gate electrode being electrically connected to the scan line; a gate insulating layer covering the gate electrode and the scan line; a first oxide semiconductor layer formed on the gate insulating layer; a second oxide semiconductor layer formed over the first oxide semiconductor layer, the second oxide semiconductor layer covering the first oxide semiconductor layer, portions of the first oxide semiconductor layer being exposed from both sides of the second oxide semiconductor layer, respectively; and a source electrode and a drain electrode formed on the first oxide semiconductor layer, the source electrode and the drain electrode being respectively in direct contact with and connected to the first oxide semiconductor layer exposed from both sides of the second oxide semiconductor layer. The array substrate and the manufacturing method thereof effectively improve the on-state current of the TFT.
Description
Technical Field
The invention relates to the technical field of display equipment, in particular to an array substrate and a manufacturing method thereof.
Background
Currently, metal oxide semiconductors have the advantages of high mobility and low leakage current, and are widely used in thin film transistors (Thin Film Transistor, TFTs) of various display devices, whereas conventional TFT architectures are mostly Back Channel Etched (BCE) TFTs; when the source/drain electrode is etched, the metal oxide semiconductor is easily damaged, resulting in deterioration of the TFT performance. In addition, when an insulating layer is deposited above the source drain metal layer, a large amount of H ions are contained in the film forming gas, the H ions have strong activity, and the penetration into the metal oxide semiconductor can cause the threshold voltage shift of the metal oxide TFT, so that the leakage current is increased and even the characteristics of the semiconductor are lost.
Disclosure of Invention
In view of this, the invention provides an array substrate and a manufacturing method thereof, which effectively improves the on-state current of a TFT.
The manufacturing method of the array substrate comprises the following steps:
A substrate is provided and a substrate is provided,
Forming a first metal layer on a substrate, and performing patterning treatment on the first metal layer to form a grid electrode and a scanning line, wherein the grid electrode is in conductive connection with the scanning line;
Forming a gate insulating layer covering the gate electrode and the scan line on the substrate;
Sequentially forming a first metal oxide layer and a first photoresist layer on the gate insulating layer;
Exposing the first photoresist layer by using a half-tone mask plate, wherein the half-tone mask plate comprises a first opaque region, a second opaque region, a first semi-opaque region and a first full-transparent region, the first opaque region and the second opaque region respectively correspond to a first photoresist part and a second photoresist part, the first semi-opaque region corresponds to a third photoresist part, and the first photoresist part and the second photoresist part are respectively positioned at two sides of the third photoresist part;
Developing the first photoresist layer, reserving the first photoresist part, the second photoresist part and the third photoresist part, and removing the first photoresist layer in other areas, wherein the thicknesses of the first photoresist part and the second photoresist part are larger than that of the third photoresist part;
etching to remove the first metal oxide layer which does not cover the first, second and third photoresist parts under the protection of the first, second and third photoresist parts to form a first oxide semiconductor layer;
Ashing and thinning the first photoresist part, the second photoresist part and the third photoresist part simultaneously, removing the third photoresist part and reserving the first photoresist part and the second photoresist part, so that a channel region for covering the second oxide semiconductor layer is formed between the first photoresist part and the second photoresist part;
Sequentially forming a second metal oxide layer and a second photoresist layer covering the first oxide semiconductor layer, the first photoresist portion and the second photoresist portion on the gate insulating layer, wherein the oxygen content of the second metal oxide layer is greater than that of the first oxide semiconductor layer;
exposing and developing the second photoresist layer;
patterning the second metal oxide layer, stripping the first photoresist part, the second photoresist part and the second photoresist layer to form a second oxide semiconductor layer covering the channel region, wherein the first oxide semiconductor layer is exposed from two sides of the second oxide semiconductor layer;
Forming a second metal layer covering the first oxide semiconductor layer and the second oxide semiconductor layer on the gate insulating layer, performing patterning treatment on the second metal layer to enable the second metal layer to form a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively covered on the first oxide semiconductor layer and the second oxide semiconductor layer from two sides of the first oxide semiconductor layer, and the source electrode and the drain electrode are arranged at intervals and are connected with the first oxide semiconductor layer.
In an embodiment of the present invention, the exposing and developing of the second photoresist layer includes:
Exposing the second photoresist layer by using the halftone mask plate for exposing the first photoresist layer, wherein the first opaque region corresponds to a fourth photoresist portion, the second opaque region corresponds to a fifth photoresist portion, the first semi-opaque region corresponds to a sixth photoresist portion, the sixth photoresist portion is arranged corresponding to the channel region, and the orthographic projections of the fourth photoresist portion, the fifth photoresist portion and the sixth photoresist portion on the substrate coincide with the orthographic projection of the first oxide semiconductor layer on the substrate;
And developing the second photoresist layer, reserving the fourth photoresist part, the fifth photoresist part and the sixth photoresist part, and removing the second photoresist layer in other areas to expose the second metal oxide layer.
In an embodiment of the present invention, the exposing and developing of the second photoresist layer includes:
exposing the second photoresist layer by using a mask plate, wherein the mask plate comprises a third light-tight region and a second full-light-tight region, the third light-tight region at least corresponds to the channel region, and the second full-light-tight region corresponds to other regions;
And developing the second photoresist layer, at least reserving the second photoresist layer of the channel region, and removing the second photoresist layer of other regions to expose the second metal oxide layer.
In an embodiment of the present invention, when the mask plate is used to expose the second photoresist layer, the third opaque region at least corresponds to a portion of the first photoresist portion and a portion of the second photoresist portion.
In an embodiment of the present invention, patterning the second metal oxide layer, and stripping the first photoresist portion, the second photoresist portion, and the second photoresist layer to form the second oxide semiconductor layer covering the channel region, wherein the exposing of the first oxide semiconductor layer from both sides of the second oxide semiconductor layer includes:
And etching the second metal oxide layer under the protection of the fourth photoresist part, the fifth photoresist part and the sixth photoresist part to remove the corresponding second metal oxide layer, and reserving the second metal oxide layer corresponding to the fourth photoresist part, the fifth photoresist part and the sixth photoresist part.
And removing the first photoresist part, the second photoresist part, the fourth photoresist part, the fifth photoresist part and the sixth photoresist part by adopting a lift off process, and simultaneously removing the second metal oxide layer outside the channel region to enable the second metal oxide layer to form the second oxide semiconductor layer.
In an embodiment of the present invention, the above manufacturing method further includes:
Forming a first insulating layer covering the source electrode, the drain electrode, and the second oxide semiconductor layer on the gate insulating layer;
Forming a first transparent conducting layer on the first insulating layer in a whole surface, and carrying out patterning treatment on the first transparent conducting layer to enable the first transparent conducting layer to form a common electrode;
forming a second insulating layer covering the common electrode on the first insulating layer;
and forming a second transparent conducting layer on the whole surface of the second insulating layer, carrying out patterning treatment on the second transparent conducting layer to enable the second transparent conducting layer to form a pixel electrode, wherein the pixel electrode is arranged corresponding to the public electrode, and the pixel electrode is connected with the drain electrode in a conducting manner.
In an embodiment of the present invention, the above manufacturing method further includes:
Forming a first insulating layer covering the source electrode, the drain electrode, and the second oxide semiconductor layer on the gate insulating layer;
forming a planar layer on the first insulating layer, forming a first transparent conductive layer on the planar layer, and performing patterning treatment on the first transparent conductive layer to form a common electrode on the first transparent conductive layer;
Forming a second insulating layer covering the common electrode on the planarization layer;
and forming a second transparent conducting layer on the whole surface of the second insulating layer, carrying out patterning treatment on the second transparent conducting layer to enable the second transparent conducting layer to form a pixel electrode, wherein the pixel electrode is arranged corresponding to the public electrode, and the pixel electrode is connected with the drain electrode in a conducting manner.
An array substrate, the array substrate is manufactured by the manufacturing method of the array substrate, and the array substrate comprises:
A substrate;
A gate electrode and a scan line formed on the substrate, the gate electrode being electrically connected to the scan line;
A gate insulating layer covering the gate electrode and the scan line;
A first oxide semiconductor layer formed on the gate insulating layer;
A second oxide semiconductor layer formed over the first oxide semiconductor layer, the second oxide semiconductor layer covering the first oxide semiconductor layer, portions of the first oxide semiconductor layer being exposed from both sides of the second oxide semiconductor layer, respectively;
and a source electrode and a drain electrode formed on the first oxide semiconductor layer, the source electrode and the drain electrode being respectively in direct contact with and connected to the first oxide semiconductor layer exposed from both sides of the second oxide semiconductor layer.
In an embodiment of the present invention, the source electrode and the drain electrode further cover the second oxide semiconductor layer, respectively, and the source electrode and the drain electrode are disposed at intervals.
In an embodiment of the present invention, a width of a stacked position of the source electrode and the first oxide semiconductor layer and a stacked position of the drain electrode and the first oxide semiconductor layer is1 μm or more.
According to the array substrate and the manufacturing method, as the oxygen content of the second oxide semiconductor layer is high, the diffusion of H ions into the first oxide semiconductor layer can be effectively prevented, and therefore the IV characteristics and the stability of the TFT are improved. In addition, no matter when the first oxide semiconductor layer or the second oxide semiconductor layer is manufactured, the corresponding first photoresist layer or the second photoresist layer is covered, so that the manufacturing method of the array substrate of the embodiment of the invention can protect the first oxide semiconductor layer in the whole flow, ensure that the first oxide semiconductor layer is not affected by any etching, and even if the second oxide semiconductor layer is slightly damaged in the subsequent etching process of the source electrode and the drain electrode, the characteristics of the first oxide semiconductor layer are not affected. Meanwhile, the source electrode and the drain electrode are in direct conductive contact with the first oxide semiconductor layer, and the first oxide semiconductor layer is low in oxygen content, high in carrier concentration and small in resistance, so that the contact resistance of the source electrode and the drain electrode with the first oxide semiconductor layer is low, the source electrode, the drain electrode and the first oxide semiconductor layer form good ohmic contact, on-state current of the TFT is effectively improved, and comprehensive performance of the array substrate is optimized.
Drawings
Fig. 1 to 20 are schematic cross-sectional manufacturing flow diagrams of a manufacturing method of an array substrate according to a first embodiment of the invention;
FIG. 21 is a schematic plan view of the array substrate shown in FIG. 7;
FIG. 22 is a schematic plan view of the array substrate shown in FIG. 11;
fig. 23 to 28 are schematic cross-sectional manufacturing flow diagrams of a manufacturing method of an array substrate according to a second embodiment of the invention.
Detailed Description
For the convenience of understanding of those skilled in the art, the following examples are provided to illustrate specific implementation procedures of the technical solution provided in the present application.
First embodiment
As shown in fig. 1 to 22, a first embodiment of the present invention provides a method for manufacturing an array substrate.
S1: the manufacturing method comprises the following steps: as shown in fig. 1, a substrate 10 is provided, and the substrate 10 may be made of glass, quartz, acrylic, polycarbonate, or the like. A first metal layer 11 is formed on the substrate 10, and the first metal layer 11 is patterned to form a gate 111 (see fig. 2) and a scan line 112 (see fig. 22), where the gate 111 is electrically connected to the scan line 112, and the first metal layer 11 may be made of copper and molybdenum niobium (Cu/MoNb) or copper and molybdenum (Cu/Mo).
S2: the manufacturing method further comprises the following steps: as shown in fig. 3, a gate insulating layer 12 covering the gate electrode 111 and the scan line 112 is formed on the substrate; the gate insulating layer 12 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.
S3: the manufacturing method further comprises the following steps: first, as shown in fig. 4, the first metal oxide layer 13 and the first photoresist layer 14 are sequentially formed over the gate insulating layer 12. The first metal oxide layer 13 is, for example, indium Gallium Zinc Oxide (IGZO). Specifically: indium gallium zinc oxide is a mixed oxide doped with indium (In) and gallium (Ga) elements based on zinc oxide (ZnO), and the main function of indium and gallium as doping elements is to adjust carrier concentration. The carriers of the indium gallium zinc oxide are mainly generated by Oxygen Vacancies (OV), and under a specific external environment, the metal oxide can cause Oxygen in the crystal lattice to be separated so as to cause Oxygen deficiency, so that Oxygen vacancies are formed. The greater the number of oxygen vacancies, the higher the carrier concentration and vice versa. Therefore, the carrier concentration can be adjusted by controlling the oxygen content, so that the oxide semiconductor layers have different electron mobilities.
As shown in fig. 5, the first photoresist layer 14 is then exposed by using a halftone mask 15, and the halftone mask 15 includes a first opaque region 151, a second opaque region 152, a first semi-opaque region 153 and a first fully-opaque region 154, the first opaque region 151 and the second opaque region 152 respectively correspond to the first photoresist portion 141 and the second photoresist portion 142, the first semi-opaque region 153 corresponds to the third photoresist portion 143, and the first photoresist portion 141 and the second photoresist portion 142 are respectively located at two sides of the third photoresist portion 143.
As shown in fig. 6, the first photoresist layer 14 is developed, the first photoresist portion 141, the second photoresist portion 142 and the third photoresist portion 143 are remained, the first photoresist layer 14 is removed in other areas, and the thicknesses of the first photoresist portion 141 and the second photoresist portion 142 are larger than the thickness of the third photoresist portion 143.
Finally, under the protection of the first photoresist portion 141, the second photoresist portion 142 and the third photoresist portion 143, the first metal oxide layer 13 not covering the first photoresist portion 141, the second photoresist portion 142 and the third photoresist portion 143 is etched away to form the first oxide semiconductor layer 131. The first metal oxide layer 13 may be etched and removed by wet etching or dry etching, and the first oxide semiconductor layer 131 is completely covered with the first photoresist portion 141, the second photoresist portion 142, and the third photoresist portion 143, so that the first oxide semiconductor layer 131 is not damaged during the wet etching or the dry etching.
S4: the manufacturing method further comprises the following steps: as shown in fig. 7, ashing and thinning processes are simultaneously performed on the first photoresist portion 141, the second photoresist portion 142, and the third photoresist portion 143, the third photoresist portion 143 is removed, and the first photoresist portion 141 and the second photoresist portion 142 remain, so that a channel region for covering the second oxide semiconductor layer 161 is formed between the first photoresist portion 141 and the second photoresist portion 142. In this embodiment, since only the third photoresist portion 143 is removed and the first photoresist portion 141 and the second photoresist portion 142 are remained, compared with the prior art in which the first photoresist portion 141, the second photoresist portion 142 and the third photoresist portion 143 are removed simultaneously, the method can completely ensure that the first photoresist portion 141 and the second photoresist portion 142 can protect the corresponding first oxide semiconductor layer 131 from etching in the whole process when the second metal oxide layer 16 is etched later.
S5: as shown in fig. 8, a second metal oxide layer 16 and a second photoresist layer 17 are sequentially formed on the gate insulating layer 12 to cover the first oxide semiconductor layer 131, the first photoresist portion 141 and the second photoresist portion 142. The second metal oxide layer 16 is, for example, indium Gallium Zinc Oxide (IGZO), and the oxygen content of the second metal oxide layer 16 is greater than that of the first oxide semiconductor layer 131. And the method of forming the second metal oxide layer 16 having an oxygen content greater than that of the first oxide semiconductor layer 131 includes, for example: when the first metal oxide layer 13 is deposited, the flow ratio of oxygen to argon entering the film coating chamber is x to y, wherein the range of x is 0-3, and the range of y is 5-20; when depositing the second metal oxide layer 16, the flow ratio of oxygen to argon entering the coating chamber is a:b, wherein a ranges from 3 to 10, and b ranges from 5 to 20; and x: y is smaller than a: b, i.e., the flow rate of oxygen and argon is higher when the second metal oxide layer 16 is deposited than when the first metal oxide layer 13 is deposited, thus making the oxygen content of the second metal oxide layer 16 larger than that of the first oxide semiconductor layer 131.
For example, when the first metal oxide layer 13 is deposited, the oxygen flow rate into the film plating chamber is 0 standard milliliter per minute (SCCM) and the argon flow rate is 10 standard milliliters per minute (SCCM). Taking a: b=2:10 as an example, specifically, for example, the oxygen flow rate into the plating chamber at the time of depositing the second metal oxide layer 16 is 2 standard state milliliters/minute (SCCM), and the argon flow rate is 10 standard state milliliters/minute (SCCM).
S6: the manufacturing method further comprises the following steps: the second photoresist layer 17 is exposed. In the present embodiment, the second photoresist layer 17 is exposed by using the halftone mask plate 15 exposing the first photoresist layer 14 when the second photoresist layer 17 is exposed. Therefore, one mask plate for exposing the second photoresist layer 17 independently can be saved
As shown in fig. 9, the first opaque region 151 corresponds to the fourth photoresist portion 171, the second opaque region 152 corresponds to the fifth photoresist portion 172, the semi-opaque region corresponds to the sixth photoresist portion 173, the sixth photoresist portion 173 is disposed corresponding to the channel region, and the orthographic projections of the fourth photoresist portion 171, the fifth photoresist portion 172 and the sixth photoresist portion 173 on the substrate overlap with the orthographic projection of the first oxide semiconductor layer 131 on the substrate.
S7: the manufacturing method further comprises the following steps: as shown in fig. 10, the second photoresist layer 17 is developed, the fourth photoresist portion 171, the fifth photoresist portion 172 and the sixth photoresist portion 173 are remained, and the second photoresist layer 17 is removed in other areas to expose the second metal oxide layer 16.
S8: the manufacturing method further comprises the following steps: as shown in fig. 11, the second metal oxide layer 16 is subjected to patterning treatment, and the fourth photoresist portion 171, the fifth photoresist portion 172, and the sixth photoresist portion 173 are stripped, so that the second metal oxide layer 16 forms a second oxide semiconductor layer 161 covering the channel region, and the first oxide semiconductor layer 131 is exposed from both sides of the second oxide semiconductor layer 161.
Wherein patterning the second metal oxide layer 16 comprises: the second metal oxide layer 16 is etched under the protection of the fourth photoresist portion 171, the fifth photoresist portion 172 and the sixth photoresist portion 173, the corresponding second metal oxide layer 16 is removed, and the second metal oxide layer 16 corresponding to the fourth photoresist portion 171, the fifth photoresist portion 172 and the sixth photoresist portion 173 remains.
The first, second, third, fourth, fifth, and sixth photoresist portions 141, 142, 143, 171, 172, 173 are removed by lift off, and the second metal oxide layer 16 outside the channel region is removed to form the second oxide semiconductor layer 161 from the second metal oxide layer 16. In this embodiment, when etching the exposed second metal oxide layer 16, wet etching or dry etching may be used, and the second metal oxide layer 16 on which the second oxide semiconductor layer 161 needs to be formed is completely covered by the fourth photoresist portion 171, the fifth photoresist portion 172 and the sixth photoresist portion 173, so that the second metal oxide layer 16 is not damaged during wet etching or dry etching, and has good ohmic contact with the source electrode 182 and the drain electrode 181, thereby improving the TFT on-state current.
S9: the manufacturing method further comprises the following steps: as shown in fig. 12 and 13, a second metal layer 18 is formed over the gate insulating layer 12 to cover the first oxide semiconductor layer 131 and the second oxide semiconductor layer 161, the second metal layer 18 is patterned to form a source 182 and a drain 181 over the first oxide semiconductor layer 131 and the second oxide semiconductor layer 161 from both sides of the first oxide semiconductor layer 131, and the source 182 and the drain 181 are each connected to the first oxide semiconductor layer 131 and the second oxide semiconductor layer 161 with a space therebetween. In this embodiment, the second metal layer 18 is patterned, so that the second metal layer 18 forms the source 182 and the drain 181 and also forms the data line, and the data line is electrically connected to the source 182.
S10: the manufacturing method further comprises the following steps: as shown in fig. 14, a first insulating layer 19 covering the source electrode 182, the drain electrode 181, and the second oxide semiconductor layer 161 is formed on the gate insulating layer 12.
Referring to fig. 15 and 16, a first transparent conductive layer 21 is formed on the first insulating layer 19, and the first transparent conductive layer 21 is patterned to form a common electrode 211 on the first transparent conductive layer 21; the first transparent conductive layer 21 is made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In the present embodiment, the first transparent conductive layer 21 is preferably Indium Tin Oxide (ITO).
Referring to fig. 17 and 18, a second insulating layer 22 covering the common electrode 211 is formed on the first insulating layer 19, and the second insulating layer 22 is patterned to form a via hole penetrating the second insulating layer 22 and the first insulating layer 19, wherein the via hole is used for conducting connection between the pixel electrode 231 and the drain electrode 181.
Referring to fig. 19 and 20, a second transparent conductive layer 23 is formed on the second insulating layer 22, and the second transparent conductive layer 23 is electrically connected to the drain electrode 181 after filling the via hole, and the second transparent conductive layer 23 is patterned to form a pixel electrode 231, the pixel electrode 231 is disposed corresponding to the common electrode 211, and the pixel electrode 231 is electrically connected to the drain electrode 181. The second transparent conductive layer 23 is made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In the present embodiment, the second transparent conductive layer 23 is preferably Indium Tin Oxide (ITO).
The invention also provides an array substrate 10, which is manufactured by adopting the manufacturing method of the array substrate 10.
Further, the array substrate includes a base; a gate electrode 111 and a scan line 112 formed on the substrate, the gate electrode 111 being electrically connected to the scan line 112; a gate insulating layer 12 covering the gate 111 and the scan line 112; a first oxide semiconductor layer 131 formed on the gate insulating layer 12; and a second oxide semiconductor layer 161 formed over the first oxide semiconductor layer 131, the second oxide semiconductor layer 161 covering the first oxide semiconductor layer 131, and a portion of the first oxide semiconductor layer 131 being exposed from both sides of the second oxide semiconductor layer 161, respectively.
Further, the width of the first oxide semiconductor layer 131 exposed from each side of the second oxide semiconductor layer 161 is, for example, 1 to 8 μm. The thickness of the first oxide semiconductor layer 131 is, for example, 10 to 90 nm, and the thickness of the second oxide semiconductor layer 161 is, for example, 10 to 90 nm; the width of the first oxide semiconductor layer 131 is, for example, 10 to 20 μm, and the width of the second oxide semiconductor layer 161 is, for example, 4 to 18 μm.
Further, the array substrate further includes a source electrode 182 and a drain electrode 181 formed on the first oxide semiconductor layer 131, and the source electrode 182 and the drain electrode 181 are respectively in direct contact connection with the first oxide semiconductor layer 131 exposed from both sides of the second oxide semiconductor layer 161.
Further, the source electrode 182 and the drain electrode 181 also cover the second oxide semiconductor layer 161, respectively, and the source electrode 182 and the drain electrode 181 are disposed at intervals.
Further, the width of the stacked position of the source electrode 182 and the first oxide semiconductor layer 131 and the stacked position of the drain electrode 181 and the first oxide semiconductor layer 131 is 1 μm or more.
Further, the distance between the source 182 and the drain 181 (i.e., channel length) is, for example, 2 to 8 micrometers.
In the array substrate and the manufacturing method provided by the embodiment of the invention, because the oxygen content of the second oxide semiconductor layer 161 is high, H ions can be effectively prevented from diffusing into the first oxide semiconductor layer 131, and therefore, the current-voltage characteristic and the stability of the TFT are improved. In addition, no matter when the first oxide semiconductor layer 131 or the second oxide semiconductor layer 161 is manufactured, the corresponding first photoresist layer 14 or the second photoresist layer 17 is covered, so the manufacturing method of the array substrate provided by the embodiment of the invention can protect the first oxide semiconductor layer 131 in the whole flow, ensure that the first oxide semiconductor layer 131 is not affected by any etching, and even if the second oxide semiconductor layer 161 is slightly damaged in the subsequent etching process of the source electrode 182 and the drain electrode 181, the characteristics of the first oxide semiconductor layer 131 are not affected. Meanwhile, the source electrode 182 and the drain electrode 181 are in direct conductive contact with the first oxide semiconductor layer 131, and the first oxide semiconductor layer 131 is low in oxygen content, high in carrier concentration and small in resistance, so that the contact resistance between the source electrode 182 and the drain electrode 181 and the first oxide semiconductor layer 131 is low, the source electrode 182 and the drain electrode 181 form good ohmic contact with the first oxide semiconductor layer 131, on-state current of the TFT is effectively improved, and comprehensive performance of the array substrate is optimized.
Second embodiment
As shown in fig. 23 to 28, the structure of the array substrate provided by the second embodiment of the present invention is exactly the same as that of the first embodiment. However, the manufacturing method of the array substrate in this embodiment is different from that of the first embodiment, specifically, the manufacturing method is different from that of the first embodiment S6 to S7, and the other manufacturing methods have the same steps.
Specifically:
S6': the second photoresist layer 17 is exposed by using the mask plate 24, and the mask plate 24 includes a third light-tight region 241 and a second full-transparent region 242, where the third light-tight region 241 at least corresponds to the channel region, and the second full-transparent region 242 corresponds to other regions. In this embodiment, as shown in fig. 23 to 25, the third light-impermeable region 241 and the first oxide semiconductor layer 131 may entirely correspond; as shown in fig. 26 to 28, alignment deviation may be formed with the first oxide semiconductor layer 131 as appropriate; or the first oxide semiconductor layer 131 corresponds to only the channel region. Preferably, the third opaque region 241 corresponds to the first oxide semiconductor layer 131 completely or the third opaque region 241 and the first oxide semiconductor layer 131 are properly aligned, so that the third opaque region 241 at least corresponds to a portion of the first photoresist 141 and a portion of the second photoresist 142, which ensures that the first oxide semiconductor layer 131 is not damaged during the wet etching process.
S7': the second photoresist layer 17 is developed, at least the second photoresist layer 17 in the channel region is remained, and the second photoresist layer 17 in other regions is removed to expose the second metal oxide layer 16.
For other structures and manufacturing methods of the array substrate, please refer to the first embodiment, and the description thereof is omitted.
Third embodiment
The array substrate and the manufacturing method thereof provided in the third embodiment of the present invention are substantially the same as those in the first embodiment, and the difference is that the array substrate in the present embodiment further includes a flat layer and the S10 of the array substrate in the present embodiment is different.
Specifically:
S10': forming a first insulating layer 19 covering the source electrode 182, the drain electrode 181, and the second oxide semiconductor layer 161 on the gate insulating layer 12;
Forming a planar layer on the first insulating layer 19, forming a first transparent conductive layer 21 on the planar layer, and patterning the first transparent conductive layer 21 to form a common electrode 211 on the first transparent conductive layer 21; the first transparent conductive layer 21 is made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In the present embodiment, the first transparent conductive layer 21 is preferably Indium Tin Oxide (ITO).
A second insulating layer 22 covering the common electrode 211 is formed on the planarization layer.
The second transparent conductive layer 23 is formed on the entire surface of the second insulating layer 22, and the second transparent conductive layer 23 is patterned to form the pixel electrode 231 on the second transparent conductive layer 23, the pixel electrode 231 is disposed corresponding to the common electrode 211, and the pixel electrode 231 is electrically connected to the drain electrode 181. The second transparent conductive layer 23 is made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In the present embodiment, the second transparent conductive layer 23 is preferably Indium Tin Oxide (ITO).
For other structures and manufacturing methods of the array substrate, please refer to the second embodiment, and the description thereof is omitted.
In this document, terms such as up, down, left, right, front, rear, etc. are defined by the positions of the structures in the drawings and the positions of the structures with respect to each other, for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of directional terms should not be construed to limit the scope of the application as claimed. It should also be understood that the terms "first" and "second," etc., as used herein, are used merely for distinguishing between names and not for limiting the number and order.
The present invention is not limited to the above embodiments, but is capable of being modified or altered in various ways by persons skilled in the art without departing from the scope of the invention.
Claims (10)
1. The manufacturing method of the array substrate is characterized by comprising the following steps of:
Providing a substrate (10),
Forming a first metal layer (11) on the substrate (10), and performing patterning treatment on the first metal layer (11) to form a grid electrode (111) and a scanning line (112), wherein the grid electrode (111) is in conductive connection with the scanning line (112);
forming a gate insulating layer (12) covering the gate electrode (111) and the scan line (112) on the substrate (10);
sequentially forming a first metal oxide layer (13) and a first photoresist layer (14) on the gate insulating layer (12);
Exposing the first photoresist layer (14) by using a half-tone mask plate (15), wherein the half-tone mask plate (15) comprises a first opaque region (151), a second opaque region (152), a first half-opaque region (153) and a first full-opaque region (154), the first opaque region (151) and the second opaque region (152) correspond to a first photoresist part (141) and a second photoresist part (142) respectively, the first half-opaque region (153) corresponds to a third photoresist part (143), and the first photoresist part (141) and the second photoresist part (142) are respectively positioned at two sides of the third photoresist part (143);
Developing the first photoresist layer (14), and reserving the first photoresist portion (141), the second photoresist portion (142) and the third photoresist portion (143), wherein the first photoresist layer (14) is removed from other areas, and the thicknesses of the first photoresist portion (141) and the second photoresist portion (142) are larger than the thickness of the third photoresist portion (143);
Etching to remove the first metal oxide layer (13) not covering the first, second and third photoresist portions (141, 142, 143) under the protection of the first, second and third photoresist portions (141, 142, 143) to form a first oxide semiconductor layer (131);
ashing and thinning the first photoresist portion (141), the second photoresist portion (142) and the third photoresist portion (143) simultaneously, removing the third photoresist portion (143) and reserving the first photoresist portion (141) and the second photoresist portion (142), so that a channel region for covering the second oxide semiconductor layer (161) is formed between the first photoresist portion (141) and the second photoresist portion (142);
A second metal oxide layer (16) and a second photoresist layer (17) which cover the first oxide semiconductor layer (131), the first photoresist portion (141) and the second photoresist portion (142) are sequentially formed on the gate insulating layer (12), wherein the oxygen content of the second metal oxide layer (16) is greater than the oxygen content of the first oxide semiconductor layer (131);
Exposing and developing the second photoresist layer (17);
Patterning the second metal oxide layer (16), and stripping the first photoresist portion (141), the second photoresist portion (142) and the second photoresist layer (17), so that the second metal oxide layer (16) forms the second oxide semiconductor layer (161) covering the channel region, and the first oxide semiconductor layer (131) is exposed from both sides of the second oxide semiconductor layer (161);
forming a second metal layer (18) covering the first oxide semiconductor layer (131) and the second oxide semiconductor layer (161) on the gate insulating layer (12), performing patterning treatment on the second metal layer (18) to enable the second metal layer (18) to form a source electrode (182) and a drain electrode (181), wherein the source electrode (182) and the drain electrode (181) are respectively covered on the first oxide semiconductor layer (131) and the second oxide semiconductor layer (161) from two sides of the first oxide semiconductor layer (131), and the source electrode (182) and the drain electrode (181) are arranged at intervals and are connected with the first oxide semiconductor layer (131).
2. The method of manufacturing an array substrate according to claim 1, wherein exposing and developing the second photoresist layer (17) comprises:
Exposing the second photoresist layer (17) by using the halftone mask plate (15) for exposing the first photoresist layer (14), wherein the first opaque region (151) corresponds to a fourth photoresist portion (171), the second opaque region (152) corresponds to a fifth photoresist portion (172), the first semi-opaque region (153) corresponds to a sixth photoresist portion (173), the sixth photoresist portion (173) is arranged corresponding to the channel region, and the orthographic projections of the fourth photoresist portion (171), the fifth photoresist portion (172) and the sixth photoresist portion (173) on the substrate (10) coincide with the orthographic projection of the first oxide semiconductor layer (131) on the substrate (10);
And developing the second photoresist layer (17), and reserving the fourth photoresist portion (171), the fifth photoresist portion (172) and the sixth photoresist portion (173), wherein other areas remove the second photoresist layer (17) to expose the second metal oxide layer (16).
3. The method of manufacturing an array substrate according to claim 1, wherein exposing and developing the second photoresist layer (17) comprises:
Exposing the second photoresist layer (17) by using a mask plate (24), wherein the mask plate (24) comprises a third light-tight region (241) and a second full-transparent region (242), the third light-tight region (241) at least corresponds to the channel region, and the second full-transparent region (242) corresponds to other regions;
-developing the second photoresist layer (17), leaving at least the second photoresist layer (17) of the channel region, and removing the second photoresist layer (17) of other regions to expose the second metal oxide layer (16).
4. The method of manufacturing an array substrate according to claim 3, wherein when the mask (24) is used to expose the second photoresist layer (17), the third opaque region (241) at least corresponds to a portion of the first photoresist portion (141) and a portion of the second photoresist portion (142).
5. The method of manufacturing an array substrate according to claim 2, wherein patterning the second metal oxide layer (16), stripping the first photoresist portion (141), the second photoresist portion (142), and the second photoresist layer (17) to form the second metal oxide layer (16) to cover the second oxide semiconductor layer (161) of the channel region, and exposing the first oxide semiconductor layer (131) from both sides of the second oxide semiconductor layer (161) comprises:
Etching the second metal oxide layer (16) under the protection of the fourth photoresist part (171), the fifth photoresist part (172) and the sixth photoresist part (173), removing the corresponding second metal oxide layer (16), and reserving the second metal oxide layer (16) corresponding to the fourth photoresist part (171), the fifth photoresist part (172) and the sixth photoresist part (173);
and removing the first photoresist part (141), the second photoresist part (142), the fourth photoresist part (171), the fifth photoresist part (172) and the sixth photoresist part (173) by using a lift off process, and simultaneously removing the second metal oxide layer (16) outside the channel region, so that the second metal oxide layer (16) forms the second oxide semiconductor layer (161).
6. The method for manufacturing an array substrate according to claim 1, further comprising:
Forming a first insulating layer (19) covering the source electrode (182), the drain electrode (181), and the second oxide semiconductor layer (161) on the gate insulating layer (12);
forming a first transparent conductive layer (21) on the first insulating layer (19), and patterning the first transparent conductive layer (21) to form a common electrode (211) on the first transparent conductive layer (21);
Forming a second insulating layer (22) covering the common electrode (211) on the first insulating layer (19);
And forming a second transparent conductive layer (23) on the whole surface of the second insulating layer (22), performing patterning treatment on the second transparent conductive layer (23) to enable the second transparent conductive layer (23) to form a pixel electrode (231), wherein the pixel electrode (231) is arranged corresponding to the common electrode (211), and the pixel electrode (231) is connected with the drain electrode (181) in a conductive mode.
7. The method for manufacturing an array substrate according to claim 1, further comprising:
Forming a first insulating layer (19) covering the source electrode (182), the drain electrode (181), and the second oxide semiconductor layer (161) on the gate insulating layer (12);
Forming a planar layer on the first insulating layer (19), forming a first transparent conductive layer (21) on the planar layer, and patterning the first transparent conductive layer (21) to form a common electrode (211) on the first transparent conductive layer (21);
Forming a second insulating layer (22) covering the common electrode (211) on the flat layer;
And forming a second transparent conductive layer (23) on the whole surface of the second insulating layer (22), performing patterning treatment on the second transparent conductive layer (23) to enable the second transparent conductive layer (23) to form a pixel electrode (231), wherein the pixel electrode (231) is arranged corresponding to the common electrode (211), and the pixel electrode (231) is connected with the drain electrode (181) in a conductive mode.
8. An array substrate, characterized in that the array substrate is manufactured by the manufacturing method of the array substrate of any one of claims 1-7, and the array substrate comprises:
a substrate (10);
a gate electrode (111) and a scanning line (112) formed on the substrate (10), the gate electrode (111) being electrically connected to the scanning line (112);
a gate insulating layer (12) covering the gate electrode (111) and the scanning line (112);
A first oxide semiconductor layer (131) formed on the gate insulating layer (12);
A second oxide semiconductor layer (161) formed on the first oxide semiconductor layer (131), the second oxide semiconductor layer (161) covering the first oxide semiconductor layer (131), a portion of the first oxide semiconductor layer (131) being exposed from both sides of the second oxide semiconductor layer (161), respectively;
And a source electrode (182) and a drain electrode (181) formed on the first oxide semiconductor layer (131), wherein the source electrode (182) and the drain electrode (181) are respectively in direct contact connection with the first oxide semiconductor layer (131) exposed from both sides of the second oxide semiconductor layer (161).
9. The array substrate according to claim 8, wherein the source electrode (182) and the drain electrode (181) further cover the second oxide semiconductor layer (161), respectively, the source electrode (182) being disposed apart from the drain electrode (181).
10. The array substrate according to claim 8, wherein a width of a stacked position of the source electrode (182) and the first oxide semiconductor layer (131) and a stacked position of the drain electrode (181) and the first oxide semiconductor layer (131) is 1 μm or more.
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