CN114518981A - eMMC test method, device, readable storage medium and electronic equipment - Google Patents
eMMC test method, device, readable storage medium and electronic equipment Download PDFInfo
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Abstract
The invention discloses an eMMC test method, an eMMC test device, a readable storage medium and electronic equipment, wherein a steady-state performance test request of an eMMC chip to be tested is received; according to the steady-state performance test request, carrying out region division on the eMMC chip to be tested according to a first preset capacity to obtain the divided eMMC chip to be tested; performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity, and storing data read-write results corresponding to the data read-write operation; the steady-state performance test result corresponding to the steady-state performance test request is determined based on the data read-write result, the capacity is used as the test dimension for testing, whether the steady-state performance of the eMMC chip is normal can be tested, whether the steady-state performance falls or not can be accurately known, and compared with a test method using time as the test dimension, the method is more convenient, the complexity of the test is reduced, and the convenience of the steady-state performance test can be improved.
Description
Technical Field
The invention relates to the technical field of memories, in particular to an eMMC testing method, an eMMC testing device, a readable storage medium and electronic equipment.
Background
An eMMC chip (Embedded multimedia Card) is widely used in various mobile electronic devices, and its performance is often tested by using android (a benchmark test application). When the eMMC chip is used as the single storage device, if the bandwidth, the time delay, and the IOPS (the number of times of read/write Operations Per Second) in a period of time are tested according to a conventional single steady-state performance testing method, that is, after the period of time to be tested reaches a steady state, a certain period of time (which is always set to 6 hours) is used as a testing time length, the testing method is too complicated for a user who only wants to know whether the steady-state performance has a drop, and a large amount of testing resources are wasted.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: provided are an eMMC test method, an eMMC test device, a readable storage medium and electronic equipment, which can improve the convenience of steady-state performance test.
In order to solve the technical problems, the invention adopts a technical scheme that:
an eMMC test method, comprising:
receiving a steady-state performance test request of an eMMC chip to be tested;
according to the steady-state performance test request, carrying out region division on the eMMC chip to be tested according to a first preset capacity to obtain the divided eMMC chip to be tested;
performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity, and storing data read-write results corresponding to the data read-write operation;
and determining a steady-state performance test result corresponding to the steady-state performance test request based on the data read-write result.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
an eMMC test device, comprising:
the request receiving module is used for receiving a steady-state performance test request of the eMMC chip to be tested;
the area division module is used for carrying out area division on the eMMC chip to be tested according to the steady-state performance test request and a first preset capacity to obtain the divided eMMC chip to be tested;
the test module is used for performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity and storing data read-write results corresponding to the data read-write operation;
and the result determining module is used for determining a steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a method of eMMC testing as described above.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
an electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of an eMMC testing method as described above when executing the computer program.
The invention has the beneficial effects that: the method includes the steps that area division is conducted on the eMMC chip to be tested according to a received steady-state performance test request and a first preset capacity, data read-write operation is conducted on the divided eMMC chip to be tested according to a second preset capacity, data read-write results corresponding to the data read-write operation are stored, steady-state performance test results are determined based on the data read-write results, the steady-state performance test is conducted by taking time as a test dimension instead of the capacity as the test dimension in the prior art, whether the steady-state performance of the eMMC chip is normal or not can be tested, whether the steady-state performance falls or not can be accurately known, compared with a test method with time as the test dimension, the method is more convenient, the complexity degree of the test is reduced, and convenience of the steady-state performance test can be improved.
Drawings
Fig. 1 is a flowchart illustrating steps of an eMMC testing method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an eMMC testing apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to explain the technical contents, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, an embodiment of the present invention provides an eMMC testing method, including:
receiving a steady-state performance test request of an eMMC chip to be tested;
according to the steady-state performance test request, carrying out region division on the eMMC chip to be tested according to a first preset capacity to obtain the divided eMMC chip to be tested;
performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity, and storing data read-write results corresponding to the data read-write operation;
and determining a steady-state performance test result corresponding to the steady-state performance test request based on the data read-write result.
As can be seen from the above description, the beneficial effects of the present invention are: the method includes the steps that area division is conducted on the eMMC chip to be tested according to a received steady-state performance test request and a first preset capacity, data read-write operation is conducted on the divided eMMC chip to be tested according to a second preset capacity, data read-write results corresponding to the data read-write operation are stored, steady-state performance test results are determined based on the data read-write results, the steady-state performance test is conducted by taking time as a test dimension instead of the capacity as the test dimension in the prior art, whether the steady-state performance of the eMMC chip is normal or not can be tested, whether the steady-state performance falls or not can be accurately known, compared with a test method with time as the test dimension, the method is more convenient, the complexity degree of the test is reduced, and convenience of the steady-state performance test can be improved.
Further, before performing the area division on the eMMC chip to be tested according to the steady-state performance test request and the first preset capacity, the method includes:
and writing the eMMC chips to be tested for the preset times according to the steady-state performance test request and the first preset test data to obtain the eMMC chips to be tested in a steady state.
According to the description, the eMMC chips to be tested are ensured to enter the stable state through the sequential writing of the preset times to the whole disk of the eMMC chips to be tested, the condition that the stable state performance test fails due to the fact that the eMMC chips are not in the stable state is eliminated, and the reliability of the stable state performance test result is improved.
Further, the steady-state performance test request comprises a test index;
the step of performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity and storing data read-write results corresponding to the data read-write operation comprises the following steps:
determining a test model corresponding to the test index according to the test index;
and performing data read-write operation on the divided eMMC chips to be tested according to the test model and a second preset capacity, and storing data read-write results corresponding to the data read-write operation according to the test indexes.
According to the description, different test models are determined according to different test indexes, and then data read-write operation is performed on the divided eMMC chips to be tested according to the test models and the second preset capacity, so that flexible eMMC steady-state performance test is achieved.
Further, the test model comprises a sequential read-write model and/or a random read-write model;
the data read-write operation of the divided eMMC chips to be tested according to the second preset capacity according to the test model comprises the following steps:
sequentially selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the sequential read-write model, and performing sequential read-write operation on the sequentially selected second preset capacity;
and randomly selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the random read-write model, and performing random read-write operation on the randomly selected second preset capacity.
As can be seen from the above description, the test model includes a sequential read-write model and/or a random read-write model, a second preset capacity is sequentially selected from each of the first preset capacities of the divided eMMC chips to be tested according to the sequential read-write model, sequential read-write operation is performed on the sequentially selected second preset capacity, a second preset capacity is randomly selected from each of the first preset capacities of the divided eMMC chips to be tested according to the random read-write model, random read-write operation is performed on the randomly selected second preset capacity, partition test can be performed on the eMMC chips, and effectiveness of steady-state performance test is improved.
Further, the test metrics include runtime metrics;
the determining, according to the test index, a test model corresponding to the test index includes:
and determining a first sequential read-write model and a first random read-write model corresponding to the running time index according to the running time index.
According to the above description, when the test index includes the operation time index, the corresponding first sequential read-write model and the corresponding first random read-write model are determined, and the steady-state performance test is subsequently performed according to the first sequential read-write model and the first random read-write model, so that the steady-state performance test with the capacity as the test dimension and the operation time as the test index is realized, and the steady-state performance test can be simply and effectively realized.
Further, the test indicator comprises a bandwidth indicator;
the determining, according to the test index, a test model corresponding to the test index includes:
and determining a second sequential read-write model corresponding to the bandwidth index according to the bandwidth index.
According to the above description, when the test index includes the bandwidth index, the corresponding second sequential read-write model can be determined, and then the test is performed according to the second sequential read-write model, so that the steady-state performance test with the capacity as the test dimension and the bandwidth as the test index is realized, and the simple and effective steady-state performance test can also be realized.
Further, the test index comprises an IOPS index or a time delay index;
the determining, according to the test index, a test model corresponding to the test index includes:
determining a second random read-write model corresponding to the IOPS index according to the IOPS index;
and determining a third random read-write model corresponding to the time delay index according to the time delay index.
As can be seen from the above description, the test index may be the running time and the bandwidth, and may also be the IOPS (number of times of read/write operations per second) and the time delay, and the steady-state performance test on the eMMC can be implemented from multiple angles, so that the applicability and flexibility of the test are improved, and a tester can flexibly select the test according to the actual situation, thereby improving the effectiveness of the steady-state performance test.
Referring to fig. 2, another embodiment of the present invention provides an eMMC testing apparatus, including:
the request receiving module is used for receiving a steady-state performance test request of the eMMC chip to be tested;
the area dividing module is used for carrying out area division on the eMMC chip to be tested according to the steady-state performance test request and a first preset capacity to obtain the divided eMMC chip to be tested;
the test module is used for performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity and storing data read-write results corresponding to the data read-write operation;
and the result determining module is used for determining a steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result.
Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of a method for eMMC testing as described above.
Referring to fig. 3, another embodiment of the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the eMMC testing method when executing the computer program.
The eMMC test method, the eMMC test device, the readable storage medium, and the electronic device according to the present invention can be applied to a test scenario of an eMMC chip, and the following description is provided by specific embodiments:
example one
Referring to fig. 1, an eMMC testing method of the present embodiment includes:
s0, writing the eMMC chips to be tested according to the steady-state performance test request and the first preset test data in a preset frequency sequence to obtain the eMMC chips to be tested in a steady state;
the preset times can be set according to actual conditions, as long as the eMMC chip to be tested can enter a stable state, and in the embodiment, the preset times are 2 times;
specifically, the eMMC chip to be tested is placed in a card reader, connected to a PC (the PC is an ubuntu system), and subjected to full disk sequence writing for 2 times by using an FIO tool (I/O tool) according to the steady-state performance test request and according to first preset test data, so that the eMMC chip to be tested in a steady state is obtained;
s1, receiving a steady-state performance test request of the eMMC chip to be tested;
wherein the steady state performance test request comprises a test index;
the test indexes comprise an operation time index, a bandwidth index, an IOPS index or a time delay index;
s2, performing area division on the eMMC chip to be tested according to the steady-state performance test request and a first preset capacity to obtain the divided eMMC chip to be tested;
the first preset capacity can be set according to an actual situation, and in this embodiment, the first preset capacity is 1G;
for example, the capacity of the to-be-tested eMMC chip is 64G, the to-be-tested eMMC chip is divided into 64 areas according to 1G, and the divided eMMC chips are sequentially divided into 64 1G capacities;
s3, performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity, and storing a data read-write result corresponding to the data read-write operation, which specifically includes:
s31, determining a test model corresponding to the test index according to the test index;
the test model comprises a sequential read-write model and/or a random read-write model;
s32, performing data read-write operation on the divided eMMC chips to be tested according to the test model and a second preset capacity, and storing data read-write results corresponding to the data read-write operation according to the test indexes, which specifically includes:
s321, sequentially selecting a second preset capacity from each first preset capacity of the divided eMMC chip to be tested according to the sequential read-write model, and performing sequential read-write operation on the sequentially selected second preset capacity;
the second preset capacity may refer to a test model of Androbench, and in this embodiment, the second preset capacity is 512M;
s322, randomly selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the random read-write model, and performing random read-write operation on the randomly selected second preset capacity;
s323, storing a data read-write result corresponding to the data read-write operation according to the test index;
s4, determining a steady-state performance test result corresponding to the steady-state performance test request based on the data read-write result;
in an alternative embodiment, the step S3 may be repeated multiple times to ensure sufficient test sampling number, thereby improving the reliability of the steady-state performance test result.
Example two
Referring to fig. 1, a difference between the first embodiment and the second embodiment lies in that a steady-state performance test is implemented according to an operation time index, which specifically includes:
the S31 specifically includes:
determining a first sequential read-write model and a first random read-write model corresponding to the running time index according to the running time index;
when the test index is the run-time index, the S32 includes the S321, the S322, and the S323: the first sequential read-write model is a 512k sequential read-write model, and the first random read-write model is a 4k random read-write model;
the S321 specifically includes:
sequentially selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the first sequential read-write model, and performing sequential read-write operation on the sequentially selected second preset capacity;
specifically, 512M is selected from each 1G capacity of the divided eMMC chip to be tested according to a LBA Address (logical Block Address ) sequence, 512k sequential reading is performed on 64 512M, and then 512k sequential writing is performed on 64 512M;
the S322 specifically includes:
randomly selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the first random read-write model, and performing random read-write operation on the randomly selected second preset capacity;
specifically, 512M is randomly selected from each 1G capacity of the divided eMMC chips to be tested, 64 512M are respectively subjected to 4k random reading, and then 64 512M are respectively subjected to 4k random writing;
the S323 specifically comprises:
storing a data reading and writing time result corresponding to the data reading and writing operation according to the running time index;
specifically, after 512k finishes sequentially reading each 512M, the sequential reading time is saved, and 64 sequential reading times are total, after 512k finishes sequentially writing each 512M, the sequential writing time is saved, 64 sequential writing times are total, after 4k finishes randomly reading each 512M, the random reading time is saved, 64 random reading times are total, and after 4k finishes randomly writing each 512M, the random writing time is saved, and 64 random writing times are total;
the S4 specifically includes:
s41, generating a time curve graph according to the data reading and writing time result;
specifically, a sequential read time curve graph is generated according to 64 sequential read times, a sequential write time curve graph is generated according to 64 sequential write times, a random read time curve graph is generated according to 64 random read times, and a random write time curve graph is generated according to 64 random write times;
s42, determining a steady-state performance test result corresponding to the steady-state performance test request based on the time curve graph;
specifically, determining the maximum time and the minimum time in each time curve graph, and judging whether the difference value between the maximum time and the minimum time in each time curve graph does not exceed a first preset proportion, if so, passing the steady-state performance test, and if not, failing to pass the steady-state performance test;
wherein the first preset proportion is 10%.
EXAMPLE III
Referring to fig. 1, the difference between the present embodiment and the first or second embodiment is that the steady-state performance test is implemented according to the bandwidth index, which specifically includes:
the S31 specifically includes:
determining a second sequential read-write model corresponding to the bandwidth index according to the bandwidth index;
the second sequential read-write model is queue depth 8, 512K sequential read-write;
wherein, the depth of the queue is assigned to 8 through the parameter iododepth in the test tool FIO;
when the test index is a bandwidth index, the S32 includes the S321 and the S323:
the S321 specifically includes:
sequentially selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the second sequential read-write model, and performing sequential read-write operation on the sequentially selected second preset capacity;
specifically, 512M is selected from each 1G capacity of the divided eMMC chip to be tested according to the LBA address sequence according to the queue depth 8, 512k sequential reading is performed on 64 512M, and then 512k sequential writing is performed on 64 512M;
the S323 specifically comprises:
storing a data read-write bandwidth result corresponding to the data read-write operation according to the bandwidth index;
specifically, after each 512M is sequentially read by 512k, the sequential read bandwidth is stored, and the total sequential read bandwidth is 64, and after each 512M is sequentially written by 512k, the sequential write bandwidth is stored, and the total sequential write bandwidth is 64;
the S4 specifically includes:
s41, generating a bandwidth curve graph according to the data read-write bandwidth result;
specifically, a sequential read bandwidth graph is generated according to 64 sequential read times, and a sequential write bandwidth graph is generated according to 64 sequential write times;
s42, determining a steady-state performance test result corresponding to the steady-state performance test request based on the bandwidth curve graph;
specifically, determining a maximum bandwidth and a minimum bandwidth in each bandwidth curve graph, and judging whether the difference value between the maximum bandwidth and the minimum bandwidth in each bandwidth curve graph does not exceed a second preset proportion, if so, passing the steady-state performance test, and if not, passing the steady-state performance test;
wherein the second predetermined proportion is 10%.
Example four
Referring to fig. 1, the difference between the present embodiment and the first, second, or third embodiment is that the steady state performance test is implemented according to the IOPS index, specifically:
the S31 specifically includes:
determining a second random read-write model corresponding to the IOPS index according to the IOPS index;
the second random read-write model is queue depth 8, 4K random read-write;
when the test index is the IOPS index, the S32 includes the S322 and the S323:
the S322 specifically includes:
randomly selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the second random read-write model, and performing random read-write operation on the randomly selected second preset capacity;
specifically, 512M is randomly selected from each 1G capacity of the divided eMMC chips to be tested according to the queue depth 8, 64 512M are respectively subjected to 4k random reading, and then 64 512M are respectively subjected to 4k random writing;
the S323 specifically comprises:
storing a data read-write IOPS result corresponding to the data read-write operation according to the IOPS index;
specifically, after 4k finishes randomly reading each 512M, the random read IOPS is stored, 64 random read IOPS are provided, and after 4k finishes randomly writing each 512M, the random write IOPS is stored, 64 random write IOPS are provided;
the S4 specifically includes:
s41, generating an IOPS graph according to the data reading and writing IOPS result;
specifically, a random reading IOPS graph is generated according to 64 random reading IOPS, and a random writing IOPS graph is generated according to 64 random writing IOPS;
s42, determining a steady-state performance test result corresponding to the steady-state performance test request based on the IOPS graph;
specifically, determining a maximum IOPS and a minimum IOPS in each IOPS graph, and determining whether a difference value between the maximum IOPS and the minimum IOPS in each IOPS graph does not exceed a third preset proportion, if so, passing the steady-state performance test, and if not, passing the steady-state performance test;
wherein the third predetermined proportion is 10%.
EXAMPLE five
Referring to fig. 1, the difference between the present embodiment and the first, second, third, or fourth embodiment lies in that the steady-state performance test is implemented according to the delay indicator, which specifically includes:
the S31 specifically includes:
determining a third random read-write model corresponding to the time delay index according to the time delay index;
the third random read-write model is queue depth 1, 4k random read-write;
when the test index is the time delay index, the S32 includes the S322 and the S323:
the S322 specifically includes:
randomly selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the third random read-write model, and performing random read-write operation on the randomly selected second preset capacity;
specifically, 512M is randomly selected from each 1G capacity of the divided eMMC chips to be tested according to the queue depth 1, 64 512M are respectively subjected to 4k random reading, and then 64 512M are respectively subjected to 4k random writing;
the S323 specifically includes:
storing a data read-write time delay result corresponding to the data read-write operation according to the time delay index;
specifically, after 4k finishes randomly reading each 512M, the random reading time delay is stored, and 64 random reading time delays are stored, and after 4k finishes randomly writing each 512M, the random writing time delay is stored, and 64 random writing time delays are stored;
the S4 specifically includes:
s41, generating a time delay curve graph according to the data reading and writing time delay result;
specifically, a random reading delay curve graph is generated according to 64 random reading delays, and a random writing delay curve graph is generated according to 64 random writing delays;
s42, determining a steady-state performance test result corresponding to the steady-state performance test request based on the time delay curve graph;
specifically, determining the maximum delay and the minimum delay in each delay curve graph, and judging whether the difference value between the maximum delay and the minimum delay in each delay curve graph does not exceed a fourth preset proportion, if so, passing the steady-state performance test, and if not, failing to pass the steady-state performance test;
wherein the fourth predetermined proportion is 10%.
EXAMPLE six
Referring to fig. 2, an eMMC testing apparatus includes:
the request receiving module is used for receiving a steady-state performance test request of the eMMC chip to be tested;
the area division module is used for carrying out area division on the eMMC chip to be tested according to the steady-state performance test request and a first preset capacity to obtain the divided eMMC chip to be tested;
the test module is used for performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity and storing data read-write results corresponding to the data read-write operation;
and the result determining module is used for determining a steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result.
EXAMPLE seven
A computer-readable storage medium, having stored thereon, a computer program that, when executed by a processor, performs the steps of the eMMC testing method of embodiment one, embodiment two, embodiment three, embodiment four, or embodiment five.
Example eight
Referring to fig. 3, an electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the steps of the eMMC test method in embodiment one, embodiment two, embodiment three, embodiment four, or embodiment five.
In summary, according to the eMMC test method, the eMMC test device, the readable storage medium, and the electronic device provided by the present invention, the eMMC chip to be tested is subjected to area division according to the received steady-state performance test request of the eMMC chip to be tested and the first preset capacity, so as to obtain the divided eMMC chip to be tested; the method comprises the steps that a steady-state performance test request comprises test indexes, the test indexes comprise an operation time index, a bandwidth index, an IOPS index or a time delay index, a test model is determined according to the test indexes, the test model comprises a sequential read-write model and/or a random read-write model, data read-write operation is conducted on a divided eMMC chip to be tested according to the test model and according to a second preset capacity, data read-write results corresponding to the data read-write operation are stored according to the test indexes, and a steady-state performance test result corresponding to the steady-state performance test request is determined based on the data read-write results; different test models are determined according to different test indexes, data read-write operation is performed on the divided eMMC chips to be tested according to the test models and the second preset capacity, partition test can be performed on the eMMC chips, and flexible eMMC steady-state performance test is achieved; the capacity is used as the testing dimension for testing, whether the steady-state performance of the eMMC chip is normal or not can be tested, whether the steady-state performance falls or not can be accurately known, and compared with a testing method using time as the testing dimension, the testing method is more convenient and faster, the complexity of testing is reduced, and therefore the convenience of testing the steady-state performance can be improved.
In the above embodiments provided in the present application, it should be understood that the disclosed method, apparatus, computer-readable storage medium, and electronic device may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple components or modules may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or components or modules, and may be in an electrical, mechanical or other form.
The components described as separate parts may or may not be physically separate, and parts displayed as components may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the components can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each component may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (10)
1. An eMMC test method, comprising:
receiving a steady-state performance test request of an eMMC chip to be tested;
according to the steady-state performance test request, carrying out region division on the eMMC chip to be tested according to a first preset capacity to obtain the divided eMMC chip to be tested;
performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity, and storing data read-write results corresponding to the data read-write operation;
and determining a steady-state performance test result corresponding to the steady-state performance test request based on the data read-write result.
2. The eMMC test method of claim 1, wherein prior to performing the area division on the eMMC chip under test according to the steady-state performance test request and according to a first preset capacity, the method comprises:
and writing the eMMC chips to be tested for the preset times according to the steady-state performance test request and the first preset test data to obtain the eMMC chips to be tested in a steady state.
3. The eMMC testing method of claim 1 or 2, wherein the steady state performance test request includes a test indicator;
the data reading and writing operation of the divided eMMC chips to be tested according to a second preset capacity and the storage of the data reading and writing results corresponding to the data reading and writing operation comprise:
determining a test model corresponding to the test index according to the test index;
and performing data read-write operation on the divided eMMC chips to be tested according to the test model and a second preset capacity, and storing data read-write results corresponding to the data read-write operation according to the test indexes.
4. The eMMC testing method of claim 3, wherein the test patterns comprise sequential read-write patterns and/or random read-write patterns;
the data read-write operation of the divided eMMC chips to be tested according to the second preset capacity according to the test model comprises the following steps:
sequentially selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the sequential read-write model, and performing sequential read-write operation on the sequentially selected second preset capacity;
and randomly selecting a second preset capacity from each first preset capacity of the divided eMMC chips to be tested according to the random read-write model, and performing random read-write operation on the randomly selected second preset capacity.
5. The eMMC testing method of claim 4, wherein the test metrics include a run time metric;
the determining, according to the test index, a test model corresponding to the test index includes:
and determining a first sequential read-write model and a first random read-write model corresponding to the running time index according to the running time index.
6. The eMMC testing method of claim 4, wherein the test metrics include a bandwidth metric;
the determining, according to the test index, a test model corresponding to the test index includes:
and determining a second sequential read-write model corresponding to the bandwidth index according to the bandwidth index.
7. The eMMC test method of claim 4, wherein the test metric comprises an IOPS metric or a latency metric;
the determining, according to the test index, a test model corresponding to the test index includes:
determining a second random read-write model corresponding to the IOPS index according to the IOPS index;
and determining a third random read-write model corresponding to the time delay index according to the time delay index.
8. An eMMC test device, comprising:
the request receiving module is used for receiving a steady-state performance test request of the eMMC chip to be tested;
the area division module is used for carrying out area division on the eMMC chip to be tested according to the steady-state performance test request and a first preset capacity to obtain the divided eMMC chip to be tested;
the test module is used for performing data read-write operation on the divided eMMC chips to be tested according to a second preset capacity and storing data read-write results corresponding to the data read-write operation;
and the result determining module is used for determining a steady-state performance test result corresponding to the steady-state performance test request based on the data reading and writing result.
9. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of a method for eMMC testing as claimed in any one of claims 1 to 7.
10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of a method for eMMC testing as claimed in any one of claims 1 to 7 when executing the computer program.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115547396A (en) * | 2022-11-30 | 2022-12-30 | 合肥康芯威存储技术有限公司 | Test method and device for eMMC |
| CN117012266A (en) * | 2023-06-30 | 2023-11-07 | 珠海妙存科技有限公司 | Performance test method and device based on EMMC (EMMC management computer) and storage medium thereof |
| CN117935893A (en) * | 2024-03-21 | 2024-04-26 | 成都佰维存储科技有限公司 | EMMC four-corner test method and device, readable storage medium and electronic equipment |
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2022
- 2022-01-10 CN CN202210021369.5A patent/CN114518981A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115547396A (en) * | 2022-11-30 | 2022-12-30 | 合肥康芯威存储技术有限公司 | Test method and device for eMMC |
| CN117012266A (en) * | 2023-06-30 | 2023-11-07 | 珠海妙存科技有限公司 | Performance test method and device based on EMMC (EMMC management computer) and storage medium thereof |
| CN117935893A (en) * | 2024-03-21 | 2024-04-26 | 成都佰维存储科技有限公司 | EMMC four-corner test method and device, readable storage medium and electronic equipment |
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