CN114513211B - Mixed probability LDPC decoder based on full correlation sequence - Google Patents
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract
The invention discloses a mixed probability LDPC decoder based on a full correlation sequence, which relates to the technical field of wireless communication and has the technical scheme that: the channel information initializing module is used for receiving the log-likelihood ratio information of each symbol from the channel, and processing the log-likelihood ratio information into a range which can be represented by probability information to obtain the channel information; the variable node updating module is used for updating the variable nodes according to the channel information and the initial probability information by using an MSA algorithm to obtain variable node updating results; the full-correlation probability information generation module is used for generating full-correlation probability information according to the variable node updating result; and the check node updating module is used for updating the check nodes by using an MSA algorithm according to the fully-correlated probability information to obtain updated probability information, and performing iterative decoding by taking the updated probability information as initial probability information until the decoding requirement is met. The invention has the advantages of good performance, high throughput rate, high hardware efficiency and the like.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a mixed probability LDPC decoder based on a full correlation sequence.
Background
The LDPC code has been one of the most recently focused channel coding schemes because of its performance approaching the shannon limit, and is widely used in various communication standards. The LDPC code is decoded by an iterative decoding algorithm, such as BP (Belief-Propagation) algorithm. During decoding, information alternates and updates between Check nodes (VNs) and Variable Nodes (VNs). Due to the high parallelism of the decoding algorithms, the LDPC decoder can achieve a very high throughput. However, the complex update rules of the processing nodes also incur significant hardware overhead. Meanwhile, congestion caused by connection between processing nodes also occupies a large amount of hardware cost, and when the method is applied to a 5G communication scene of massive connection, the contradiction between area cost and throughput rate becomes a bottleneck of hardware implementation.
Probability computation (Stochastic Computation) characterizes a conventional digital signal with a series of random symbol sequences, and can be implemented with very simple circuitry compared to conventional two's complement characterization. For example, the multiplication may be implemented by a logical AND gate. The probability decoder is an LDPC decoder with low hardware overhead, which is proposed based on probability calculation. The update rules of the processing nodes can be implemented in the probability calculation by simple logic gates, and the wiring between the processing nodes is also greatly reduced in the probability domain.
However, inherent problems of probability calculation, including a decrease in calculation accuracy and a slow convergence speed due to correlation and randomness, also cause degradation of decoding performance of the probability decoder and a longer decoding period. Therefore, how to study and design an LDPC decoder capable of overcoming the above-mentioned drawbacks is a problem that we need to solve at present.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide the mixed probability LDPC decoder based on the full correlation sequence, and the mixed probability LDPC decoder has the advantages of good performance, high throughput rate, high hardware efficiency and the like.
The technical aim of the invention is realized by the following technical scheme: a mixed probability LDPC decoder based on a full correlation sequence, comprising:
the channel information initializing module is used for receiving the log-likelihood ratio information of each symbol from the channel, and processing the log-likelihood ratio information into a range which can be represented by probability information to obtain the channel information;
the variable node updating module is used for updating the variable nodes according to the channel information and the initial probability information by using an MSA algorithm to obtain variable node updating results;
the full-correlation probability information generation module is used for generating full-correlation probability information according to the variable node updating result;
and the check node updating module is used for updating the check nodes by using an MSA algorithm according to the fully-correlated probability information to obtain updated probability information, and performing iterative decoding by taking the updated probability information as initial probability information until the decoding requirement is met.
Further, the channel information initializing module includes:
the saturation unit is used for saturating the channel information to a preset range according to the scaling factor to obtain saturated information;
a scaling unit for scaling the saturated information to the range of [ -1,1] to obtain scaled information suitable for the probability information representation;
and the quantization unit is used for quantizing the scaled information to obtain channel information represented by a preset low-bit-width number.
Further, the value range of the preset low-bit width number is 3-4 bits.
Further, the variable node update module includes:
the cumulative parallel counter is used for accumulating all probability information from the check node updating module in parallel;
a plurality of accumulation counter modules for accumulating each probability information received;
and the subtracter modules are used for subtracting the cumulative sum of all the probability information from the cumulative sum of each probability information to obtain a variable node updating result.
Further, the calculation formula for updating the variable nodes by using the MSA algorithm is specifically as follows:
wherein Q is n→m Information indicating that the variable node n sends to the check node m; l (L) n Representing channel information; p (P) m'→n Information indicating that the check node m' sends to the variable node n; m (n) represents a set of check nodes M' adjacent to variable node n; m (n) \m represents that check node M is removed from this set.
Further, the full correlation probability information generation module includes:
a random number generator module for generating a random number sequence having a specific distribution;
and the comparator module is used for generating a probability bit stream after comparing each input number with the random number.
Further, the check node updating module includes:
the symbol calculation module is used for calculating a symbol part of the result after verification and update;
and the amplitude calculation module is used for calculating an amplitude part of the verification updated result.
Further, the calculation formula for updating the check node by using the MSA algorithm is specifically as follows:
wherein P is m→n Information indicating that the check node m sends to the variable node n; q (Q) n'→m Information indicating that the variable node n' is sent to the check node m; n (m) represents a set of variable nodes N' adjacent to the check node m; n (m) \n represents the variable node N removed from the set; sign () represents a sign operation, and pi represents a product operation.
Furthermore, the decoding requirement is that the decoding reaches the preset maximum iteration number and/or the decoding result meets a decoding equation.
Further, the LDPC decoder is applied to the 10GBASE-T standard.
Compared with the prior art, the invention has the following beneficial effects:
the mixed probability LDPC decoder based on the full correlation sequence combines the characteristics of simple hardware structure and high hardware efficiency of the probability decoder and the high performance advantage of the traditional SPA (Sum-Product Algorithm) decoder, efficiently realizes MSA (Min-Sum Algorithm) and an enhancement Algorithm thereof, improves the performance by at least 0.2dB compared with the existing probability LDPC decoder, approximates to the performance of a floating point OMSA (Offset Min-Sum Algorithm) decoder, and has high throughput rate and hardware efficiency.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
FIG. 1 is a block diagram of the overall structure in an embodiment of the invention;
FIG. 2 is a block diagram of a channel information initialization module according to an embodiment of the present invention;
FIG. 3 is a block diagram illustrating the structure of a variable node update module in accordance with an embodiment of the present invention;
FIG. 4 is a block diagram of the structure of the full correlation probability information generation module in an embodiment of the present invention;
fig. 5 is a block diagram illustrating a structure of a check node update module according to an embodiment of the present invention.
In the drawings, the reference numerals and corresponding part names:
101. a channel information initializing module; 102. a variable node updating module; 103. the full-correlation probability information generation module; 104. a check node updating module; 201. a saturation unit; 202. a scaling unit; 203. a quantization unit; 301. an accumulating parallel counter; 302. an accumulation counter module; 303. a subtracter module; 401. a random number generator module; 402. a comparator module; 501. a symbol calculation module; 502. and an amplitude calculation module.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Examples: the mixed probability LDPC decoder based on the full correlation sequence comprises a channel information initialization module 101, a variable node update module 102, a full correlation probability information generation module 103 and a check node update module 104 as shown in figure 1. The output end of the channel information initialization module 101 is connected with the input end of the variable node update module 102; the input end of the variable node updating module 102 is connected with the input end of the full-correlation probability information generating module 103; the output end of the full correlation probability information generation module 103 is connected with the input end of the check node updating module 104; and an output of the check node update module 104 is connected to an input of the variable node update module 102.
The channel information initializing module 101 is configured to receive log likelihood ratio information of each symbol from the channel, and process the log likelihood ratio information into a range that can be represented by probability information, so as to obtain the channel information. And the variable node updating module 102 is used for updating the variable nodes by using an MSA algorithm according to the channel information and the initial probability information to obtain variable node updating results. And the full-correlation probability information generation module 103 is used for generating full-correlation probability information according to the variable node update result. And the check node updating module 104 is configured to update the check node with an MSA algorithm according to the fully-correlated probability information to obtain updated probability information, and iteratively decode the updated probability information as initial probability information until the decoding requirement is met. It should be noted that the MSA algorithm may be replaced with its enhancement algorithm.
In this embodiment, the decoding requirement satisfies a decoding equation for decoding up to a preset maximum iteration number and/or decoding result.
The mixed probability LDPC decoder based on the full correlation sequence has the highest performance compared with the prior calculation in the LDPC decoding applied to the 10GBASE-T standard, and has the performance loss within 0.1dB compared with the floating point algorithm.
As shown in fig. 2, the channel information initializing module 101 includes a saturation unit 201, a scaling unit 202, and a quantization unit 203.
The saturation unit 201 is configured to saturate the channel information to a preset range according to the scaling factor, and obtain saturated information. A scaling unit 202 for scaling the saturated information to the range of [ -1,1] to obtain scaled information suitable for the probability information representation. A quantization unit 203, configured to quantize the scaled information to obtain channel information represented by a preset low-bit-width number.
In this embodiment, the range of the preset low-level width number is 3-4 bits, and it should be noted that the preset low-level width number may also be set to other values, such as 2 bits, 5 bits, etc., according to the requirement.
Specifically, let the LLR information received from channel n be L n The range is [ - ≡and infinity [ - ≡]To enable it to be represented in the probability domain, L is first of all n Is limited to [ - α, α]Wherein, alpha is a scaling factor, and the specific formula is as follows:
next, L is n The range of (2) is limited to [ -1,1]The specific formula is as follows:
finally, L is n The small bit width number is output to the variable node update module 102.
As shown in fig. 3, the variable node update module 102 includes an accumulation parallel counter 301 (APC, accumulate Parallel Counter), a plurality of accumulation counter modules 302, and a plurality of subtractor modules 303.
Wherein the accumulation parallel counter 301 is configured to accumulate all probability information from the check node update module 104 in parallel. A plurality of accumulation counter modules 302 for accumulating each probability information received. And a plurality of subtractor modules 303, configured to subtract the cumulative sum of all the probability information from the cumulative sum of each probability information to obtain a variable node update result.
Specifically, let variable node receive m update information P from check node represented by probability information 1 ,P 2 ,...,P m Since probability information is serially propagated, at each clock, the variable node receives m 2 bits of information [ sign (P), P (t)]T=1, 2,..i. Where l is the length of the probability sequence. Each clock, the addition tree in the APC adds together the information received at this clock
The output through one clock APC is
The output of the accumulation adder is +.>
Information via subtractor module 303P is jointly represented by sign (P) and P (t), and the output is:
wherein Q is n→m Information indicating that the variable node n sends to the check node m; l (L) n Representing channel information; p (P) m'→n Information indicating that the check node m' sends to the variable node n; m (n) represents a set of check nodes M' adjacent to variable node n; m (n) \m represents that check node M is removed from this set. The updating of the variable nodes is realized, and the result is sent to the full-correlation probability information generation module.
As shown in fig. 4, the full correlation probability information generation module 103 includes a random number generator module 401 and a comparator module 402.
Wherein the random number generator module 401 is configured to generate a random number sequence with a specific distribution; a comparator module 402 for generating a probability bit stream after comparing each input number with a random number per clock.
Specifically, the random number sequence generated by the random number generator module 401 is { R (t) }, t=1, 2, l, at each of the clocks of the time, the output of the comparator is:
wherein Q is i For inputting the information value of the random number generator module 401, the information value representing the information value sent by the variable node to the i-th neighbor check node, i e 1, dv]Dv is the degree of the variable node. Q (Q) i (t) is a random bit stream sequence generated by the random number generator module 401. Since all bit sequences are generated by comparison with the same random number sequence, they are fully correlated. The fully correlated nature ensures that the check node update module 104 can properly implement the check node update of the MSA algorithm.
As shown in fig. 5, the check node update module 104 includes a sign calculation module 501 and an amplitude calculation module 502.
The symbol calculation module 501 is configured to calculate a symbol portion of the updated result; the amplitude calculating module 502 is configured to calculate an amplitude portion of the result after the verification update.
Specifically, the MSA check node update formula may be divided into a sign calculation section and an amplitude calculation section. The probability information is also represented by a combination of sign bits and a probability bit stream. Thus, the update formula of the MSA check node may be implemented by the sign calculation module 501 and the magnitude calculation module 502, respectively.
Symbol +1 is represented by bit 0 and symbol-1 is represented by bit 1, and multiplication between symbols can be achieved by an exclusive or gate, i.e.:
wherein, the liquid crystal display device comprises a liquid crystal display device,
representing modulo-2 addition.
And this rule can be generalized to the multiple input case, so:
the symbol computation module thus implements the symbol portion of the check node update.
Because of adopting the structure of the full-correlation sequence generator, the generated random bit stream is full-correlated, and the amplitude of the probability information is represented by the random bit stream, the minimum value of the amplitude can be obtained by AND gate
Thereby realizing the amplitude value settlement part of the MSA algorithm.
Finally, a calculation formula for updating the check node by using the MSA algorithm is specifically as follows:
wherein P is m→n Information indicating that the check node m sends to the variable node n; q (Q) n'→m Information indicating that the variable node n' is sent to the check node m; n (m) represents a set of variable nodes N' adjacent to the check node m; n (m) \n represents the variable node N removed from the set; sign () represents a sign operation, and pi represents a product operation.
Working principle: the invention combines the characteristics of simple hardware structure and high hardware efficiency of the probability decoder and the high performance of the traditional SPA (Sum-Product Algorithm) decoder, efficiently realizes MSA (Min-Sum Algorithm) and an enhancement Algorithm thereof, improves the performance by at least 0.2dB compared with the traditional probability LDPC decoder, approximates the performance of the floating point OMSA (Offset Min-Sum Algorithm) decoder, and has high throughput rate and hardware efficiency.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. A mixed probability LDPC decoder based on a full correlation sequence, comprising:
a channel information initializing module (101) for receiving log-likelihood ratio information of each symbol from the channel, and processing the log-likelihood ratio information into a range in which probability information can be represented, to obtain channel information;
the variable node updating module (102) is used for updating the variable nodes by using an MSA algorithm according to the channel information and the initial probability information to obtain variable node updating results;
the full-correlation probability information generation module (103) is used for generating full-correlation probability information according to the variable node updating result;
the check node updating module (104) is used for updating the check nodes by an MSA algorithm according to the fully-relevant probability information to obtain updated probability information, and performing iterative decoding by taking the updated probability information as initial probability information until the decoding requirement is met;
wherein the MSA Algorithm is Min-Sum Algorithm.
2. The full correlation sequence based hybrid probability LDPC decoder of claim 1, wherein the channel information initialization module (101) comprises:
a saturation unit (201) for saturating the channel information to a preset range according to the scaling factor to obtain saturated information;
a scaling unit (202) for scaling the saturated information to a range of [ -1,1] to obtain scaled information suitable for the probability information representation;
and a quantization unit (203) for quantizing the scaled information to obtain channel information represented by a preset low-bit-width number.
3. The full correlation sequence based hybrid probability LDPC decoder according to claim 2 wherein the predetermined low bit-width number has a range of 3 to 4 bits.
4. The full correlation sequence based hybrid probability LDPC decoder of claim 1, wherein the variable node update module (102) comprises:
an accumulation parallel counter (301) for accumulating all probability information from the check node update module (104) in parallel;
a plurality of accumulation counter modules (302) for accumulating each probability information received;
and the subtracter modules (303) are used for subtracting the cumulative sum of all the probability information from the cumulative sum of each probability information to obtain a variable node updating result.
5. The mixed probability LDPC decoder according to claim 1 wherein the calculation formula for updating the variable nodes by the MSA algorithm is as follows:
wherein Q is n→m Information indicating that the variable node n sends to the check node m; l (L) n Representing channel information; p (P) m'→n Information indicating that the check node m' sends to the variable node n; m (n) represents a set of check nodes M' adjacent to variable node n; m (n) \m represents that check node M is removed from this set.
6. The full correlation sequence based hybrid probability LDPC decoder of claim 1, wherein the full correlation probability information generation module (103) comprises:
a random number generator module (401) for generating a random number sequence having a specific distribution;
a comparator module (402) for generating a probability bit stream after comparing each input number with a random number per clock.
7. The full correlation sequence based hybrid probability LDPC decoder of claim 1, wherein the check node update module (104) comprises:
a symbol calculation module (501) for calculating a symbol portion of the result after the verification update;
and the amplitude calculation module (502) is used for calculating an amplitude part of the verification updated result.
8. The mixed probability LDPC decoder according to claim 1 wherein the calculation formula for updating the check nodes by the MSA algorithm is as follows:
wherein P is m→n Information indicating that the check node m sends to the variable node n; q (Q) n'→m Information indicating that the variable node n' is sent to the check node m; n (m) represents a set of variable nodes N' adjacent to the check node m; n (m) \n represents the variable node N removed from the set; sign () represents a signed operation, and pi represents a product operation.
9. The full correlation sequence based mixed probability LDPC decoder according to any of claims 1-8, wherein the decoding requirement satisfies a decoding equation for decoding up to a preset maximum number of iterations and/or decoding results.
10. A mixed probability LDPC decoder based on full correlation sequences according to any of claims 1-8, wherein the LDPC decoder is applied to the 10GBASE-T standard.
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