CN114512600A

CN114512600A - Three-dimensional phase change memory and forming method thereof

Info

Publication number: CN114512600A
Application number: CN202210105229.6A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2022-01-28
Filing date: 2022-01-28
Publication date: 2022-05-17

Abstract

The embodiment of the application provides a forming method of a three-dimensional phase change memory and the three-dimensional phase change memory, wherein the method comprises the following steps: etching the first mask stack by using a plurality of initial etching patterns extending along a first direction to form a first etching mask stack; forming a second mask lamination on the surface of the first etching mask lamination; sequentially etching the second mask lamination and the first etching mask lamination by adopting a plurality of secondary etching patterns extending along a second direction to form a secondary etching mask lamination, wherein the secondary etching mask lamination is provided with grid-shaped patterns; and etching the phase change memory unit lamination by taking the secondary etching mask lamination as a mask to form a columnar phase change memory unit.

Description

Three-dimensional phase change memory and forming method thereof

Technical Field

The embodiment of the application relates to the field of semiconductors, and relates to but is not limited to a three-dimensional phase change memory and a forming method thereof.

Background

Phase Change Memory (PCM) is a non-volatile solid-state Memory technology that utilizes reversible, thermally-assisted switching of Phase Change materials between states having different resistances. The phase change material in a PCM cell may be located between two electrodes and a current may be applied to repeatedly switch the phase change material (or portions thereof that block the current path) between the two phases to store data.

In a three-dimensional phase change memory (3D PCM), a memory chip is composed of many memory arrays having individual Word Lines (WL) and Bit Lines (BL). Self-aligned PCM cells are formed at the intersections of mutually perpendicular WLs and BLs in each array, the PCM cells being in the shape of vertical square columns, in contact with the top and bottom BL contacts, the WL being located in the middle of the PCM cell.

In the related art, when a PCM cell is manufactured, a double patterning technology is required to form structures in the WL direction and the BL direction, a plurality of deposition layers are required to be deposited and formed when the structures in the WL direction or the BL direction are formed, partial etching is performed twice respectively, 4 times of partial etching and 8 deposition layers are required to form one PCM cell, and after the etching is completed, redundant deposition layer materials are required to be removed, so that the etching process is very complex. In addition, in the 3D PCM process of forming 2 stacks or 4 stacks, the number of partial etching is increased to 4 or 8 times, and the number of deposition layers formed is also increased by one or four times. That is, as the number of 3D PCM stacks increases, the number of processes for etching may be multiplied, which greatly increases the manufacturing cost.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a method for forming a three-dimensional phase change memory and a three-dimensional phase change memory.

The technical scheme of the embodiment of the application is realized as follows:

the embodiment of the application provides a method for forming a three-dimensional phase change memory, which comprises the following steps: providing a laminated structure; the laminated structure comprises a phase change memory unit laminated layer and a first mask laminated layer which are sequentially stacked;

etching the first mask stack by using a plurality of initial etching patterns extending along a first direction to form a first etching mask stack;

forming a second mask lamination on the surface of the first etching mask lamination;

sequentially etching the second mask lamination and the first etching mask lamination by adopting a plurality of secondary etching patterns extending along a second direction to form a secondary etching mask lamination, wherein the secondary etching mask lamination is provided with grid-shaped patterns;

etching the phase change memory unit lamination by taking the secondary etching mask lamination as a mask to form a columnar phase change memory unit; wherein the first direction and the second direction are perpendicular to each other.

In some embodiments, the laminate structure further comprises: the phase change memory cell comprises a plurality of bit lines extending along the first direction and arranged along the second direction, and at least one bit line contact positioned on each bit line, wherein the bit line contacts are used for connecting the bit lines and the phase change memory cell stacks.

In some embodiments, the first mask stack comprises at least: the mask layer comprises a first mask layer, a second mask layer and a third mask layer which are sequentially stacked from bottom to top;

the first etch mask stack is formed by:

etching the third mask layer based on a plurality of initial etching patterns extending along the first direction to form a third etching mask layer with the initial etching patterns;

etching the second mask layer by taking the third etching mask layer as a mask, and removing the residual third etching mask layer to form a second etching mask layer with the initial etching pattern; wherein the first mask layer and the second etch mask layer form the first etch mask stack.

In some embodiments, the first mask stack further comprises: the first core shaft layer, the first medium layer and the first barrier layer are positioned on the third mask layer and stacked in sequence;

correspondingly, before the etching the third mask layer along the plurality of initial etching patterns extending in the first direction, the method further includes:

patterning the first barrier layer to form a first etching barrier layer;

sequentially etching the first dielectric layer and the first mandrel layer by taking the first etching barrier layer as a mask, and removing the remaining first etching barrier layer to form a first etching mandrel layer;

depositing and forming first spacers positioned at two sides of each first mandrel body in the first etching mandrel layer based on the mandrel pattern of the first etching mandrel layer; wherein the first spacer has the initial etch pattern;

and removing the first etching mandrel layer to form a plurality of initial etching patterns extending along the first direction.

In some embodiments, the third mask layer is etched by:

and etching the third mask layer by taking the first spacing body as a mask to form the third etching mask layer.

In some embodiments, the second mask stack is formed by:

depositing a second mandrel layer, a second dielectric layer and a second barrier layer on the surface of the second etching mask layer in sequence;

the second mandrel layer, the second dielectric layer and the second barrier layer form the second mask lamination.

In some embodiments, the secondary etch mask stack is formed by:

etching the second barrier layer by adopting a plurality of secondary etching patterns extending along the second direction to form a second etching barrier layer;

taking the second etching barrier layer as a mask, sequentially etching the second dielectric layer and the second mandrel layer, and removing the remaining second etching barrier layer to form a second etching mandrel layer;

depositing and forming second spacers positioned at two sides of each second mandrel body in the second etching mandrel layer based on the mandrel pattern of the second etching mandrel layer;

removing the second etching mandrel layer;

and carrying out secondary etching on the first etching mask lamination by taking the second spacer as a mask to form the secondary etching mask lamination.

In some embodiments, the secondary etch mask stack is formed by:

performing secondary etching on the second etching mask layer by taking the second spacer as a mask to form a secondary second etching mask layer;

removing the second spacer; and the first mask layer and the secondary second etching mask layer form the secondary etching mask lamination.

In some embodiments, the secondary etch mask stack is formed by:

sequentially etching the second etching mask layer and the first mask layer by taking the second spacer as a mask to form a second etching mask layer and a first etching mask layer;

removing the second spacer; and the secondary second etching mask layer and the first etching mask layer form the secondary etching mask laminated layer.

In some embodiments, the phase change memory cell stack includes, stacked sequentially from bottom to top: a bottom stack and a top stack;

correspondingly, the phase change memory is obtained by the following steps:

taking the secondary etching mask lamination as a mask, and carrying out first etching on the top lamination to form a top lamination unit;

depositing a first packaging layer on the surface of the top laminated unit;

taking the top lamination unit with the first packaging layer as a mask, and carrying out second etching on the bottom lamination to form a phase change storage unit;

and depositing a second packaging layer on the surface of the phase change memory unit to obtain the columnar phase change memory unit.

In some embodiments, the top laminate comprises, sequentially from bottom to top: a PCM element layer, a first electrode layer and a hard mask layer;

first etching the top stack by:

sequentially carrying out first etching on the hard mask layer, the first electrode layer and the PCM element layer by taking the secondary etching mask lamination as a mask, forming the hard etching mask layer, the first etching electrode layer and the PCM etching element layer after etching, and forming a first through hole penetrating through the hard etching mask layer, the first etching electrode layer and the PCM etching element layer and a top lamination unit positioned around the first through hole;

the depositing and forming of the first packaging layer on the surface of the top lamination unit comprises:

and depositing a first packaging material on the side wall of the first through hole and the surface of the hard etching mask layer to form the first packaging layer.

In some embodiments, the bottom laminate comprises, in order from bottom to top: a third electrode layer, a selector layer and a second electrode layer;

second etching the bottom stack by:

sequentially carrying out second etching on the second electrode layer, the selector layer and the third electrode layer by taking the top laminated unit with the first packaging layer as a mask, forming a second etching electrode layer, an etching selector layer and a third etching electrode layer after etching, and forming a second through hole penetrating through the second etching electrode layer, the etching selector layer and the third etching electrode layer and the phase change memory unit positioned around the second through hole;

depositing and forming a second packaging layer on the surface of the phase change memory unit, wherein the second packaging layer comprises:

and depositing a second packaging material on the side wall of the second through hole and the surface of the phase change memory unit to form the second packaging layer.

In some embodiments, the method further comprises:

filling a gap material on the surface of the second packaging layer to form a gap material layer;

and removing the residual hard etching mask layer in the top lamination layer to expose the first etching electrode layer in the top lamination layer unit.

In some embodiments, the method further comprises:

forming a word line contact on the first etched electrode layer in each exposed top laminated unit;

forming a plurality of word lines extending along the second direction and arranged along the first direction on the word line contacts, thereby forming the phase change memory; the word line contact is used for connecting the first etching electrode layer and the word line, and the material of the word line comprises copper;

alternatively, the first and second electrodes may be,

and forming a plurality of word lines on the exposed first etching electrode layer in each top laminated unit, wherein the material of the word lines comprises tungsten.

The embodiment of the application provides a three-dimensional phase change memory, which is formed by adopting the forming method, and is characterized in that the three-dimensional phase change memory at least comprises: and a columnar phase change memory cell.

In the embodiment of the application, the first mask lamination is etched through the plurality of initial etching patterns extending along the first direction, the second mask lamination and the first etching mask lamination are etched for the second time based on the plurality of secondary etching patterns extending along the second direction, and the secondary etching mask lamination with the grid-shaped patterns is formed, so that the phase change storage unit lamination is etched based on the secondary etching mask lamination, and the phase change storage unit is obtained. Therefore, the number of etching times and the number of deposition layers can be reduced by at least half, and the PCM unit of the three-dimensional phase change memory is formed, so that the process steps are reduced, and the manufacturing cost is reduced.

Drawings

FIGS. 1-2 are schematic structural diagrams of a related art in which bit lines and word lines are formed by double patterning;

fig. 2 is a schematic flowchart illustrating a method for forming a three-dimensional phase change memory according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a stacked structure provided by an embodiment of the present application;

fig. 4-1 to fig. 4-32 are schematic diagrams illustrating a forming process of a three-dimensional phase change memory according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, above and/or below, which may include multiple layers.

In the process of forming the 3D PCM memory in the related art, in conjunction with fig. 1-1 and 1-2, the WL and the BL are formed using a double patterning technique, and it is required to perform partial etching twice and form a plurality of deposition layers to form the WL or the BL, respectively. As shown in fig. 1-1, the structure formed by double patterning in the word line WL direction in the related art is shown in fig. 1-2, which is formed by double patterning in the bit line BL direction, and the number of etching steps is large, which results in a longer process time and an increased process cost.

Based on this, an embodiment of the present application provides a method for manufacturing a three-dimensional phase change memory, and fig. 2 is a flowchart of a method for manufacturing a three-dimensional phase change memory according to an embodiment of the present application, as shown in fig. 2, the method includes:

step S101: providing a laminated structure; the laminated structure comprises a phase change memory cell laminated layer and a first mask laminated layer which are sequentially stacked.

Fig. 3 is a schematic view of a stacked structure provided in an embodiment of the present application, and referring to fig. 3, the stacked structure sequentially includes, from bottom to top: a phase change memory cell stack 120 and a first mask stack 130.

In some embodiments, the laminate structure further comprises: a substrate (not shown in fig. 3) located at the lowermost layer of the stacked structure, and a plurality of bit lines 101 located above the substrate and extending in a first direction.

Here, the substrate may be a silicon substrate, and may also include other semiconductor elements, such as: germanium (Ge), or semiconductor compounds such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP), or indium antimonide (InSb), or including other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), indium aluminum arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP), or combinations thereof.

The substrate may include a top surface at the front side and a bottom surface at the back side opposite the front side; the direction perpendicular to the top and bottom surfaces of the substrate is defined as a third direction, ignoring the flatness of the top and bottom surfaces. In the direction of the top surface and the bottom surface of the substrate (i.e. the plane of the substrate), two first directions and second directions perpendicular to each other are defined, wherein the extending direction along the plurality of bit line structures is the first direction, the arrangement direction of the bit line structures is defined as the second direction, and the plane direction of the substrate can be determined based on the first direction and the second direction. Here, the first direction, the second direction, and the third direction are perpendicular to each other. In this embodiment, the first direction is defined as an X direction, the second direction is defined as a Y direction, and the third direction is defined as a Z direction.

With continued reference to fig. 3, in the embodiment of the present application, the bit lines 101 extending along the X direction may be metal bit lines. These mutually parallel bit lines 101 may be formed by depositing a metal layer, followed by patterning using photolithographic techniques. In some embodiments, the bit line 101 may be formed using copper (Cu), which may be another metal, such as tungsten (W), cobalt (Co), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

In some embodiments, a bit line contact 102 may be further formed on the bit line 101, the bit line contact 102 is used to connect the bit line 101 and the phase-change memory cell stack 120, and the bit line contact is made of a different material than the bit line, and may be a metal such as tungsten. In some embodiments, the bit line contact may also be made of the same material as the bit line, so that the bit line with the contact may be formed directly to further reduce the number of steps for forming the phase change memory.

In some embodiments, the bit lines 101 may be formed while peripheral wiring (not shown in fig. 3) is formed over the substrate. The peripheral wiring may be used to externally connect any digital, analog, and/or mixed signal peripheral device suitable for 3D PCM operation. For example, the peripheral devices may include one or more of data buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, or any active or passive components of circuitry (e.g., transistors, diodes, resistors, or capacitors). The material of the peripheral wiring may be metallic copper to further reduce BL and WL resistance and overall RC delay (RC delay).

Step S102: and etching the first mask stack by adopting a plurality of initial etching patterns extending along the first direction to form a first etching mask stack.

The first mask stack 130 is first etched using a plurality of initial etching patterns extending along the X direction to form a first etching mask stack, where the plurality of initial etching patterns extending along the first direction may be a plurality of etching patterns parallel to the bit lines, and the formed first etching mask stack is used to further form the etching patterns extending along the X direction of the phase change memory.

Step S103: and forming a second mask lamination on the surface of the first etching mask lamination.

And depositing a second mask lamination on the surface of the first etching mask lamination, wherein the second mask lamination is used for forming an etching pattern extending along the Y direction of the phase change memory.

Step S104: and sequentially etching the second mask lamination and the first etching mask lamination by adopting a plurality of secondary etching patterns extending along a second direction to form a secondary etching mask lamination, wherein the secondary etching mask lamination is provided with a grid pattern.

Here, when the patterns of the first etching mask stack having the X-direction etching pattern and the second etching mask stack having the Y-direction etching pattern are merged in the secondary etching mask stack, a grid-like pattern crossing in the X-direction and the Y-direction is formed on the surface of the secondary etching mask stack.

Step S105: etching the phase change memory unit lamination by taking the secondary etching mask lamination as a mask to form a columnar phase change memory unit; wherein the first direction and the second direction are perpendicular to each other.

And etching the phase change memory cell stack 120 by taking the secondarily patterned first mask stack with the grid-shaped pattern as a mask, so that the etched phase change memory cell stack has the same grid-shaped pattern as the secondarily patterned first mask stack to form a columnar phase change memory cell.

In the embodiment of the application, the first mask lamination is etched through the plurality of initial etching patterns extending along the X direction, the second mask lamination and the first etching mask lamination are etched for the second time based on the plurality of secondary etching patterns extending along the Y direction, the secondary etching mask lamination with the grid-shaped patterns is formed, and the phase change memory unit lamination is etched based on the secondary etching mask lamination to form the columnar phase change memory unit. Therefore, the number of etching times and the number of deposition layers can be reduced by at least half, and the PCM unit of the three-dimensional phase change memory is formed, so that the process steps are reduced, and the manufacturing cost is reduced.

The embodiment of the present application further provides a method for manufacturing a three-dimensional phase change memory, where the method includes:

step S201: a stacked structure is provided.

The laminated structure comprises a phase change memory unit laminated layer and a first mask laminated layer which are sequentially stacked along the Z direction; the first mask stack comprises at least: the mask structure comprises a first mask layer, a second mask layer, a third mask layer, a first mandrel layer, a first dielectric layer and a first barrier layer which are sequentially stacked from bottom to top.

Referring to fig. 4-1, a schematic diagram of a stacked structure provided by an embodiment of the present application, a first mask stack 130 in the stacked structure includes: a first mask layer 1301a, a second mask layer 1301b, a third mask layer 1301c, a first mandrel layer 1312, a first dielectric layer 1313, and a first barrier layer 1314 are sequentially stacked in a third direction.

Step S202: and patterning the first barrier layer to form a first etching barrier layer.

First, referring to fig. 4-2, the topmost first barrier layer 1314 of the first mask stack 130 is etched using an etch pattern to form a first etch barrier layer 1314'. Fig. 4-3 is a top view of fig. 4-2, and as shown in fig. 4-3, the first etch stopper 1314' has a plurality of groove patterns parallel to each other along the first direction.

In the embodiment of the present application, the first barrier layer is used for forming the groove pattern, and the first barrier layer may be formed by SiN material deposition.

Step S203: and sequentially etching the first dielectric layer and the first mandrel layer by taking the first etching barrier layer as a mask, and removing the residual first etching barrier layer to form a first etching mandrel layer.

Referring to fig. 4-4, the first dielectric layer 1313 and the first mandrel layer 1312 are sequentially etched along the Z direction by using the first etch stop layer 1314 'as a mask, and the remaining first etch stop layer 1314' is removed to form a first etch dielectric layer 1313 'and a first etch mandrel layer 1312'. The first etching medium layer 1313 'and the first etching mandrel layer 1312' are formed to correspond to a plurality of first mandrel bodies M1, and a groove pattern is formed between every two adjacent first mandrel bodies M1. Fig. 4-5 is a top view of fig. 4-4, and as shown in fig. 4-5, the first dielectric layer 1313 'and the first etching mandrel layer 1312' have a plurality of groove patterns extending in the X direction and parallel to each other in a plane parallel to the substrate.

In the embodiment of the present application, the first dielectric layer may be formed by depositing SiON material; the material of the first mandrel layer may be polysilicon.

Step S204: depositing and forming first spacers positioned at two sides of each first mandrel body in the first etching mandrel layer based on the mandrel pattern of the first etching mandrel layer; wherein the first spacer has the initial etch pattern.

Here, the mandrel pattern of the first etching mandrel layer is a plurality of groove patterns extending in the X direction and parallel to each other formed in step S203. In the embodiment of the present application, referring to fig. 4 to 6, the first spacer may be formed in two ways:

the first method is as follows: a thin film with uniform thickness may be deposited on the entire surface of the semiconductor device on the basis of the plurality of first mandrel bodies M1 formed after etching, covering the mandrel pattern of the first etching mandrel layer; then, oxide/nitride Chemical Mechanical Planarization (CMP) is performed on the surface of the entire semiconductor device to remove the thin film deposited on the surface of the first etching dielectric layer 1313 'and expose the first etching dielectric layer 1313'; then, a mask pattern is formed on the surface of the planarized film and the surface of the first etching dielectric layer 1313', and then the film with a part of the size is etched by using an etching process based on the mask pattern, so that first spacers (spacers) S11, S12 and S13 and etching holes between two adjacent first spacers are obtained.

The second method comprises the following steps: a thin film material may be deposited between adjacent first mandrel bodies M1 on the basis of a plurality of first mandrel bodies M1 formed after etching to form a thin film having a uniform thickness; then, forming a mask pattern on the surface of the film and the first etching medium layer 1313'; and then, based on the mask pattern, etching the film with a part of size by adopting an etching process to obtain the first spacers S11, S12, S13 and the like and an etching hole positioned between two adjacent first spacers.

Fig. 4-7 are top views of fig. 4-6, and as shown in fig. 4-7, the first spacers S11, S12, S13 form an initial etch pattern in a direction perpendicular to the substrate, and the plurality of spacers having the initial etch pattern are used to form a second etch mask layer. Here, the initial etch pattern is a plurality of parallel line features extending in the X direction and arranged in the Y direction.

It should be noted that, in the above two manners, the etching selection ratio of the deposited film material is greater than that of the first dielectric layer material, that is, the etching rate of the film material is much greater than that of the first dielectric layer material under the adopted etching process.

In the embodiments of the present application, the thin film may be formed by any Deposition process, for example, a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a spin coating process, a coating process, or the like may be used. Wherein the material of the deposited layer film may be SiO₂A layer.

Step S205: and removing the first etching mandrel layer to form a plurality of initial etching patterns extending along the first direction.

The top first etching dielectric layer 1313' may be removed using a highly selective etchant, leaving the first spacers S11, S12, S13, forming a plurality of initial etching patterns extending in the X direction. Subsequently, the top portion is processed by a CMP process to remove the first etching mandrel layer 1312' and a portion of the top surface of the first spacers S11, S12, S13, so as to form the first spacers having the initial etching pattern with a flat surface.

Step S206: and etching the third mask layer based on a plurality of initial etching patterns extending along the first direction to form a third etching mask layer with the initial etching patterns.

Step S207: etching the second mask layer by taking the third etching mask layer as a mask, and removing the residual third etching mask layer to form a second etching mask layer with the initial etching pattern; wherein the first mask layer and the second etch mask layer form the first etch mask stack.

Referring to fig. 4-8, the third mask layer 1301c is etched in the Z direction using the first spacers S11, S12, S13 as masks, resulting in a third etched mask layer 1301 c'. Referring to fig. 4-9, the third etching mask layer 1301c 'is used as a mask to continue etching the second mask layer 1301b, so that the second etching mask layer 1301 b' has an initial etching pattern, and the etching is stopped on the first mask layer 1301 a. As shown in fig. 4-9, a first mask layer 1301a and a second etch mask layer 1301b 'form the first etch mask stack 130'. Fig. 4-10 are top views of fig. 4-9, the first etch mask stack 130' having a plurality of initial etch patterns extending in the X-direction.

In some embodiments, the first mask Layer, the second mask Layer, and the third mask Layer may be an Amorphous Carbon Layer (ACL), a Spin-on hard mask Layer (SOH), a polysilicon Layer, or a silicon oxynitride Layer.

In the embodiment of the present application, the first spacer is formed by a Self-aligned Double Patterning (SADP) technique. Because the imaging period in the SADP imaging technology is only half of that of the traditional etching imaging, the cost of the 3D PCM forming process is further reduced.

Step S208: and forming a second mask lamination on the surface of the first etching mask lamination.

As shown in fig. 4-11, a second mask stack 132 is formed on the surface of the first etching mask stack, where the second mask stack 132 includes: a second mandrel layer 1322, a second dielectric layer 1323, and a second barrier layer 1324. The second mask stack 132 is used to form a secondary etch pattern in the Y direction.

In the embodiment of the present application, the second blocking layer 1324 is used to form the secondary etching pattern, and the second blocking layer may be formed by depositing a SiN material.

Step S209: and etching the second barrier layer by adopting the plurality of secondary etching patterns extending along the second direction to form a second etching barrier layer.

Referring to fig. 4-12, the second barrier layer 1324 in the second mask stack is etched in the Z-direction using a plurality of secondary etch patterns extending in the Y-direction, resulting in a second etch barrier layer 1324'. Fig. 4-13 are top views of fig. 4-12, and a plurality of secondary etch patterns extending in the Y direction are formed on the second etch stop layer 1324'.

Step S210: and sequentially etching the second dielectric layer and the second mandrel layer by taking the second etching barrier layer as a mask, and removing the residual second etching barrier layer to form a second etching mandrel layer.

Referring to fig. 4-14, the second etching barrier layer 1324 'is used as a mask to sequentially etch the second dielectric layer 1323 and the second mandrel layer 1322 along the Z direction, and the second etching barrier layer 1324' is removed to form a second etching dielectric layer 1323 'and a second etching mandrel layer 1322'. The second etching medium layer 1323 'and the second etching mandrel layer 1322' correspondingly form a plurality of second mandrel bodies M2, and a groove pattern is formed between every two adjacent second mandrel bodies M2. Fig. 4-15 are top views of fig. 4-14, the second etch dielectric layer 1323 'and the second etch mandrel layer 1322' having a plurality of mutually parallel secondary etch patterns extending in the Y-direction in a plane parallel to the substrate.

In the embodiment of the present application, the material of the second dielectric layer may be SiON; the material of the second mandrel layer may be polysilicon.

Step S211: and depositing and forming second spacers positioned at two sides of each second mandrel body in the second etching mandrel layer based on the mandrel pattern of the second etching mandrel layer.

Here, the mandrel pattern of the second etching mandrel layer is a plurality of mutually parallel secondary etching patterns extending in the Y direction formed in step S210. In the embodiment of the present application, referring to fig. 4 to 16, the second spacers may be formed in the following two ways:

the first method is as follows: a thin film (not shown) with relatively uniform thickness may be deposited on the surface of the entire semiconductor device based on the second mandrel body M2 formed after etching, the second etching pattern is covered by the thin film, and then CMP processing is performed on the surface of the entire semiconductor device to remove the thin film deposited on the surface of the second dielectric layer 1323 and expose the second etching dielectric layer 1323'; then, a mask pattern is formed on the surface of the planarized film and the second etching medium layer 1323', and then the film with a part of size is etched by using an etching process based on the mask pattern, so that second spacers (spacers) S21, S22 and S23 and etching holes located between two adjacent second spacers are obtained.

The second method comprises the following steps: a thin film material can be deposited between the adjacent second mandrel bodies based on the second mandrel bodies M2 formed after etching to form a thin film with uniform thickness; then, forming a mask pattern on the surface of the thin film and the second etching medium layer 1323'; and etching the film with partial size by adopting an etching process based on the mask pattern to obtain second spacers S21, S22 and S23 and an etching hole positioned between two adjacent second spacers.

Fig. 4-17 are top views of fig. 4-16, wherein the second spacers S21, S22, S23 have a second pattern of features, and the second spacers are used to form a second etch mask layer. Here, the second feature pattern is a plurality of parallel line features extending in the Y direction and arranged in the X direction corresponding to the secondary etching pattern.

It should be noted that, in the above two manners, the etching selection ratio of the deposited film material is greater than that of the second dielectric layer material, that is, the etching rate of the film material is much greater than that of the second dielectric layer material under the adopted etching process.

In the embodiments of the present application, the deposited thin film may be formed by any one of deposition processes, for example, a CVD process, a PVD process, an ALD process, a spin coating process, or a coating process. Wherein the material of the deposited layer film may be SiO₂And (3) a layer.

Step S212: removing the second etching mandrel layer; and carrying out secondary etching on the first etching mask lamination by taking the second spacer as a mask to form the secondary etching mask lamination.

And removing the top second etching medium layer 1323' by using a highly selective etching solution, and only remaining the second spacers S21, S22 and S23 to form a plurality of second feature patterns extending along the Y direction. The top portion is then processed using a CMP process to remove the remaining second etched mandrel layer 1322' and portions of the top surface of the second spacers S21, S22, S23, forming second spacers having second feature patterns with a flat surface.

In some embodiments, the second etching is performed on the first etching mask stack in step S212 to form the second etching mask stack, which may be implemented by:

the first method is as follows: taking the second spacer as a mask, and carrying out secondary etching on the second etching mask layer to form a secondary second etching mask layer; and removing the second spacer, wherein the first mask layer and the secondary second etching mask layer form the secondary etching mask lamination.

Referring to fig. 4 to 18, the second etching mask layer 1301 b' is secondarily etched using the second spacers S21, S22, S23 having the second feature pattern as masks, thereby forming a secondary second etching mask layer 1301b ″. The secondary etch mask stack 130 "is comprised of an unetched first mask layer 1201a, and a post-etch secondary second etch mask layer 1301 b". Fig. 4-19 are top views of fig. 4-18, where the secondary second etch mask layer 1301b "has a grid-like pattern in a plane parallel to the substrate.

The second method comprises the following steps: sequentially etching the second etching mask layer and the first mask layer by taking the second spacer as a mask to form a second etching mask layer and a first etching mask layer; removing the second spacer; and the secondary second etching mask layer and the first etching mask layer form the secondary etching mask laminated layer.

Referring to fig. 4 to 20, the second spacers S21, S22, and S23 having the second feature pattern are used as masks, the second etching mask layer 1301b 'is etched for the second time to form a second etching mask layer 1301b ", and the first etching mask layer 1301a is continuously etched to form a first etching mask layer 1301 a'. The secondary etch mask stack 130 "is comprised of a first etch mask layer 1201 a', and a secondary second etch mask layer 1301 b". FIGS. 4-21 are top views of FIGS. 4-20, where the second etching mask layer 1301b "and the first etching mask layer 1301 a' have a grid pattern in a plane parallel to the substrate.

Step S213: and carrying out first etching on the top laminated layer by taking the secondary etching mask laminated layer as a mask to form a top laminated unit.

As shown in fig. 4-22, the phase change memory cell stack 120 includes: a top stack 121 and a bottom stack 122. The top laminate 121 comprises in order in the Z direction: a hard mask layer 1204, a first electrode layer 1201c, a PCM element layer 1203; the bottom laminate 122 includes, in order in the Z direction: a second electrode layer 1201b, a selector layer 1202, and a third electrode layer 1201 a.

Referring to fig. 4 to 23, step S213 is performed, and the secondary etching mask stack is used as a mask, and the hard mask layer 1204, the first electrode layer 1201 and the PCM element layer 1203 are sequentially subjected to a first etching to form a hard etching mask layer 1204 ', a first etching electrode layer 1201 c' and a PCM etching element layer 1203 ', and a first through hole 1 penetrating through the hard etching mask layer 1204', the first etching electrode layer 1201c 'and the PCM etching element layer 1203', and top

stacked unit columns

10, 20 and 30 located around the first through hole and sequentially arranged along the X direction are formed.

Fig. 4-24 are top views of fig. 4-23, where the top stacked cell row 10 includes top

stacked cells

11, 12, 13 sequentially arranged along the Y direction on a plane parallel to the substrate, the top stacked cell row 20 includes top stacked cells 21, 22, 23 sequentially arranged along the Y direction on a plane parallel to the substrate, and the top stacked cell row 30 includes top stacked cell rows 31, 32, 33 sequentially arranged along the Y direction on a plane parallel to the substrate. In the present embodiment, the top laminate unit is configured in the arrangement shown in fig. 4-24 to form a top laminate unit structure.

In the present embodiment, the PCM element is included in the PCM element layer, and the PCM element is typically a chalcogenide material, such as GST (germanium antimony tellurium); the first electrode layer may be a carbon electrode layer; the hard mask layer may be a silicon nitride layer.

Step S214: and depositing and forming a first packaging layer on the surface of the top laminated unit, and carrying out second etching on the bottom laminated unit by taking the top laminated unit with the first packaging layer as a mask to form the phase change memory unit.

Referring to fig. 4 to 25, a first encapsulation material is deposited on the sidewalls of the first via 1 and the surface of the hard etching mask layer 1204' formed in step S213 to form the first encapsulation layer Y1 for protecting the exposed PCM element after etching.

In the embodiment of the present application, the first encapsulant may be a ceramic-based encapsulant, a plastic-based encapsulant, or other encapsulant having an insulating function, which is not limited herein. Disposed in the selector layer is an Ovonic Threshold Switch (OTS), the material of which may include Zn_xTe_y、Ge_xTe_y、Nb_xO_y、Si_xAs_yTe_zAnd the like. The second electrode layer and the third electrode layer may be carbon electrode layers.

Referring to fig. 4 to 26, with the top stacked unit having the first package layer as a mask, performing second etching on the second electrode layer 1201b, the selector layer 1202, and the third electrode layer 1201a in sequence to form a second etched electrode layer 1201b ', an etched selector layer 1202', and a third etched electrode layer 1201a ', and forming a second via 2 penetrating through the second etched electrode layer 1201 b', the etched selector layer 1202 ', and the third etched electrode layer 1201 a', and the phase change

memory cell columns

101, 201, and 301 located around the second via 2. Fig. 4-27 are top views of fig. 4-26, where the phase change

memory cell columns

101, 201, 301 include phase

change memory cells

111, 112, 113, 211, 212, 213, 311, 312, 313, respectively, arranged in sequence in the Y direction parallel to the substrate plane.

Step S215: and depositing and forming a second packaging layer on the surface of the phase change memory unit, and filling a gap material on the surface of the second packaging layer to form a gap material layer.

Referring to fig. 4-28, a second encapsulation material is deposited on the surface of the phase change memory cell to form the second encapsulation layer Y2.

In the embodiment of the present application, the second encapsulation layer Y2 is used to protect the electrode material exposed after etching and the OTS material, and the material of the second encapsulation layer may be a ceramic-based encapsulation material, a plastic-based encapsulation material, or other encapsulation protection materials with an insulating effect, which is not limited herein.

Referring to fig. 4-29, the gap material is filled on the surface of the second encapsulation layer Y2 and in the gap of the second via 2 to form a gap material layer G, in the embodiment of the present application, ALD-ox, SOD or flowing CVD-ox with low thermal conductivity may be used to fill the gap, and in some embodiments, TEO with low conformality may be used to fill the gap to form an air gap.

Step S216: and removing the residual hard etching mask layer in the top lamination layer to expose the first etching electrode layer in the top lamination layer unit.

Referring to fig. 4 to 30, the hard etching mask layer on the top and portions of the first encapsulation layer Y1, the second encapsulation layer Y2 and the gap material layer G on the hard etching mask layer are removed by a CMP process to expose the first etching electrode layer 1201c ', where the exposed first etching electrode layer 1201 c' has a flat structure on a plane parallel to the substrate.

Step S217: forming a word line contact on the first etched electrode layer in each exposed top laminated unit; and forming a plurality of word lines extending along the second direction and arranged along the first direction on the word line contacts, thereby forming the three-dimensional phase change memory.

Referring to fig. 4 to 31, a word line contact 103 is formed on the first electrode layer in each of the exposed top stacked cells, and a plurality of word lines 104 extending in the X direction and arranged in parallel with each other in the Y direction are formed on each of the formed word line contacts to form the three-dimensional phase change memory 300. The three-dimensional phase change memory 300 sequentially includes in the Z direction: bit line 101, bit line contact 102, phase change memory cell 200, word line contact 103, word line 104. Fig. 4-32 are top views of fig. 4-31, the three-dimensional phase change memory 300 having mutually perpendicular word lines 104 and bit lines 101 in a plane parallel to the substrate, and pillar-shaped phase change memory cells 200 between the word lines and bit lines in regions where the mutually perpendicular word lines and bit lines intersect.

The material of the word line contact 103 may be different from the word line 104; alternatively, the material of the word line contact 103 may be the same as the word line 104. When the material of the word line contact 103 is the same as that of the word line 104, the word line may be formed directly on the exposed first etched electrode layer without forming the word line contact.

In some embodiments, the peripheral metal wiring may be formed at the same time as the word lines are formed to further reduce the resistance of the word lines and the overall RC delay.

In the embodiment of the application, the mask lamination is etched twice, and the memory cell lamination is formed in one step during etching, so that the number of mask deposition layers is reduced, the etching process steps are saved, and the manufacturing cost of the 3D PCM is reduced. In some embodiments, using the same material as the word lines to form as the word line contacts may further reduce the molding process of the 3D PCM.

An embodiment of the present application provides a three-dimensional phase change memory, including: phase change memory cells having a grid-like pattern.

In some embodiments, the three-dimensional phase change memory further comprises: a plurality of bit lines extending in the X direction and arranged in the Y direction; at least one bit line contact over the plurality of bit lines, the bit line contact for connecting the bit lines and the phase change memory cell stack.

In some embodiments, the three-dimensional phase change memory further comprises: and the packaging layer is positioned at the periphery of the etched phase change memory unit and comprises: a first packaging layer positioned on the surface of the top laminated unit and a second packaging layer positioned on the surface of the bottom laminated unit; and the gap material layer is positioned on the surface of the second packaging layer.

In some embodiments, the three-dimensional phase change memory further comprises: the word line contact is positioned on the first electrode layer in the top laminated unit, and the word lines are positioned above the word line contact, extend along the Y direction and are arranged along the X direction.

In some embodiments, the three-dimensional phase change memory may further include: a peripheral metal wiring located around the phase-change memory device.

In an embodiment of the present application, a three-dimensional phase change memory is provided, which is formed by using any one of the above methods for forming a three-dimensional phase change memory, and a PCM cell of the three-dimensional phase change memory is formed by half the number of etching times and half the number of film deposition layers, so as to reduce the process steps of the three-dimensional phase change memory and reduce the manufacturing cost of the phase change memory. Meanwhile, the formation of a plurality of copper metal BL and WL further reduces BL and WL resistance and overall RC delay, and the three-dimensional phase change memory also provides peripheral metal wiring formed simultaneously with BL and WL, respectively.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.

The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

The above description is only for some embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the embodiments of the present application, and all the changes or substitutions should be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for forming a three-dimensional phase change memory, the method comprising:

providing a laminated structure; the laminated structure comprises a phase change memory unit laminated layer and a first mask laminated layer which are sequentially stacked;

2. The method of claim 1, wherein the laminate structure further comprises:

the phase change memory cell comprises a plurality of bit lines extending along the first direction and arranged along the second direction, and at least one bit line contact positioned on each bit line, wherein the bit line contacts are used for connecting the bit lines and the phase change memory cell stacks.

3. The method of claim 1, wherein the first mask stack comprises at least: the mask layer comprises a first mask layer, a second mask layer and a third mask layer which are sequentially stacked from bottom to top;

the first etch mask stack is formed by:

4. The method of claim 3, wherein the first mask stack further comprises: the first core shaft layer, the first medium layer and the first barrier layer are positioned on the third mask layer and stacked in sequence;

patterning the first barrier layer to form a first etching barrier layer;

5. The method of claim 4, wherein the third mask layer is etched by:

6. The method of claim 3, wherein the second mask stack is formed by:

7. The method of claim 6, wherein the secondary etch mask stack is formed by:

removing the second etching mandrel layer;

8. The method of claim 7, wherein the secondary etch mask stack is formed by:

taking the second spacer as a mask, and carrying out secondary etching on the second etching mask layer to form a secondary second etching mask layer;

9. The method of claim 7, wherein the secondary etch mask stack is formed by:

10. The method of claim 9, wherein the phase-change memory cell stack comprises, stacked in order from bottom to top: a bottom stack and a top stack;

correspondingly, the phase change memory is obtained by the following steps:

depositing a first packaging layer on the surface of the top laminated unit;

11. The method of claim 10, wherein the top laminate comprises, in bottom-up order: a PCM element layer, a first electrode layer and a hard mask layer;

first etching the top stack by:

12. The method of claim 10, wherein the bottom stack comprises, in order from bottom to top: a third electrode layer, a selector layer and a second electrode layer;

second etching the bottom stack by:

13. The method of claim 12, further comprising:

14. The method of claim 13, further comprising:

forming a word line contact on the exposed first etching electrode layer in each top laminated unit;

alternatively, the first and second electrodes may be,

15. A three-dimensional phase change memory formed by the method for forming a three-dimensional phase change memory according to any one of claims 1 to 14, the three-dimensional phase change memory comprising at least: and a columnar phase change memory cell.