CN114512380B - Preparation method of grid self-aligned vertical nano air channel triode - Google Patents
Preparation method of grid self-aligned vertical nano air channel triode Download PDFInfo
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- CN114512380B CN114512380B CN202210104288.1A CN202210104288A CN114512380B CN 114512380 B CN114512380 B CN 114512380B CN 202210104288 A CN202210104288 A CN 202210104288A CN 114512380 B CN114512380 B CN 114512380B
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Abstract
The invention provides a method for preparing a grid self-aligned vertical nano air channel triode, belonging to the technical field of semiconductor transistors. The preparation method comprises the steps of firstly forming a first table-board on a substrate, then sequentially depositing a dielectric layer and a second table-board, and utilizing the technology of simultaneously depositing the dielectric layer and the second table-board on the substrate with the height difference and the first table-board, so that the self-alignment between a grid electrode and a source drain electrode can be realized, and the precision can reach the nanometer level. The method can quickly and conveniently realize the batch preparation of the wafer-level nanometer air channel triode with large area by adopting the common ultraviolet photoetching and film coating process, can accurately control the length of the nanometer air channel and the distance and the relative position between the grid and the source drain by controlling the thickness of the film coating, and has the advantages of simple and easy operation, high yield, good process consistency and good repeatability.
Description
Technical Field
The invention belongs to the technical field of semiconductor transistors, and particularly relates to a method for preparing a vertical nano air channel triode with a self-aligned grid electrode.
Background
The nanometer air channel transistor combines the advantages of a vacuum electronic device and a solid semiconductor electronic device, hollows a channel for transporting electrons in the traditional solid semiconductor device, and reduces the size of the channel to be below the mean free path of the electrons in the air, so that the electrons can be transported in a trajectory in the hollowed air channel, and the nanometer vacuum transistor or the nanometer air channel transistor which can work without a vacuum environment can be obtained. Compared with the traditional solid semiconductor device, the electronic transportation process of the device is not influenced by solid lattice scattering, so that ultra-high-speed transportation can be realized, the device can work in ultra-high frequency bands such as millimeter waves and terahertz, and the device has a series of advantages of radiation resistance, high and low temperature resistance and the like. Moreover, the nano air channel transistor can be prepared by adopting a semiconductor micro-nano process, so that the nano air channel transistor has the great advantages of miniaturization, high integration level, high yield, large-scale batch production and the like compared with the traditional vacuum electronic device.
The nanometer air channel triode is used as one of core devices in the nanometer air channel transistor, and has important application value in the aspects of power amplifiers, logic circuits, driving circuits and the like. Because the size of a channel between a source electrode and a drain electrode is usually less than hundred nanometers, the most critical and difficult process in the preparation of the nanometer air channel triode is how to accurately place a grid electrode between the source electrode and the drain electrode, so that the regulation and control of electron transportation are realized to the maximum extent. Most of the currently reported nanometer air channel triodes adopt electron beam lithography, focused ion beam etching and other fine nanometer processes to prepare the grid, but the methods highly depend on expensive nanometer processing equipment on one hand, are limited by the process technology on the other hand, the grid alignment precision can only reach about ten nanometers generally, and the yield is low, the process consistency and the repeatability are poor, and large-area batch production cannot be carried out. If a method can be developed, which has the advantages of nanoscale grid alignment precision, low dependence on process equipment and large-area batch production, the performance of the device can be further improved, the preparation cost of the nanometer air channel triode can be greatly reduced, and the practical application of the nanometer air channel triode is promoted.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a method for preparing a vertical nano air channel triode with a self-aligned grid, aiming at providing a method for preparing the nano air channel triode on a large-area wafer in batch, wherein the grid alignment precision can reach the nano level, and the method does not depend on expensive nano processing equipment, has low cost and high yield.
The technical purpose of the invention is realized by the following technical scheme:
a method for preparing a vertical nanometer air channel triode with self-aligned grid is characterized in that when a substrate material is an insulating material or a semi-insulating intrinsic semiconductor, the method comprises the following steps:
s1, forming a first table top on a substrate, wherein the first table top comprises a first conducting layer, and the first conducting layer is used as a source electrode or a drain electrode.
S2, if the projections of the drain electrode and the source electrode of the prepared triode in the vertical direction are not overlapped, S3-1 is carried out; and if the projections of the drain electrode and the source electrode of the prepared triode in the vertical direction are coincident, performing S3-2.
And S3-1, sequentially forming a dielectric layer and a second table top on the substrate and the first table top.
S3-2, forming a sacrificial layer in a partial area above the first conductive layer through photoetching, and then sequentially forming a dielectric layer and a second table top on the substrate, the first table top and the sacrificial layer; or sequentially forming a dielectric layer and a second table-board on the substrate and the first table-board, and then photoetching and etching to expose part of the window of the first conductive layer;
the upper surface of the dielectric layer is higher than the upper surface of the first conductive layer; the second mesa includes a second conductive layer; because of the height difference between the substrate and the first mesa, the higher part of the second conductive layer serves as a drain or a source, and the lower part serves as a gate. The distance between the grid and the upper electrode and the distance between the grid and the lower electrode and the depth of the nano air channel can be accurately controlled by controlling the thicknesses of the dielectric layer, the first table top and the second table top.
S4, corroding the medium layer by a wet method to form a nano air channel, and stripping the sacrificial layer if the sacrificial layer exists; and finishing the preparation of the vertical nano air channel triode.
When the substrate material is a conductive material or a doped semiconductor, the preparation method comprises the following steps:
s1, forming a first table top on a substrate, wherein the first table top comprises a first conducting layer and a first medium layer located between the first conducting layer and the substrate, and the first conducting layer is used as a grid electrode.
S2, sequentially forming a dielectric layer and a second table board on the substrate and the first table board, and exposing a part of a substrate window to be used as a drain electrode or a source electrode; the upper surface of the dielectric layer is higher than the upper surface of the first conductive layer; the second mesa includes a second conductive layer; because of the height difference between the substrate and the first mesa, the lower part of the second conducting layer is used as a drain electrode or a source electrode, and the dielectric layer and the upper part of the second conducting layer are used as sacrificial layers.
And S3, forming a nano air channel by wet etching to finish the preparation of the vertical nano air channel triode.
Preferably, the first mesa and the second mesa are formed by: the pattern is formed by photoetching, and then the pattern is obtained by adopting a dry etching, wet etching or stripping process.
Preferably, the thickness of the first conductive layer and the second conductive layer is 0.1-100nm.
Preferably, the thickness of the dielectric layer is not less than 1nm.
Preferably, the materials of the first conductive layer and the second conductive layer are metal, transparent conductive film, graphene, doped semiconductor thin film, and metalloid.
The invention has the following advantages:
1. the preparation method can realize the self-alignment of the grid electrode, the source electrode and the drain electrode of the nanometer air channel triode. In the vertical direction, the control precision of the distances between the source, the drain and the grid can reach the nanometer level by controlling the thickness of the dielectric layer; in the horizontal direction, the edge of the grid electrode and the source electrode and the edge of the drain electrode are tangent by utilizing the fall of the conductive layer formed by the steps up and down, so that the position precision of the grid electrode in a nano-scale space can realize the efficient regulation and control of the electron transport in a nano-air channel, and the extremely high amplification effect and on-off ratio are achieved. The method provided by the invention does not need to carry out alignment, does not depend on expensive nanometer processing equipment, has low cost, is simple and easy to implement, is suitable for batch production of large-area wafer-level nanometer air channel triode arrays, and has real practicability.
2. The preparation method is suitable for various substrates including insulating substrates, inorganic semiconductors and flexible organic semiconductors, and is generally suitable for nanometer air channel triodes with conductors and semiconductors as source electrodes, drain electrodes and grid electrodes.
Drawings
FIG. 1 is a schematic process flow diagram of a method for fabricating a gate self-aligned vertical nano air channel triode based on a lift-off process; wherein: 10. an insulating substrate; 11. a first conductive layer; 121. a dielectric layer; 122. a second conductive layer; 12A, a metal source/drain; 12B, a metal grid; 13. a nano air channel; 14. and (7) photoresist.
FIG. 2 is a schematic diagram of a process flow of a method for manufacturing a graphene gate self-aligned vertical nano air channel triode based on an etching process; wherein: 20. an insulating substrate; 21. graphene; 220. a first dielectric layer; 221. a dielectric layer; 22A, a graphene source/drain electrode; 22B, a graphene grid; 23. a nano air channel; 24. and (7) photoresist.
FIG. 3 is a method for fabricating a double-sided gate self-aligned vertical nano air channel triode based on a lift-off process; wherein: 30. a semi-insulating intrinsic semiconductor substrate; 31. a grown doped semiconductor film; 321. a dielectric layer; 32A, ITO a transparent conductive film source/drain; 32B, ITO transparent conductive film gate; 33. a nano air channel; 34. and (7) photoresist.
FIG. 4 is a method for fabricating a gate self-aligned vertical nano air channel triode with a conductive substrate as a source/drain; wherein: 40. doping a semiconductor substrate or a conductive substrate; 411. a first dielectric layer; 412. a TiN-like metal film gate; 421. a dielectric layer; 422. TiN-like metal film source/drain electrodes; 43. a nano air channel.
Detailed Description
The technical solution of the present invention is further explained with reference to the drawings and the embodiments.
Example 1
A method for preparing a grid self-aligned vertical nano air channel triode based on a stripping process is disclosed, wherein a substrate in the embodiment is an insulating substrate, and a first table top and a second table top only comprise metal conducting layers, as shown in figure 1, the method for preparing the grid self-aligned vertical nano air channel triode comprises the following steps:
s1, forming a first conducting layer on an insulating substrate to serve as a source electrode or a drain electrode; specifically, the method comprises the following steps:
s1-1, spin-coating a photoresist on the insulating substrate and exposing the area where the first conducting layer is located by adopting ultraviolet photoetching patterning.
S1-2, depositing Au with the thickness of 40nm on the surfaces of the insulating substrate and the photoresist to serve as a first conducting layer.
And S1-3, stripping off the photoresist and Au on the photoresist by using acetone, and forming a source electrode or a drain electrode on the first conductive layer left on the insulating substrate.
S2, forming a sacrificial layer in a partial area above the first conducting layer through photoetching, and then sequentially forming a dielectric layer and a second conducting layer on the substrate, the first conducting layer and the sacrificial layer; specifically, the method comprises the following steps:
s2-1, photoresist is coated on the substrate and the first conducting layer in a spinning mode, and partial areas of the substrate and the first conducting layer are exposed in a patterning mode through ultraviolet lithography.
S2-2, sequentially depositing SiO with the thickness of 60nm on the surfaces of the insulating substrate, the first conducting layer and the photoresist 2 A dielectric layer and a second conductive layer of 20nm Au. At this time, 60nm thick SiO existed between the upper second conductive layer and the lower first conductive layer 2 The two conductive layers form a source and a drain respectively, a grid positioned between the source and the drain in the vertical direction is formed on the substrate on the other side, the intervals between the grid and the source and the drain are all 20nm, and the edges of the grid, the source and the drain are accurately self-aligned in the horizontal direction.
S3, forming a nano air channel by wet etching, and then stripping the photoresist and the dielectric layer and the second conductive layer on the photoresist to complete the preparation of the vertical nano air channel triode; specifically, the method comprises the following steps:
and S3-1, etching by adopting BOE solution to form a nano air channel at the boundary of the edges of the source electrode, the grid electrode and the drain electrode.
And S3-2, removing the photoresist, the dielectric layer and the second conductive layer on the photoresist by adopting acetone stripping, and exposing a window area of the first conductive layer to be used as a source electrode or a drain electrode.
Example 2
A method for manufacturing a graphene gate self-aligned vertical nano air channel triode based on an etching process, wherein a substrate in the embodiment is an insulating substrate, and as shown in FIG. 2, the method comprises the following steps:
s1, forming a first table top on an insulating substrate, wherein the first table top comprises an upper first medium layer and a lower first conductive layer, and the first medium layer is made of SiO 2 The first conducting layer is a graphene film; specifically, the method comprises the following steps:
s1-1, growing or transferring a graphene film and 5nm SiO on an insulating substrate 2 A dielectric layer.
And S1-2, photoetching and etching to form a first table-board.
S2, sequentially forming a dielectric layer and a second table-board on the surfaces of the substrate and the first conductive layer, and then photoetching and etching to expose a window area of the first conductive layer; specifically, the method comprises the following steps:
s2-1, sequentially depositing SiO with the thickness of 10nm 2 And growing a single-layer graphene film as a second conductive layer. At this time, siO with a thickness of 15nm composed of a first dielectric layer and a dielectric layer is present between the first conductive layer and the second conductive layer above the first conductive layer 2 The isolation layer, the second conductive layer above the substrate on the other side, serves as a gate, the spacing between the gate and the lower graphene layer is 10nm, the spacing between the gate and the upper graphene layer is 5nm, and the edges of the gate, the lower graphene layer and the upper graphene layer form accurate self-alignment in the horizontal direction.
And S2-2, photoetching and etching to expose a window area of the first conducting layer.
S3, corroding the medium layer by a wet method to form a nano air channel, stripping off the sacrificial layer, and finishing the preparation of the vertical nano air channel triode; specifically, the method comprises the following steps:
and S3-1, adopting photoresist as a sacrificial layer to protect the junction position of the window region of the first conductive layer and the second table-board.
And S3-2, etching by adopting BOE solution, and forming a nano air channel at the boundary of the edges of the source electrode, the grid electrode and the drain electrode.
And S3-3, stripping off the photoresist by adopting acetone.
Example 3
A method for manufacturing a double-sided gate self-aligned vertical nano air channel triode based on a stripping process is disclosed, wherein a substrate in the embodiment is a semi-insulating intrinsic semiconductor substrate, and as shown in figure 3, the method comprises the following steps:
s1, forming a first conducting layer on a semi-insulating intrinsic semiconductor substrate to serve as a source electrode or a drain electrode; specifically, the method comprises the following steps:
s1-1, photoresist is spin-coated on the semi-insulating intrinsic semiconductor substrate, an area where the middle first conducting layer is located is exposed in a patterning mode through ultraviolet lithography, and then a doped semiconductor thin film with the thickness of 80nm is deposited.
And S1-2, stripping off the photoresist and the doped semiconductor film on the photoresist by using acetone, and leaving a first conductive layer formed by the doped semiconductor film in the middle area of the substrate to be used as a source electrode or a drain electrode.
S2, sequentially forming a dielectric layer and a second conductive layer on the surface of the substrate and the surface of the first conductive layer; specifically, the method comprises the following steps:
sequentially depositing SiO with the thickness of 100nm 2 The dielectric layer and a 40nm second conducting layer, wherein the second conducting layer is an ITO transparent conducting film. At this time, 100nm thick SiO is formed between the doped semiconductor thin film and the ITO transparent conductive thin film thereon 2 The isolation layer, the ITO transparent conductive film above the substrate on both sides forms a grid, the interval between the grid and the lower conductive layer is 20nm, the interval between the grid and the upper conductive layer is 40nm, and the edges of the grid, the ITO transparent conductive film and the upper conductive layer form accurate self-alignment in the horizontal direction.
And S3, etching by adopting a BOE solution, forming a nano air channel at the boundary of the edges of the source electrode, the grid electrode and the drain electrode, and finishing the preparation of the bilateral grid electrode self-aligned vertical nano air channel triode.
Example 4
A method for preparing a grid self-aligned vertical nano air channel triode with a conductive substrate as a source/drain electrode is disclosed, wherein the substrate in the embodiment is a doped semiconductor substrate or a conductive substrate, and as shown in figure 4, the preparation method comprises the following steps:
s1, forming a first table top on a conductive substrate made of a conductive material or a doped semiconductor, wherein the first table top comprises a first dielectric layer and a first conductive layer, and the first conductive layer is a grid; specifically, the method comprises the following steps:
s1-1, depositing a first dielectric layer with the thickness of 20nm and a first conductive layer with the thickness of 30nm on a conductive substrate in sequence, wherein the first dielectric layer is SiO 2 The insulating layer and the first conducting layer are TiN metal conducting films.
And S1-2, forming a first table top by ultraviolet photoetching and etching, wherein the first conducting layer is used as a grid electrode.
And S2, sequentially forming a dielectric layer and a second conductive layer on the substrate and the first table top, and exposing a part of a substrate window to be used as a drain electrode or a source electrode. Specifically, the method comprises the following steps:
s2-1, sequentially depositing SiO with the thickness of 80nm 2 A dielectric layer and a second conductive layer of 200nm, wherein the second conductive layer is a TiN metal conductive film. At this time, 80nm thick SiO was formed between the conductive substrate and the second conductive layer above it 2 The spacing between the isolation layer and the conductive substrate on the other side is 20nm and the spacing between the lower second conductive layer is 30nm, and the edges of the three are precisely self-aligned in the horizontal direction.
And S2-2, carrying out photoetching and double-mesa etching, wherein a part of region exposed out of the first conducting layer is used as a grid window region, and a part of region exposed out of the conducting substrate is used as a source drain window region.
And S3, etching by adopting a BOE solution, forming a nano air channel at the boundary of the edges of the source electrode, the grid electrode and the drain electrode, and finishing the preparation of the vertical nano air channel triode.
Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.
Claims (5)
1. A method for preparing a vertical nanometer air channel triode with self-aligned grid is characterized in that when a substrate material is an insulating material or a semi-insulating intrinsic semiconductor, the method comprises the following steps:
s1, forming a first table top on a substrate, wherein the first table top comprises a first conducting layer which is used as a source electrode or a drain electrode;
s2, if the projections of the drain electrode and the source electrode of the prepared triode in the vertical direction are not overlapped, S3-1 is carried out; if the projections of the drain electrode and the source electrode of the prepared triode in the vertical direction are overlapped, S3-2 is carried out;
s3-1, sequentially forming a dielectric layer and a second table top on the substrate and the first table top;
s3-2, forming a sacrificial layer in a partial area above the first conductive layer through photoetching, and then sequentially forming a dielectric layer and a second table-board on the substrate, the first table-board and the sacrificial layer; or sequentially forming a dielectric layer and a second table-board on the substrate and the first table-board, and then photoetching and etching to expose part of the window of the first conductive layer;
the upper surface of the dielectric layer is higher than the upper surface of the first conductive layer; the second mesa comprises a second conductive layer; because of the height difference between the substrate and the first mesa, the higher part of the second conducting layer is used as a drain electrode or a source electrode, and the lower part of the second conducting layer is used as a grid electrode;
s4, corroding the medium layer by a wet method to form a nano air channel, and stripping the sacrificial layer if the sacrificial layer exists; completing the preparation of the vertical nano air channel triode;
when the substrate material is a conductive material or a doped semiconductor, the preparation method comprises the following steps:
s1, forming a first table top on a substrate, wherein the first table top comprises a first conducting layer and a first medium layer positioned between the first conducting layer and the substrate, and the first conducting layer is used as a grid;
s2, sequentially forming a dielectric layer and a second table board on the substrate and the first table board, and exposing a part of a substrate window to be used as a drain electrode or a source electrode; the upper surface of the dielectric layer is higher than the upper surface of the first conductive layer; the second mesa comprises a second conductive layer; because the height difference exists between the substrate and the first table-board, the lower part of the second conducting layer is used as a drain electrode or a source electrode, and the higher parts of the dielectric layer and the second conducting layer are used as sacrificial layers;
and S3, forming a nano air channel by wet etching to finish the preparation of the vertical nano air channel triode.
2. The method of claim 1, wherein the first mesa and the second mesa are formed by: the pattern is formed by photoetching, and then the pattern is obtained by adopting a dry etching, wet etching or stripping process.
3. The method of claim 1 or 2, wherein the first conductive layer and the second conductive layer have a thickness of 0.1-100nm.
4. The method of claim 3, wherein the dielectric layer has a thickness of not less than 1nm.
5. The method according to claim 1 or 2, wherein the first conductive layer and the second conductive layer are made of metal, transparent conductive film, graphene, doped semiconductor thin film, or metalloid.
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